CN113535499B - Multi-type concurrent access memory stream verification method supporting multi-core shared access - Google Patents
Multi-type concurrent access memory stream verification method supporting multi-core shared access Download PDFInfo
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Abstract
The application discloses a multi-type concurrent access memory flow verification method supporting multi-core shared access, which comprises the steps of obtaining system information of a memory system corresponding to a memory component to be tested, constructing a verification system corresponding to the memory component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models; when the multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction; and respectively determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result. The method and the system realize the functions of request sending, analysis, response processing and the like of each virtual model in a short time, finally judge the correctness of processing, analysis and forwarding of the access storage component to be tested through comparing real and virtual responses, and ensure the correctness of the access storage component to be tested and no errors in streaming by the verification method and the system.
Description
Technical Field
The application relates to the technical field of verification of functional correctness before a central processing unit chip is subjected to silicon, in particular to a multi-type concurrent access memory flow verification method supporting multi-core shared access.
Background
The MEMORY access management component (MBOX) is one of the core components of the high-performance microprocessor, has decisive influence on the performance and efficiency of the computer MEMORY system, and has the main functions of analyzing and forwarding various MEMORY access operations initiated by a plurality of request sources, submitting a plurality of MEMORY access objects for MEMORY access, receiving and managing read response data and returning the read response data to each request source, and being responsible for managing the completion or non-completion of the MEMORY access, wherein the MEMORY access request sources mainly comprise requests of an execution component (EBOX), MEMORY access requests sent by other cores through a local transmission component (TBOX), MEMORY access requests initiated by a maintenance access (IOBOX), and the MEMORY access objects mainly comprise a chip main MEMORY (MEMORY), a local MEMORY (LDM) of the core and a local MEMORY (remote GLDM) of other cores. The main structure block diagram of the response is shown in fig. 1, and the response mainly includes a memory response returned by GLDM through TBOX and a main memory response returned by core management component (SBOX).
MBOX is taken as an important component of a computer storage system, and as the design is more and more complex, the multi-core parallel processing and the distributed shared storage technology are applied, and the characteristics of multiple request sources, multi-cores and multiple access types of the MBOX make functional correctness verification of the MBOX face a plurality of challenges. How to efficiently verify the correctness of the test paper in a valid time and ensure the comprehensiveness and sufficiency of verification become important. The conventional software simulation verification method has the advantages of low cost and easy error, but with the increase of design scale and complexity, the requirements on the number of test vectors and quality are increasing. The traditional software simulation method has the advantages of low running speed, low control force of simulation specific functions, difficult control of time sequences and the like, and the verification can be started only by completely constructing a system in a software simulation verification mode, so that the method has certain defects on the verification efficiency and comprehensiveness.
Disclosure of Invention
In order to solve the above problems, the embodiment of the application provides a multi-type concurrent access memory flow verification method supporting multi-core shared access.
In a first aspect, an embodiment of the present application provides a method for verifying multiple types of concurrent access memory flows supporting multiple core shared accesses, where the method includes:
acquiring system information of a storage system corresponding to a to-be-tested access component, and constructing a verification system corresponding to the to-be-tested access component based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and respectively determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
Preferably, the system information of the storage system corresponding to the access component to be tested is obtained, and a verification system corresponding to the access component to be tested is constructed based on the system information, where the verification system includes a plurality of virtual models, including:
acquiring system information of a storage system corresponding to a memory component to be tested, wherein the system information comprises a memory request source component, a memory object and a response object corresponding to the memory component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can be in one-to-one correspondence and realize the functions of the access request source component, the access object and the response object;
and constructing a verification system corresponding to the access storage component to be tested based on each virtual model.
Preferably, when the multi-source core request instruction is detected, each test stimulus of the multi-source core request instruction is determined, and after the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further comprises:
generating an analog address bit, wherein the analog address bit is used for representing a calling core;
and performing cross-core access memory sharing based on the analog address bits.
Preferably, when the multi-source core request instruction is detected, each test stimulus of the multi-source core request instruction is determined, and after the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further comprises:
and dividing different local memory addresses based on each test stimulus, and generating each control environment parameter corresponding to each local memory address, wherein the control environment parameters are used for controlling the processing time interval of each test stimulus.
Preferably, the determining each virtual model corresponding to each test stimulus separately, and processing the multi-source core request instruction based on each virtual model in parallel to obtain each virtual response result includes:
determining each virtual model corresponding to each test stimulus respectively;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to simulate and generate each storage access based on the multi-source core request instruction, and sending each storage access to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
Preferably, the method further comprises:
when test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training based on the similar sample stimulus set to generate a new virtual model, and adding the new virtual model into the verification system.
In a second aspect, an embodiment of the present application provides a multi-type concurrent access memory flow verification apparatus supporting multi-core shared access, where the apparatus includes:
the system comprises an acquisition module, a verification module and a storage module, wherein the acquisition module is used for acquiring system information of a storage system corresponding to a to-be-detected access component, and constructing a verification system corresponding to the to-be-detected access component based on the system information, wherein the verification system comprises a plurality of virtual models;
the system comprises a determining module, a processing module and a processing module, wherein the determining module is used for determining each test stimulus for sending out a multi-source core request instruction when detecting the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
the processing module is used for respectively determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
In a third aspect, an embodiment of the present application provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method as provided in the first aspect or any one of the possible implementations of the first aspect when the computer program is executed.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as provided by the first aspect or any one of the possible implementations of the first aspect.
The beneficial effects of the application are as follows: when the multisource core request instruction is detected, the functions of request sending, analysis, response processing and the like of each virtual model are realized in a short time by generating complete and efficient test excitation, and finally the correctness of processing, analysis and forwarding of the to-be-detected memory access component is judged by comparing real and virtual responses.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic block diagram of a main structure example of an existing MBOX provided by an embodiment of the present application;
FIG. 2 is a flow chart of a method for verifying multiple types of concurrent accesses supporting multiple cores shared access according to an embodiment of the present application;
FIG. 3 is a schematic block diagram of a main structure example of a verification system according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a multi-type concurrent access memory flow verification device supporting multi-core shared access according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
In the following description, the terms "first," "second," and "first," are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The following description provides various embodiments of the application that may be substituted or combined between different embodiments, and thus the application is also to be considered as embracing all possible combinations of the same and/or different embodiments described. Thus, if one embodiment includes feature A, B, C and another embodiment includes feature B, D, then the present application should also be considered to include embodiments that include one or more of all other possible combinations including A, B, C, D, although such an embodiment may not be explicitly recited in the following.
The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the application. Various examples may omit, replace, or add various procedures or components as appropriate. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
Referring to fig. 2, fig. 2 is a flow chart of a multi-type concurrent access memory flow verification method supporting multi-core shared access according to an embodiment of the present application. In an embodiment of the present application, the method includes:
s101, acquiring system information of a storage system corresponding to a to-be-tested access component, and constructing a verification system corresponding to the to-be-tested access component based on the system information, wherein the verification system comprises a plurality of virtual models.
The execution subject of the present application may be a controller.
The memory component to be tested can be understood as a memory component accessed inside a core of a high-performance microprocessor which needs to be tested in the embodiment of the application.
In the embodiment of the application, since the memory component to be tested is only a part of the memory system which is expected to be put into use, and the rest components in the memory system are required to be matched if the memory component is to be functionally verified, the prior art is to perform a step-by-step operation verification process of the functions of the whole system or the components in a software operation simulation mode after the whole system or the memory component is completely designed, the time consumption of the method in actual situations is very long, the verification time of some complex systems can be as long as a few years, and the method must be required to complete the whole system design so as to start verification, and the verification cannot be performed at all in the system design process. The application obtains the system information in the storage system corresponding to the memory component to be tested, so as to determine the current or expected operation environment of the storage system and the connection mode of other components according to the system information, independently constructs a corresponding verification system based on the system information, and replaces other components in the verification system by virtual models. For example, the generated verification system may be as shown in fig. 3, where VTX is a virtual model corresponding to TBOX, VIO is a virtual model corresponding to IOBOX, VEX is a virtual model corresponding to EBOX, VSX is a virtual model corresponding to SBOX, VLX is a virtual model corresponding to LDM, VGLX is a virtual model corresponding to GLDM, and VMEM is a virtual model corresponding to MEMORY.
In one embodiment, step S101 includes:
acquiring system information of a storage system corresponding to a memory component to be tested, wherein the system information comprises a memory request source component, a memory object and a response object corresponding to the memory component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can be in one-to-one correspondence and realize the functions of the access request source component, the access object and the response object;
and constructing a verification system corresponding to the access storage component to be tested based on each virtual model.
In the embodiment of the application, after the system information of the corresponding storage system is acquired, the information related to the access request source component, the access object, the response object and the like corresponding to the access component to be tested can be determined, the training data can be generated in a targeted manner according to the information, and finally, each virtual model corresponding to each component object one by one can be obtained, and the verification system can be constructed through each virtual model.
S102, when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs.
The multi-source core request instruction can be understood as corresponding instruction information generated when a multi-source core access request occurs in the embodiment of the application.
In the embodiment of the application, after a multi-source core request instruction is detected, in order to perform concurrent response processing on each source in the instruction, each corresponding test stimulus in the instruction needs to be determined based on the instruction.
In one embodiment, when the multi-source core request instruction is detected, each test stimulus of the multi-source core request instruction is determined, and after the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
generating an analog address bit, wherein the analog address bit is used for representing a calling core;
and performing cross-core access memory sharing based on the analog address bits.
In the embodiment of the application, in order to realize cross-core access, each core needs to be identified first, and the application generates simulated address bits to characterize the invoked core. Specifically, the cores are identified in a binary manner, for example, 0001 represents core 1,0010 represents core 2,0011 represents core 3, and so on. After the simulated address bit is determined, the simulated address bit can be used as a cross-core access memory shared address, so that the access memory flow verification process of multi-core shared access is realized.
In one embodiment, when the multi-source core request instruction is detected, each test stimulus of the multi-source core request instruction is determined, and after the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
and dividing different local memory addresses based on each test stimulus, and generating each control environment parameter corresponding to each local memory address, wherein the control environment parameters are used for controlling the processing time interval of each test stimulus.
In the embodiment of the application, different local memory addresses can be divided for each request source for storage, so that the concurrency of multi-source access requests is realized. And through setting and generating corresponding control environment parameters, the interval for transmitting/receiving the request/response is realized, error checking and problem finding are facilitated, and the function of the real memory access component memory access flow can be simulated to the greatest extent.
S103, determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
In the embodiment of the application, after each test excitation is determined, each virtual model suitable for each test excitation operation can be searched and confirmed according to each test excitation, namely, the virtual model corresponding to each test excitation is found, and after all the corresponding processes are completed, the multi-source core request instruction can be processed in parallel based on each virtual model, so that each virtual response result is obtained.
In one embodiment, step S103 includes:
determining each virtual model corresponding to each test stimulus respectively;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to simulate and generate each storage access based on the multi-source core request instruction, and sending each storage access to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
In the embodiment of the application, after the multisource core request instructions are processed in parallel based on each virtual model, a virtual response result directly output by the virtual model can be obtained. The virtual model can simulate and generate storage access based on the multi-source core request instruction, and then the storage access is sent to the access storage component to be tested for direct access processing, so that a real response result is obtained. By comparing the virtual response result with the real response result, the correctness of the memory access component to be tested can be judged.
In one embodiment, the method further comprises:
when test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training based on the similar sample stimulus set to generate a new virtual model, and adding the new virtual model into the verification system.
In the embodiment of the application, because each virtual model in the verification system is constructed based on the current state of the memory access component to be tested, the memory access component to be tested is not necessarily completely designed with all functions at present, and therefore, when a new function is designed later to be verified, the generated virtual model cannot meet the verification requirement of the function. Therefore, when the test stimulus which cannot correspond to any virtual model exists, a similar sample stimulus set is generated according to the data type of the test stimulus, so that a new virtual model is generated through training, and the new virtual model is added into a verification system, so that verification of a new function is added.
The following describes in detail a multi-type concurrent access memory flow verification system supporting multi-core shared access according to an embodiment of the present application with reference to fig. 4. It should be noted that, in the multi-type concurrent access memory flow verification system supporting multi-core shared access shown in fig. 4, for performing the method of the embodiment of fig. 2 of the present application, for convenience of explanation, only the portion relevant to the embodiment of the present application is shown, and specific technical details are not disclosed, please refer to the embodiment of fig. 2 of the present application.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a multi-type memory flow verification device supporting multi-core shared access according to an embodiment of the present application. As shown in fig. 4, the apparatus includes:
the acquisition module 201 is configured to acquire system information of a storage system corresponding to a to-be-detected access component, and construct a verification system corresponding to the to-be-detected access component based on the system information, where the verification system includes a plurality of virtual models;
a determining module 202, configured to determine, when a multi-source core request instruction is detected, each test stimulus that issues the multi-source core request instruction, where the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
the processing module 203 is configured to determine each virtual model corresponding to each test stimulus, and process the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
In one embodiment, the acquisition module 201 includes:
the system information comprises a memory access request source component, a memory access object and a response object corresponding to the memory access component to be tested;
the corresponding function realizing unit is used for generating a plurality of virtual models based on the system information, so that the virtual models can be in one-to-one correspondence and realize the functions of the access request source component, the access object and the response object;
and the verification system construction unit is used for constructing a verification system corresponding to the access storage component to be tested based on each virtual model.
In one embodiment, the apparatus comprises:
the simulated address bit generation module is used for generating simulated address bits, and the simulated address bits are used for representing a calling core;
and the sharing module is used for carrying out cross-core access memory sharing based on the analog address bits.
In one embodiment, the apparatus comprises:
the control environment parameter generation unit is used for dividing different local memory addresses based on the test stimulus and generating the control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test stimulus.
In one embodiment, the processing module 203 includes:
the excitation determining unit is used for determining each virtual model corresponding to each test excitation respectively;
the parallel processing unit is used for processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
the simulation generation unit is used for controlling each virtual model to simulate and generate each storage access based on the multi-source core request instruction, and sending each storage access to the memory access component to be tested to obtain each real response result;
and the comparison unit is used for comparing the virtual response result with the real response result and judging the correctness of the memory access component to be tested.
In one embodiment, the apparatus comprises:
the judging module is used for generating a similar sample excitation set based on the test excitation when the test excitation which cannot correspond to any virtual model exists;
and the adding module is used for generating a new virtual model based on the training of the similar sample excitation set and adding the new virtual model into the verification system.
It will be clear to those skilled in the art that the technical solutions of the embodiments of the present application may be implemented by means of software and/or hardware. "Unit" and "module" in this specification refer to software and/or hardware capable of performing a specific function, either alone or in combination with other components, such as Field programmable gate arrays (Field-Programmable Gate Array, FPGAs), integrated circuits (Integrated Circuit, ICs), etc.
The processing units and/or modules of the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.
Referring to fig. 5, a schematic structural diagram of an electronic device according to an embodiment of the present application is shown, where the electronic device may be used to implement the method in the embodiment shown in fig. 2. As shown in fig. 5, the electronic device 300 may include: at least one central processor 301, at least one network interface 304, a user interface 303, a memory 305, at least one communication bus 302.
Wherein the communication bus 302 is used to enable connected communication between these components.
The user interface 303 may include a Display screen (Display), a Camera (Camera), and the optional user interface 303 may further include a standard wired interface, and a wireless interface.
The network interface 304 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
Wherein the central processor 301 may comprise one or more processing cores. The central processor 301 connects the various parts within the overall electronic device 300 using various interfaces and lines, performs various functions of the terminal 300 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 305, and invoking data stored in the memory 305. Alternatively, the central processor 301 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The central processor 301 may integrate one or a combination of several of a central processor (Central Processing Unit, CPU), an image central processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the cpu 301 and may be implemented by a single chip.
The Memory 305 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 305 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 305 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 305 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-described respective method embodiments, etc.; the storage data area may store data or the like referred to in the above respective method embodiments. The memory 305 may also optionally be at least one storage device located remotely from the aforementioned central processor 301. As shown in fig. 3, an operating system, a network communication module, a user interface module, and program instructions may be included in the memory 305, which is a type of computer storage medium.
In the electronic device 300 shown in fig. 3, the user interface 303 is mainly used for providing an input interface for a user, and acquiring data input by the user; and the central processor 301 may be configured to invoke a multi-type concurrent access flow verification application program supporting multi-core shared access stored in the memory 305, and specifically perform the following operations:
acquiring system information of a storage system corresponding to a to-be-tested access component, and constructing a verification system corresponding to the to-be-tested access component based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and respectively determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method. The computer readable storage medium may include, among other things, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, micro-drives, and magneto-optical disks, ROM, RAM, EPROM, EEPROM, DRAM, VRAM, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on this understanding, the technical solution of the present application may be embodied essentially or partly in the form of a software product, or all or part of the technical solution, which is stored in a memory, and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be performed by hardware associated with a program that is stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic or optical disk, and the like.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a scope and spirit of the disclosure being indicated by the claims.
Claims (8)
1. A method for multi-type concurrent access memory flow verification supporting multi-core shared access, the method comprising:
acquiring system information of a storage system corresponding to a to-be-tested access component, and constructing a verification system corresponding to the to-be-tested access component based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
wherein, when detecting the multi-source core request instruction, after determining to issue each test stimulus of the multi-source core request instruction, the method further comprises:
and dividing different local memory addresses based on each test stimulus, and generating each control environment parameter corresponding to each local memory address, wherein the control environment parameters are used for controlling the processing time interval of each test stimulus.
2. The method of claim 1, wherein the obtaining system information of a storage system corresponding to the to-be-tested access component constructs a verification system corresponding to the to-be-tested access component based on the system information, the verification system including a plurality of virtual models, and the method includes:
acquiring system information of a storage system corresponding to a memory component to be tested, wherein the system information comprises a memory request source component, a memory object and a response object corresponding to the memory component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can be in one-to-one correspondence and realize the functions of the access request source component, the access object and the response object;
and constructing a verification system corresponding to the access storage component to be tested based on each virtual model.
3. The method of claim 1, wherein upon detecting a multi-source core request instruction, determining that each test stimulus of the multi-source core request instruction is issued further comprises:
generating an analog address bit, wherein the analog address bit is used for representing a calling core;
and performing cross-core access memory sharing based on the analog address bits.
4. The method of claim 1, wherein determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model, to obtain each virtual response result, comprises:
determining each virtual model corresponding to each test stimulus respectively;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to simulate and generate each storage access based on the multi-source core request instruction, and sending each storage access to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
5. The method according to claim 1, wherein the method further comprises:
when test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training based on the similar sample stimulus set to generate a new virtual model, and adding the new virtual model into the verification system.
6. A multi-type concurrent access memory flow verification apparatus supporting multi-core shared access, the apparatus comprising:
the system comprises an acquisition module, a verification module and a storage module, wherein the acquisition module is used for acquiring system information of a storage system corresponding to a to-be-detected access component, and constructing a verification system corresponding to the to-be-detected access component based on the system information, wherein the verification system comprises a plurality of virtual models;
the determining module is used for determining each test stimulus for sending out the multi-source core request instruction when the multi-source core request instruction is detected;
the processing module is used for respectively determining each virtual model corresponding to each test stimulus, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
the apparatus further comprises:
the control environment parameter generation unit is used for dividing different local memory addresses based on the test stimulus and generating the control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test stimulus.
7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1-5 when the computer program is executed.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any of claims 1-5.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2045715A1 (en) * | 1990-06-29 | 1991-12-30 | Rebecca L. Stamm | Error transition mode for multi-processor system |
| US5794012A (en) * | 1996-10-09 | 1998-08-11 | Hewlett-Packard Company | Verification of strongly ordered memory accesses in a functional model of an out-of-order computer system |
| CN101446987A (en) * | 2007-11-27 | 2009-06-03 | 上海高性能集成电路设计中心 | Consistency physical verification device of multicore processor Cache |
| WO2012052280A1 (en) * | 2010-10-19 | 2012-04-26 | Siemens Aktiengesellschaft | Method, system, and computer program for automated diagnostic with description logic reasoning |
| CN103150228A (en) * | 2013-02-22 | 2013-06-12 | 中国人民解放军国防科学技术大学 | Synthesizable pseudorandom verification method and device for high-speed buffer memory |
| CN109032879A (en) * | 2017-06-09 | 2018-12-18 | 展讯通信（上海）有限公司 | Multi-core processor memory access Data Detection verifies system and method |
| EP3573073A1 (en) * | 2018-05-22 | 2019-11-27 | Siemens Healthcare GmbH | Method for generating a knowledge base useful in identifying and/or predicting a malfunction of a medical device |
| CN110727611A (en) * | 2019-09-09 | 2020-01-24 | 无锡江南计算技术研究所 | Configurable consistency verification system with state monitoring function |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8731896B2 (en) * | 2009-07-02 | 2014-05-20 | Spirent Communications, Inc. | Virtual testbed for system verification test |
-
2021
- 2021-07-22 CN CN202110829386.7A patent/CN113535499B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2045715A1 (en) * | 1990-06-29 | 1991-12-30 | Rebecca L. Stamm | Error transition mode for multi-processor system |
| US5794012A (en) * | 1996-10-09 | 1998-08-11 | Hewlett-Packard Company | Verification of strongly ordered memory accesses in a functional model of an out-of-order computer system |
| CN101446987A (en) * | 2007-11-27 | 2009-06-03 | 上海高性能集成电路设计中心 | Consistency physical verification device of multicore processor Cache |
| WO2012052280A1 (en) * | 2010-10-19 | 2012-04-26 | Siemens Aktiengesellschaft | Method, system, and computer program for automated diagnostic with description logic reasoning |
| CN103150228A (en) * | 2013-02-22 | 2013-06-12 | 中国人民解放军国防科学技术大学 | Synthesizable pseudorandom verification method and device for high-speed buffer memory |
| CN109032879A (en) * | 2017-06-09 | 2018-12-18 | 展讯通信（上海）有限公司 | Multi-core processor memory access Data Detection verifies system and method |
| EP3573073A1 (en) * | 2018-05-22 | 2019-11-27 | Siemens Healthcare GmbH | Method for generating a knowledge base useful in identifying and/or predicting a malfunction of a medical device |
| CN110727611A (en) * | 2019-09-09 | 2020-01-24 | 无锡江南计算技术研究所 | Configurable consistency verification system with state monitoring function |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
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