CN110266561B

CN110266561B - Portable Space Wire router test system and test method

Info

Publication number: CN110266561B
Application number: CN201910569309.5A
Authority: CN
Inventors: 刘蕾; 刘欢
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2019-06-27
Filing date: 2019-06-27
Publication date: 2022-04-01
Anticipated expiration: 2039-06-27
Also published as: CN110266561A

Abstract

The invention discloses a portable Space Wire router test system and a test method; according to the system, the FPGA is matched with the trigger button and the LED indicator lamp, after the system is powered on, a tester can start testing only by pressing the trigger button, and the LED indicator lamp visually displays whether a testing result is correct or not, so that the practical operability is high. Compared with the traditional board-level test verification platform, the system reduces the test of a PC (personal computer), interface software and complicated physical connection lines, and can carry out the test only by providing a voltage-stabilized power supply. The test system has certain antistatic capacity, is convenient to carry, can be used in various application places, and has strong applicability; the system provides a portable demonstration platform for application and popularization of the Space Wire bus, provides precedent and test verification platforms for a localization road of the Space Wire router, and provides early test verification for the Space Wire bus as a Space bus technology application suitable for an aerospace environment.

Description

Portable Space Wire router test system and test method

[ technical field ] A method for producing a semiconductor device

The invention belongs to the field of reliable and consistent quality of integrated circuits, and relates to a portable Space Wire router test system and a test method.

[ background of the invention ]

The Space Wire bus is a research unit combining European and air administration (ESA) in 2003, develops a set of Space bus standard suitable for aerospace environment based on two commercial standards IEEE 1355-.

LC7910 is a homemade Space Wire router circuit developed in the nuclear high-base subject 200Mbps anti-irradiation high-speed bus control device, provides 8 bidirectional full duplex Space Wire links, has a transmission rate of 2Mbps-200Mbps configurable, 2 external FIFO interfaces, supports path address routing, logical address routing, group adaptation routing, priority arbitration and the like, has a bit error rate of less than or equal to 10-12 (non-irradiation, room temperature), and complies with the ECSS-E-ST-50-12C specification and the RMAP specification. The router functionality is compatible with ATMEL corporation AT 7910E.

In the chip testing stage, the method is limited to the resources of the ATE automatic testing machine and the real environment between tests, and the RMAP command receiving and responding function and the routing function cannot be tested.

[ summary of the invention ]

The invention aims to overcome the defects of the prior art and provides a portable Space Wire router test system and a test method; the system aims at testing the main functions of the LC7910, and comprises RMAP command testing and routing function testing, wherein the two functions are the main functions of a Space Wire router. The test system provides a good test verification platform for application popularization and test of the domestic Space Wire router chip.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

a portable Space Wire router test system comprises a test board and a power supply cable; the power supply cable is used for providing a stabilized voltage power supply transmitted from the outside for the test board; the test plate comprises: the device comprises a power supply module, a clock and reset module, an auxiliary test module, a module to be tested, a button and an indicator light module; the Space Wire router is an LC7910, and the LC7910 is a chip to be tested;

the power supply module is used for providing voltage for the clock and reset module, the auxiliary test module, the module to be tested and the button and indicator light module;

the clock and reset module is used for resetting the tested chip and the auxiliary test module on the tested module and providing a clock signal;

the auxiliary test module is used for receiving a test starting signal sent by the button and indicator light module, sending a test signal to the tested chip, receiving and judging test return data, and inputting a test result to the button and indicator light module;

the tested module is used for fixing the tested chip so that the auxiliary test module tests the tested chip;

and the button and indicator light module is used for sending a test starting trigger level to the auxiliary test module and displaying whether the test result of the auxiliary test module is correct or not.

The invention is further improved in that:

preferably, the power supply module is used for providing +1.0V, +1.8V, +2.5V and + 3.3V.

Preferably, the auxiliary test module comprises a main chip FPGA and a serial memory EEPROM which are connected;

a test program is arranged in the serial memory EEPROM;

after receiving the test signals in the button and indicator light module, the FPGA outputs the test signals to the tested chip of the LC7910 and receives the returned data; the FPGA judges the returned data through a test program input by the EEPROM and outputs a test result to the button and indicator light module.

Preferably, the module to be tested comprises a test socket, a signal pin, a filter capacitor, a pull-up resistor, a pull-down resistor and a matching resistor;

the test socket is used for fixedly placing a chip to be tested in the Space Wire router;

the filter capacitor is used for stabilizing the level input to the tested chip;

the pull-up resistor is used for enabling the level of the signal pin to be in a weak pull-up state;

the pull-down resistor is used for enabling the level of the signal pin to be in a weak pull-down state;

and the matching resistor is used as a terminal resistor of the chip differential signal input end to quickly discharge the parasitic capacitor on the differential bus.

Preferably, the button and indicator light module comprises five test trigger buttons and a plurality of test result lights;

the five test starting buttons comprise four common buttons and a standby button, and the common buttons are respectively used for triggering circuit power-on, link starting, test starting and Space Wire routing circuit power-off in the Space Wire router;

and the test result lamp is used for displaying whether the link test result in the Space Wire router is correct, whether the loading of the test program in the auxiliary test module is finished and the FIFO state in the LC 7910.

A portable Space Wire router test method comprises the following steps:

step 1, after a test system is electrified, an FPGA automatically loads a test program in a matched EEPROM;

step 2, the trigger button sends out a trigger level for starting test, the FPGA receives a trigger instruction, and RMAP command test and routing function test are carried out on a chip to be tested in the LC7910 according to a loaded test program;

step 3, the FPGA receives the returned test data of the LC7910, analyzes and judges the test data, and displays the test result through a result indicating lamp;

and 4, powering off the test system to complete the test.

Preferably, in step 2, the RMAP command test is: performing RMAP command test on the Space Wire link 1, if the RMAP command test result of the Space Wire link 1 is correct, displaying that an indicator lamp of the channel 1 with correct RMAP command test is on, and if the RMAP command test result is wrong, stopping the test; after the testing result of the Space Wire link 1 is correct, starting to perform RMAP command testing on the Space Wire link 2, if the testing result of the RMAP command of the Space Wire link 2 is correct, displaying that an indicator lamp of the channel 2 with correct RMAP command testing is on, and if the testing result is wrong, stopping the testing; sequentially starting RMAP command tests of Space Wire

links

3, 4, 5, 6, 7 and 8; by analogy, if all the RMAP commands of the

links

3, 4, 5, 6, 7, 8 are tested correctly, the indicator light showing that the RMAP command test results of the

channels

3, 4, 5, 6, 7, 8 are correct is on, and if the RMAP command test results are incorrect, the next test is not performed; after the RMAP command test result of the link 8 is correct, starting the RMAP command test of the external port 9, if the RMAP command test of the external port 9 is correct, performing the RMAP command test of the external port 10, and if the RMAP command test of the external port 9 is wrong, not performing the next test; if the RMAP commands of 8 channels and 2 external ports are all completed and correct, indicator lamps which all indicate that the RMAP command test result is correct are lightened, then the RMAP command test result is extinguished, and then the routing function test is carried out.

Preferably, the RMAP command test of each link in the Space Wire comprises the following steps:

(1) the link carries out an RMAP (remote management access point) single-address reading command, accesses a router table and a register with an address range of 0x000-0x109, judges whether a command return packet and a register value are correct or not, and transfers to the step (2) if the command return packet and the register value are correct, and if the command return packet and the register value are wrong, the next step of testing is not carried out;

(2) the link writes a single address command through the RMAP, accesses a router table and a register with the address range of 0x020-0x0ff, judges whether the command return packet is correct, and transfers to the step (3) if the command return packet is correct, and if the command return packet is wrong, the next step of testing is not carried out;

(3) reading and modifying the write command by the link through the RMAP, accessing the router table and the register with the address range of 0x020-0x0ff, judging whether the command return packet and the register value are correct, and if so, turning to the step (3), and if not, not carrying out the next test;

(4) the link reads an address increasing command through the RMAP, accesses a router table and a register with an address range of 0x000-0x109, judges whether a command return packet and a register value are correct or not, and transfers to the step (5) if the command return packet and the register value are correct, and if the command return packet and the register value are wrong, the next step of testing is not carried out;

(5) and the indicator lamp for displaying the RMAP command of the channel and the correct test result is lightened.

Preferably, in step 2, the routing function test includes the following steps: carrying out a routing function test on the Space Wire link 1, if the routing function is correct, displaying that an indication that the routing function test result of the channel 1 is correct is bright, starting the test of the Space Wire link 2, and otherwise, stopping the test; carrying out a routing function test on the Space Wire link 2, if the routing function is correct, displaying an indication of a routing function test result of the channel 2 to be bright, starting a test on the Space Wire link 3, and otherwise, stopping the test; by analogy, the routing function tests of the Space Wire

links

3, 4, 5, 6, 7 and 8 are sequentially carried out, if the routing function tests of the

links

3, 4, 5, 6, 7 and 8 are correct, an indicator lamp for displaying that the routing test results of the

channels

3, 4, 5, 6, 7 and 8 are correct is lightened, and if the routing test results are wrong, the next step of testing is not carried out; if the route function test of the Space Wire link 8 is correct, starting the route function test of the external port 9, if the route of the external port 9 is correct, performing the route function test of the external port 10, and if the route of the external port 9 is wrong, not performing the next test; if the routing function tests of the 8 channels and the 2 external ports are completely finished and correct, all indicator lamps indicating that the routing function tests are correct are all lightened, and then the indicator lamps are turned off; the indicator light that indicates RAMP testing is correct then blinks.

Preferably, each Space Wire link routing function test comprises the following steps:

(1) the FPGA sequentially sends data packet headers of 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09 and 0x0a to the link, the number of the data is 256, and routing packet testing is carried out on data packets of 0x00-0 xFF; turning to the step (2);

(2) sequentially detecting whether the received data packets returned from the LC7910 router are correct at 10 receiving channel ends of the FPGA end, and if the data packets are correct, displaying that an indicator lamp with a correct channel routing function test result is on; if the error is found, the next test is not carried out.

Compared with the prior art, the invention has the following beneficial effects:

the invention discloses a portable Space Wire router test system; according to the system, the FPGA is matched with the trigger button and the LED indicator lamp, after the system is powered on, a tester can start testing only by pressing the trigger button, and the LED indicator lamp visually displays whether a testing result is correct or not, so that the practical operability is high. Compared with the traditional board-level test verification platform, the system reduces the test of a PC (personal computer), interface software and complicated physical connection lines, and can carry out the test only by providing a voltage-stabilized power supply. The test system has certain antistatic capacity, is convenient to carry, can be used in various application places, and has strong applicability. The system provides a portable demonstration platform for application and popularization of the Space Wire bus, provides precedent and test verification platforms for a localization road of the Space Wire router, and provides early test verification for the Space Wire bus as a Space bus technology application suitable for an aerospace environment.

Furthermore, the invention has strong expandability, because the FPGA carries out testing by introducing the program of the EEPROM, the FPGA code can be updated, the testing of other functional items is realized, the flexibility of the FPGA programming is utilized, an external communication serial port is reserved in the testing system according to the testing requirement, a testing PC can be externally expanded, and a more complex testing platform is built.

The invention also discloses a portable Space Wire router test method, which tests the RMAP command receiving response function and the routing function of the Space Wire router LC7910, and the test result is displayed by a result display lamp, so that the whole process is simple and easy to implement, the result can be clearly and visually displayed, the operation is simple, the real operability is strong, and the test result is rapid in response.

[ description of the drawings ]

FIG. 1 is a schematic structural diagram of a portable Space Wire router test system according to the present invention;

FIG. 2 is a schematic diagram of the portable Space Wire router test board according to the present invention.

Wherein: the device comprises a 1-voltage-stabilized power supply, a 2-power supply cable, a 3-test board, a 4-power supply module, a 5-clock and reset module, a 6-auxiliary test module, a 7-tested module and an 8-button and indicator light module.

[ detailed description ] embodiments

The invention is described in further detail below with reference to the figures and the detailed description.

The invention discloses a portable Space Wire router test system; the Space Wire router in the invention is an LC7910, namely the system is used for testing the LC7910, and the whole testing system consists of a testing board 3 and a power supply cable 2. Referring to fig. 1, a power supply cable 2 is used to connect an external regulated power supply 1 to a test board 3; referring to fig. 2, the testing board 3 mainly includes a power supply module 4, a clock and reset module 5, an auxiliary testing module 6, a module under test 7, and a button and indicator light module 8.

Power supply module

The power supply module 4 is used for supplying required voltage to the clock and reset module 5, the auxiliary test module 6, the module to be tested, the button and indicator light module 8 by managing one path of +5V direct current input by the test board 3 through a secondary power supply.

Referring to fig. 2, the power supply module 4 includes a first power management circuit, a high-power module, and a second power management circuit, where the first power management circuit selects a power chip TPS75901, the high-power module selects a power chip PTH08T230, and the second power management circuit selects a power chip TPS 74401; the power supply module 4 can provide voltages of four specifications: +1.0V, +1.8V, +2.5V, + 3.3V; the power supply module 4 comprises JP1, JP2, J8 and J9 jumpers, which are alternative jumpers and comprise 3 pins: 1. 2 and 3, the pin 2 can be selectively connected to the pin 1 or the pin 3 through a jumper cap, so that the switching of the power-on mode is realized.

The FPGA in the auxiliary test module 6 needs to provide +1.0V, +2.5V, +3.3V as core power supply, monitor power supply, and IO power supply, where +1.0V uses the power chip PTH08T230 to supply power, and +2.5V, +3.3V uses 1 power chip TPS75901 to supply power. The EEPROM matched with the FPGA needs to provide +3.3V and +1.8V as kernel power supply and IO power supply, wherein the +3.3V and the FPGA use the same TPS75901 for power supply, and the +1.8V uses a power chip TPS74401 for power supply. After the system is powered on, the power chip simultaneously outputs a plurality of voltages to supply power to the auxiliary test module 6; the LC7910 in the module under test 7 needs to provide +3.3V, +1.8V, each using 1 TPS 75901.

The clock and reset module 5 and the button and indicator light module 8 need to provide +3.3V, and the two modules are connected with the FPAG power supply chip and power is supplied by using a power supply circuit of the FPGA.

The LC7910 is a Space Wire router, so that the influence of different board-level power supply conditions on the chip is explored, the chip can be ensured to be normally powered on to work, and a power supply system is independent; by supplying power through the TPS75901, the LC7910 has three power-on modes, which are respectively as follows:

the first method is as follows: JP1 and

JP2 jumper selections

2 and 3, and J8 and J9 jumper disconnection. At the moment, after the system is powered on at +5V, the TPS75901 of the power supply chip is directly enabled, and simultaneously +3.3V and +1.8V power supplies are output;

the second method comprises the following steps: JP1 jumper selects 1, 2, J8 jumper short circuit; JP2 jumper selects 2, 3, J9 jumper open. At this time, after the +5V power-on of the system, the +3.3V lags behind the +1.8V 57ms output voltage. Similarly, JP1 jumper selects 2, 3, and J8 jumper is disconnected; JP2 jumper selects 1, 2, J9 jumper shorts. At the moment, after the +5V power-on of the system, the +1.8V lags behind the +3.3V 57ms output voltage;

the third method comprises the following steps: JP1 and JP2 jumper selection 1 and 2, and J8 and J9 jumper disconnection, wherein the IO pin of the FPGA can be used for conducting software power-on control, and the power-on sequence and the interval time are controllable.

At present, a test system is powered on in a third use mode.

Clock and reset module

The clock and reset module 5 is used for providing clock reset and software and hardware reset for the test system.

3 crystal oscillator positions are arranged on the test board 3, the FPGA is provided with 2 crystal oscillators, the LC7910 is provided with 1 crystal oscillator, and the LC7910 can also provide clock signals by using the FPGA. The test system currently uses CLK1 to provide a clock signal to the FPGA, and LC7910 uses the clock signal provided by the FPGA.

The power management chip TPS3707-33D is used as a reset chip. And the FPGA and the LC7910 are respectively RESET by pressing RESET buttons RESET1 and RESET2 on the board through hardware. The LC7910 may also be reset by the FPGA software, and the LC7910 software reset signal and the on-board hardware reset button are input to the reset chip via the and gate 54HC08, where a low signal triggers the LC7910 reset to be active.

Third, auxiliary test module 6

The auxiliary test module 6 is used for sending a test instruction to the LC7910, receiving and judging test return data, and displaying whether the test result is correct or not. The test auxiliary module comprises a main chip FPGA (an EEPROM program is loaded into the test auxiliary module, and the FPGA has no function of storing the program), a serial memory EEPROM (the test function of the whole test system can be changed by changing the program in the test auxiliary module), an IO pin and a 1-way 232 serial port.

The FPGA with the model number of XC5VLX85-2FF676I is selected as a main chip of the auxiliary test module 6, and the EEPROM with the model number of XCF32PV0G48C is selected as a serial memory for storing test programs. Introducing all functional signals of the tested chip socket into the FPGA; 5 trigger buttons with initial high in the button and indicator light module 8 are pressed down, a signal is output to the FPGA by outputting low level to the corresponding IO pin of the FPGA, and the FPGA starts to test the LC 7910; and when the corresponding IO pin of the FPGA outputs high or low level, the 16 light-emitting diodes can be lightened or extinguished for displaying the test result.

After the test system is powered on, the FPGA automatically loads a program in the EEPROM, and a tester presses a trigger button on the test board 3: SET1-SET4(SET5 is a spare button) triggers the test procedure. The FPGA receives the trigger instruction, tests the LC7910 according to a pre-loaded test program, receives returned data for analysis and judgment, and visually displays whether the test result is correct or not by lighting or extinguishing an indicator lamp on the test board 3. And 1 path of 232 serial ports are reserved in the FPGA for expansion. Different programs can be input into the FPGA by modifying the programs in the EEPROM, so that the test function of the FPGA is adjusted.

Fourth, the module 7 to be tested

The tested module 7 is used for fixing the LC7910 tested chip, and the tested module 7 comprises a test socket, a signal pin connected with the FPGA, a filter capacitor, a pull-up resistor, a pull-down resistor, a matching resistor and a detection point.

An LY-CQFP-196 connector is selected as a test socket of the LC7910, an LC7910 chip is placed in the socket and locks a socket fixing cover plate, all signal pins are connected with the FPGA, and the power supply pins are 1: 1, a 0.1uF filter capacitor is arranged to ensure the level stability of an LC7910 power supply domain; the pull-up resistor and the pull-down resistor are configured on a Space Wire differential pair signal, the pull-up resistor is used for enabling a positive end of a differential signal to reach a high level faster, the pull-down resistor is used for enabling a negative end of the differential signal to reach a low level faster, and the matching resistor is used for enabling parasitic capacitors on a differential bus to discharge fast, so that signal quality is better.

And matching resistors are arranged between the positive differential signals and the negative differential signals, and the coupling ensures the transmission quality of the differential signals.

And the detection point is used for preliminarily judging the state of the tested circuit, and after the test is started, the oscilloscope is used for carrying out signal observation to preliminarily judge the state of the tested chip.

Fifth, button and indicator light module 8

The button and indicator light module 8 is used for sending out a trigger level for starting the test and displaying a test result.

The test board 3 is provided with 5 initial high test trigger buttons, wherein SET1-SET4 are used for triggering the LC7910 circuit to be tested to be powered on, the link is started, the test is started, the LC7910 circuit is powered off, and the SET5 is used as a standby button. An indicator light LD22 for completing the loading of the FPGA program is arranged on the test board 3, after the system is powered on, the FPGA automatically loads the program in the EEPROM memory, and the LD22 is extinguished to indicate that the program loading is completed. The test board 3 is provided with 2 groups of 8 test result indicator lamps, and the 16 test result indicator lamps are used for displaying whether the Space Wire RMAP command test and the routing function test of the LC7910 circuit pass or not. The test board 3 is also provided with FIFO status indicator lamps LD 23-LD 26 of LC7910 for indicating FIFO status, and can assist judgment when the test result is wrong. LC7910 is equipped with 2 FIFOs, defined as FIFO9, FIFP10, LD23, LD25 lights on, indicating FIFO9 and FIFP10 are full, LD23, LD25 lights off, indicating FIFO9 and FIFP10 are empty; LD24 and LD26 are on, indicating FIFP9 and FIFP10 have data, LD24 and LD26 are off, indicating FIFO9 and FIFO10 are empty.

The test contents of the portable domestic Space Wire router test system comprise various test contents listed in table 1. The test conditions were as follows:

a)TA＝-55℃，VDDA＝VDD33＝3.63V，VDDPLL＝VDDPLLA＝VDD18＝1.98V；

b)TA＝25℃，VDDA＝VDD33＝3.3V，VDDPLL＝VDDPLLA＝VDD18＝1.8V；

c)TA＝125℃，VDDA＝VDD33＝2.97V，VDDPLL＝VDDPLLA＝VDD18＝1.62V；

d) when testing function, FCLK is 30 MHz.

TABLE 1 test items and test purposes

The system can test the RMAP command test and the routing function test in the LC7910, and when the RMAP command test is finished and correct, the routing function test is carried out; the purpose and the steps of the content are as follows:

(1) RMAP Command test:

the test purpose is as follows: the RMAP command of each Space Wire link channel and each external channel is tested to test whether the access to the internal register and the routing table is correct.

Step 1: the Space Wire link 1 carries out RMAP single-address reading command, accesses a router table and a register with the address range of 0x000-0x109, and judges whether the command return packet and the register value are correct or not; turning to the step 2 correctly; if the error is found, the next test is not carried out;

step 2: the Space Wire link 1 writes a single address command through the RMAP, accesses a router table and a register with an address range of (0x020-0x0ff), and judges whether a command return packet is correct or not; turning to the step 3 correctly; if the error is found, the next test is not carried out;

and step 3: the Space Wire link 1 reads and modifies a write command through the RMAP, accesses a router table and a register with the address range of 0x020-0x0ff, and judges whether the command return packet and the register value are correct or not; turning to the step 4 correctly; if the error is found, the next test is not carried out;

and 4, step 4: the Space Wire link 1 reads an address increasing command through the RMAP, accesses a router table and a register with an address range of (0x000-0x109), and judges whether a command return packet and a register value are correct or not; turning to step 5 correctly; if the error is found, the next test is not carried out;

and 5: the FPGA lights up an indicator lamp for displaying a channel 1RMAP command test result to be correct, and the step 6 is carried out;

step 6: starting the RMAP command test of the Space Wire link 2; repeating the steps 1 to 4, however, the link 1 in the steps 1 to 4 is replaced by the link 2, if all the RMAP commands of the link 2 are tested correctly, the indicator light which indicates that the RMAP command test result of the channel 2 is correct is on, and then, turning to the step 7; if the error is found, the next test is not carried out;

and 7: sequentially starting RMAP command tests of Space Wire links 3, 4, 5, 6, 7 and 8; by analogy, if all the RMAP commands of the

links

3, 4, 5, 6, 7, 8 are tested correctly, the indicator light showing that the RMAP commands of the

channels

3, 4, 5, 6, 7, 8 are tested correctly is turned on, and step 8 is performed; if the error is found, the next test is not carried out;

and 8: starting the RMAP command test of the external port 9, if the RMAP command test is correct, carrying out the RMAP command test of the external port 10, and if the RMAP command test is wrong, not carrying out the next test; if the RMAP commands of 8 channels and 2 external ports are all completed and correct, indicator lamps (8 in total) for indicating that the RMAP command test result is correct are lightened up, then the indicator lamps are extinguished, and then the routing function test is carried out, otherwise the next function test is not carried out.

(2) And (3) testing a routing function:

the test purpose is as follows: and testing the routing function of each Space Wire link channel and the external channel.

Step 1: the FPGA sequentially sends the Space Wire link 1 with the data packet headers of 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a and LC7910 to the Space Wire link 1, the data number is 256, and the routing packet test is carried out on the data packets from 0x00 to 0 xFF; turning to the step 2;

step 2: sequentially detecting whether the received data packets routed back from the LC7910 are correct at 10 receiving channel ends of the FPGA end, if so, lightening an indicator lamp indicating that the routing function test result of the channel 1 is correct, and turning to the step 3; if the error is found, the next test is not carried out;

and step 3: the FPGA sequentially sends a Space Wire link 1 with data packet headers of 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09 and 0x0a to the LC7910 to a Space Wire link 2, the data number is 256, and a routing packet test is carried out on data packets from 0x00 to 0 xFF; sequentially detecting whether the received data packets routed back from the LC7910 are correct or not at 10 receiving channel ends of the FPGA end, if so, lightening an indicator lamp for displaying that the routing function test result of the channel 2 is correct, and turning to the step 4; if the error is found, the next test is not carried out;

and 4, step 4: carrying out the routing function tests of the Space Wire links 3, 4, 5, 6, 7 and 8 in sequence according to the method, if the routing function tests of the

links

3, 4, 5, 6, 7 and 8 are correct, lightening an indicator lamp indicating that the routing test results of the

channels

3, 4, 5, 6, 7 and 8 are correct, and turning to the step 5; if the error is found, the next test is not carried out;

and 5: starting the routing function test of the external port 9, and if the routing function test of the external port 10 is correct, carrying out the routing function test; if the error is found, the next test is not carried out; because the external port 9, the result indicator lamp of the external port 10 routing function test and the result indicator lamp of the RMAP command test are the same group of indicator lamps (all indicator lamps of RMAP), and are different from the RMAP command test result indication, the indicator lamp indicating the RMAP command test is correct when the external port 9 and the external port 10 routing function test are correct flashes to represent that the test is correct, and if not, the test is failed; when the RMAP commands to test, if the indicator light is normally on, the test is correct, and if the indicator light is not on, the test is failed; if the routing function tests of the 8 channels and the 2 external ports are completely finished and correct, all indicator lamps indicating that the routing function tests are correct are all lightened, then the indicator lamps are extinguished, and then the RMAP orders all indicator lamps indicating that the tests are correct to start to flicker.

The use flow of the whole test system is as follows:

step 1: the test system adds power, and the test system adds the 5V power, and 3 board electric currents of test panel are after adding power: about 0.7A-0.8A;

step 2: after pressing the power-on button on the test board 3, the LC7910 is powered on, and after power-on the test board 3, the current is: 1.4A-1.5A;

and step 3: after a link starting button on the test board 3 is pressed, all Space Wire links of the LC7910 are in a running state, at the moment, an oscilloscope probe can be used for checking an output detection point on the test board 3, continuous NULL characters which accord with a Space Wire protocol exist, the action serves as an auxiliary judgment circuit function correctness, and at the moment, the current of the whole board is as follows: 1.5A-1.6A;

and 4, step 4: after a test button on the test board 3 is pressed, starting to perform RMAP command test, and if the test result is correct, indicating the result RMAP to instruct a group of indicating lamps with correct test result to be on; and then turning off, starting to perform a routing function test, if the test result is correct, indicating a group of indicator lamps with correct routing function test results to be on, then turning off, and then indicating the RMAP to instruct the indicator lamps with correct routing function test to start flashing, and finishing the whole test process. If the lights are not lit in the order described above, or if the lights are not fully lit, the test result is false.

And 5: after pressing the outage button on testing panel 3, cut off power supply to LC7910, the whole board electric current of outage back is: about 0.7A-0.8A; and (6) completing the test.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A portable Space Wire router test system is characterized by comprising a test board (3) and a power supply cable (2); the power supply cable (2) is used for providing a stabilized voltage power supply (1) transmitted from the outside for the test board (3); the test board (3) comprises: the device comprises a power supply module (4), a clock and reset module (5), an auxiliary test module (6), a module to be tested (7) and a button and indicator light module (8); the Space Wire router is an LC7910, and the LC7910 is a chip to be tested;

the power supply module (4) is used for providing voltage for the clock and reset module (5), the auxiliary test module (6), the module to be tested (7) and the button and indicator light module (8);

the clock and reset module (5) is used for resetting the tested chip on the tested module (7) and the auxiliary test module (6) and providing clock signals;

the auxiliary test module (6) is used for receiving a test starting signal sent by the button and indicator light module (8), sending a test signal to the tested chip, receiving and judging test return data, and inputting a test result to the button and indicator light module (8);

the auxiliary test module (6) comprises a main chip FPGA and a serial memory EEPROM which are connected;

a test program is arranged in the serial memory EEPROM;

after receiving the test signal in the button and indicator light module (8), the FPGA outputs the test signal to the tested chip of the LC7910 and receives the returned data; the FPGA judges the returned data through a test program input by the EEPROM and outputs a test result to a button and indicator light module (8);

the tested module (7) is used for fixing the tested chip so that the auxiliary test module (6) tests the tested chip;

the button and indicator light module (8) is used for sending a test starting trigger level to the auxiliary test module (6) and displaying whether the test result of the auxiliary test module (6) is correct or not;

the system is used for executing a test method and comprises the following steps:

and 4, powering off the test system to complete the test.

2. The portable Space Wire router test system according to claim 1, wherein the power supply module (4) is configured to provide +1.0V, +1.8V, +2.5V and + 3.3V.

3. The portable Space Wire router test system as claimed in claim 1, wherein the module under test (7) comprises a test socket, a signal pin, a filter capacitor, a pull-up resistor, a pull-down resistor and a matching resistor;

4. The portable Space Wire router test system as claimed in claim 1, wherein the button and indicator light module (8) includes five test trigger buttons and a plurality of test result lights;

the five test trigger buttons comprise four common buttons and a standby button, and the common buttons are respectively used for triggering circuit power-on, link starting, test starting and Space Wire routing circuit power-off in the Space Wire router;

and the test result lamp is used for displaying whether the link test result in the Space Wire router is correct, whether the loading of the test program in the auxiliary test module (6) is finished and the FIFO state in the LC 7910.

5. A testing method implemented by the portable Space Wire router testing system of claim 1, wherein in step 2, the RMAP command test is: performing RMAP command test on the Space Wire link 1, if the RMAP command test result of the Space Wire link 1 is correct, displaying that an indicator lamp of the channel 1 with correct RMAP command test is on, and if the RMAP command test result is wrong, stopping the test; after the testing result of the Space Wire link 1 is correct, starting to perform RMAP command testing on the Space Wire link 2, if the testing result of the RMAP command of the Space Wire link 2 is correct, displaying that an indicator lamp of the channel 2 with correct RMAP command testing is on, and if the testing result is wrong, stopping the testing; sequentially starting RMAP command tests of Space Wire links 3, 4, 5, 6, 7 and 8; by analogy, if all the RMAP commands of the links 3, 4, 5, 6, 7, 8 are tested correctly, the indicator light showing that the RMAP command test results of the channels 3, 4, 5, 6, 7, 8 are correct is on, and if the RMAP command test results are incorrect, the next test is not performed; after the RMAP command test result of the link 8 is correct, starting the RMAP command test of the external port 9, if the RMAP command test of the external port 9 is correct, performing the RMAP command test of the external port 10, and if the RMAP command test of the external port 9 is wrong, not performing the next test; if the RMAP commands of 8 channels and 2 external ports are all completed and correct, indicator lamps which all indicate that the RMAP command test result is correct are lightened, then the RMAP command test result is extinguished, and then the routing function test is carried out.

6. The testing method as claimed in claim 5, wherein the RMAP command test of each link in the Space Wire comprises the following steps:

(3) reading and modifying the write command by the link through the RMAP, accessing the router table and the register with the address range of 0x020-0x0ff, judging whether the command return packet and the register value are correct, and if so, turning to the step (4), and if not, not carrying out the next test;

7. The method according to claim 5, wherein in step 2, the routing function test comprises the following steps: carrying out a routing function test on the Space Wire link 1, if the routing function is correct, displaying that an indicator lamp with a correct routing function test result of the channel 1 is on, starting the test of the Space Wire link 2, and otherwise, stopping the test; carrying out a routing function test on the Space Wire link 2, if the routing function is correct, displaying an indication of a routing function test result of the channel 2 to be bright, starting a test on the Space Wire link 3, and otherwise, stopping the test; by analogy, the routing function tests of the Space Wire links 3, 4, 5, 6, 7 and 8 are sequentially carried out, if the routing function tests of the links 3, 4, 5, 6, 7 and 8 are correct, an indicator lamp for displaying that the routing test results of the channels 3, 4, 5, 6, 7 and 8 are correct is lightened, and if the routing test results are wrong, the next step of testing is not carried out; if the route function test of the Space Wire link 8 is correct, starting the route function test of the external port 9, if the route of the external port 9 is correct, performing the route function test of the external port 10, and if the route of the external port 9 is wrong, not performing the next test; if the routing function tests of the 8 channels and the 2 external ports are completely finished and correct, all indicator lamps indicating that the routing function tests are correct are all lightened, and then the indicator lamps are turned off; the indicator light that indicates RAMP testing is correct then blinks.

8. The method for testing as claimed in claim 7, wherein each Space Wire link routing function test comprises the following steps: