CN110264975B

CN110264975B - display panel

Info

Publication number: CN110264975B
Application number: CN201910618462.2A
Authority: CN
Inventors: 黄郁升; 黄圣淼; 陈柏维
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2018-07-10
Filing date: 2019-07-10
Publication date: 2021-05-28
Anticipated expiration: 2039-07-10
Also published as: CN110264975A

Abstract

The present invention provides a display panel, comprising a pixel structure corresponding to a display area and having a plurality of pixels; and a receiving antenna structure disposed in the pixel structure. The receive antenna structure includes antenna blocks. The antenna block includes an antenna and two diodes. The diodes are arranged in parallel and in opposite directions, and are connected to the two switches to provide two mutually opposite clock signals. For each pixel, the switches are alternately on or off in successive frames for a dot inversion drive mode. The scan line extends and crosses the antenna to form a crossover area, and the width of the scan line and the crossover portion can be adjusted to compensate the load of the scan line caused by the antenna of the crossover area.

Description

Display panel

Technical Field

The present invention relates to a display technology, and more particularly, to a display device using an antenna and a scan line for dot inversion driving and signal compensation.

Background

Currently, wireless transmission technology has been applied to signal transmission of display panels. In general, a display panel includes a peripheral non-display region, which is used to set a plurality of Integrated Circuits (ICs) as Data drivers (Data drivers) that supply Data signals (Data signals) to pixels of the display panel. In order to reduce or eliminate the peripheral non-display area, a wireless transmission technique can be applied to transmit data signals to achieve a high data transmission speed and to reduce the loss of the resistance-capacitance delay (RC delay).

However, when the wireless transmission technology is used in a Liquid Crystal Display (LCD) device, in a large-sized (e.g., greater than 85 ") and high-resolution (over 8K) LCD device, a capacitive loading (RC loading) may be important, and it does not have an antenna arrangement that can allow the pixel to perform a dot inversion driving mode. Furthermore, in a display panel having a plurality of Scan lines (Scan lines) for providing pixel Scan signals (Scan signals), the Scan lines generate cross regions (cross areas) with the receiving antennas, thereby increasing the load of the Scan lines. Because each of the scan lines has a different corresponding position with respect to the receiving antenna, the load increase of each of the scan lines should be different, resulting in a significant load difference between the scan lines.

Disclosure of Invention

The present invention provides a display panel including: a pixel structure corresponding to the display area and having a plurality of pixels; and a receiving antenna structure disposed in the pixel structure to provide a first signal to the pixel in a dot inversion driving mode, wherein the receiving antenna structure includes a plurality of antenna blocks, each of the antenna blocks corresponds to M × N pixels among the pixels, the M × N pixels are disposed in M columns and N rows, and M and N are positive integers; wherein each of the antenna blocks includes: an antenna having an inner feed terminal and an outer feed terminal, wherein one of the inner feed terminal and the outer feed terminal is used as a feed terminal, and the other of the inner feed terminal and the outer feed terminal is electrically connected to a DC voltage potential as a reference terminal; a first diode and a second diode, both of which are connected in parallel and electrically connected to the feed-in terminal of the antenna, wherein the first diode and the second diode are arranged in opposite directions; the first switch is electrically connected with the first diode and the M x N pixels, wherein the control end of the first switch is electrically connected with a first clock signal; and a second switch electrically connected to the second diode and the M x N pixels, wherein a control terminal of the second switch is electrically connected to a second clock signal, and a phase of the second clock signal is opposite to a phase of the first clock signal; in each of the M × N pixels, the first switch is turned on and the second switch is turned off in a first frame, and the first switch is turned off and the second switch is turned on in a second frame.

In an embodiment of the invention, each of the antenna blocks further includes a bridge, the M × N pixels are electrically connected to the first switch and the second switch respectively through the bridge, the bridge has a main line and a plurality of branch lines, the main line is electrically connected to the first switch and the second switch respectively, and the branch lines extend from the main line along the row direction and are electrically connected to the M × N pixels.

In an embodiment of the invention, the display panel further includes a common electrode, wherein the reference terminal of the antenna of each of the antenna blocks is electrically connected to the common electrode for receiving the dc voltage potential from the common electrode.

In an embodiment of the invention, the display panel further includes a plurality of scan lines extending across the antenna of the antenna block, wherein the antenna of the antenna block has a plurality of antenna crossing regions, the antenna crossing regions overlap with the scan lines in a direction perpendicular to the pixel structure, and each scan line has a crossing portion, the crossing portion overlaps with the common electrode in the perpendicular direction, and a width of the crossing portion of each scan line is greater than or equal to a width of a remaining portion of each scan line.

In an embodiment of the present invention, the scan lines include a first scan line and a second scan line, the first scan line and the second scan line respectively correspond to a first number and a second number of the antenna crossing regions, the second number is greater than the first number, and a width of the crossing portion of the first scan line is greater than a width of the crossing portion of the second scan line.

In an embodiment of the present invention, the scan lines further include third scan lines, the third scan lines correspond to a third number of the antenna crossing regions, and the third number is greater than the first number and smaller than the second number, and widths of the crossing portions of the third scan lines are respectively greater than widths of the crossing portions of the second scan lines and smaller than widths of the crossing portions of the first scan lines.

In an embodiment of the present invention, a width of the crossing portion of each scan line is determined by a total crossing area of the antenna crossing region corresponding to the crossing portion.

In an embodiment of the present invention, each of the pixels further includes a plurality of scan switches, and a control terminal of each of the scan switches is electrically connected to the corresponding scan line.

In an embodiment of the invention, the display panel further includes a plurality of common electrodes, the reference terminal of each antenna block is electrically connected to one of the common electrodes, and each common electrode has a corresponding dc voltage potential.

In an embodiment of the present invention, the antenna blocks of the antenna block are electrically connected to the different common electrodes respectively.

In an embodiment of the invention, the display panel further includes a plurality of scan lines and a plurality of gate drivers, the gate drivers are electrically connected to the scan lines, and at least one of the gate drivers is disposed in the display area and between two adjacent antenna blocks.

The present invention also provides another display panel, including: a pixel structure corresponding to the display area and having a plurality of pixels; a receiving antenna structure disposed in the pixel structure to provide a first signal to the pixel, wherein the receiving antenna structure comprises a plurality of antennas; a plurality of scan lines extending across the antenna, wherein the antenna has a plurality of antenna cross-over regions overlapping the scan lines in a direction perpendicular to the pixel structure; a common electrode, wherein the scan line has a crossing portion overlapping the common electrode in a vertical direction; wherein the width of the crossing part of each scanning line is larger than or equal to the width of the rest part of each scanning line; the scanning lines further include a first scanning line and a second scanning line, the first scanning line and the second scanning line respectively correspond to a first number and a second number of the antenna crossing regions, the second number is greater than the first number, and the width of the crossing portion of the first scanning line is greater than the width of the crossing portion of the second scanning line.

In an embodiment of the present invention, a central scan line of the scan lines corresponds to a maximum number of the antenna crossing regions, and a width of the crossing portion of the central scan line is equal to a width of the remaining portion of the central scan line.

In an embodiment of the present invention, the common electrode further includes a plurality of strip portions disposed around the antenna, each of the strip portions has a plurality of overlapping portions corresponding to the crossing portions of the scan lines, and a width of each of the overlapping portions is greater than a width of a remaining portion of each of the strip portions.

In an embodiment of the present invention, the scan lines further include a plurality of X scan lines and a plurality of Y scan lines, the X scan lines extend along the column direction, and the Y scan lines extend along the row lines.

In an embodiment of the present invention, the receiving antenna structure further includes a plurality of antenna blocks, each of the antenna blocks corresponds to M × N pixels among the pixels, the M × N pixels are arranged in M columns and N rows, and M and N are positive integers, and each of the antenna blocks further includes: the antenna corresponding to the antenna is provided with an inner feed end and an outer feed end, wherein one of the inner feed end and the outer feed end is used as a feed end, and the other of the inner feed end and the outer feed end is electrically connected with a common voltage for receiving a direct current voltage potential and used as a reference end; a first diode and a second diode, both of which are connected in parallel and electrically connected to the feed-in terminal of the corresponding antenna, wherein the first diode and the second diode are arranged in opposite directions; a first switch electrically connected to the first diode and the M × N pixels, wherein a control terminal of the first switch is electrically connected to a first clock signal; and a second switch electrically connected to the second diode and the M x N pixels, wherein a control terminal of the second switch is electrically connected to a second clock signal, and a phase of the second clock signal is opposite to a phase of the first clock signal; in each of the M × N pixels, the first switch is turned on and the second switch is turned off in a first frame, and the first switch is turned off and the second switch is turned on in a second frame.

In an embodiment of the invention, the display panel further includes a plurality of gate drivers electrically connected to the scan lines, wherein at least one of the gate drivers is disposed in the display region and between two adjacent antenna blocks.

Drawings

Fig. 1A is an exploded perspective view of a display panel of a display device according to an embodiment of the invention.

Fig. 1B is a schematic diagram of a portion of a tft array according to an embodiment of the invention.

Fig. 2A is a schematic diagram illustrating a connection relationship between an antenna matrix formed by a plurality of receiving antenna groups in a receiving antenna structure and corresponding scan lines according to an embodiment of the invention.

Fig. 2B is a schematic diagram illustrating connection among the receiving antenna, the pixel circuit of a specific pixel, and the scan transistor switches corresponding to the pixel according to an embodiment of the invention.

Fig. 3 is a top view of an antenna according to an embodiment of the invention.

Fig. 4A is a schematic diagram of an antenna block of a receiving antenna structure according to an embodiment of the invention.

Fig. 4B is a schematic diagram of the antenna block shown in fig. 4A according to an embodiment of the invention.

Fig. 4C is a schematic diagram illustrating connections among a plurality of pixels, a plurality of scan lines, and bridges in an antenna block according to an embodiment of the invention.

Fig. 5A is a schematic diagram illustrating an antenna block connected to a pixel according to an embodiment of the invention.

Fig. 5B is a timing diagram illustrating a plurality of scanning signals and a plurality of clock signals of the antenna block and the pixel in fig. 5A according to an embodiment of the invention.

FIG. 5C is a schematic diagram illustrating voltage transmission of the pixel in FIG. 5A in the first frame as shown in FIG. 5B when the odd clock signal is turned on according to the embodiment of the present invention.

FIG. 5D is a schematic diagram illustrating voltage transmission of the pixel of FIG. 5A in the first frame of FIG. 5B with the even clock signal on according to one embodiment of the present invention.

Fig. 6 is a schematic diagram of an antenna block of a receiving antenna structure according to an embodiment of the invention.

Fig. 7 is a schematic antenna block diagram of a receiving antenna structure according to yet another embodiment of the invention.

Fig. 8A is a schematic diagram illustrating an intersection region between a receiving antenna and a scan line according to an embodiment of the invention.

Fig. 8B is a schematic diagram illustrating an intersection region between the horizontal receiving antenna and the X scanning lines in fig. 8A according to an embodiment of the invention.

Fig. 8C is a schematic diagram illustrating an intersection region between a part of the vertical receiving antenna and the Y scanning line in fig. 8A according to an embodiment of the invention.

FIG. 8D is a timing diagram illustrating capacitance values of the X-scan lines in FIG. 8A according to an embodiment of the invention.

FIG. 8E is a timing diagram illustrating capacitance values of the Y scan lines in FIG. 8A according to an embodiment of the invention.

Fig. 9 is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line in a display panel according to an embodiment of the invention.

Fig. 10A is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line according to an embodiment of the invention.

Fig. 10B is a schematic diagram illustrating an intersection region between the X-scan line and the horizontal stripe portion of the common electrode in fig. 8A according to an embodiment of the invention.

FIG. 10C is a timing diagram illustrating the compensation region of the X-scan line in FIG. 8A according to an embodiment of the present invention.

FIG. 10D is a timing diagram illustrating the capacitance of the X scan line in FIG. 8A according to an embodiment of the present invention.

FIG. 10E is a timing diagram illustrating the compensation region of the Y scan line in FIG. 8A according to an embodiment of the present invention.

FIG. 10F is a timing diagram illustrating the capacitance of the Y scan line in FIG. 8A according to an embodiment of the invention.

Fig. 11 is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line according to an embodiment of the invention.

Fig. 12A is a timing chart illustrating the X-scan line compensation region corresponding to the bar having five receiving antennas in the case where the number of windings N of each receiving antenna is 12 according to the embodiment of the present invention.

FIG. 12B is a timing diagram illustrating the capacitance of the compensation data of the X-scan line in FIG. 12A according to an embodiment of the present invention.

Fig. 12C is a timing diagram illustrating the Y scan line compensation area corresponding to the row having twelve receive antennas when the number of windings N of each receive antenna is 12 according to the embodiment of the present invention.

FIG. 12D is a timing diagram illustrating the capacitance of the compensation data for the Y scan line of FIG. 12A according to an embodiment of the present invention.

Wherein the reference numerals are:

100. 900: display panel 110: display unit

112: first polarizer 114: color filter layer

116: liquid crystal layer 118: second polarizer

120: thin film transistor array 122: gate driver

124: the data driver 130: transmitting antenna structure

150. 400, 500, 600, 700, 1000: receiving antenna structure

170: the backlight module 200: pixel structure

210: receive antenna matrix 220: x-gate drive array

222: x scan transistor 230: y-gate drive array

232:

y scan transistors

240, 910, 1010, Rx: receiving antenna

252. 254:

circuit modules

300, 412, 810: antenna with a shield

302. 412B: feed-out

end

304, 412A: inner feed end

310: vertical segment 320: horizontal segment

410. 610, 710, 800, 1100: antenna block

414A, 414B, 514A, 514B: diode with a high-voltage source

416A, 416B, 516A, 516B: the switch 418: bridge connector

418M:

main lines

418B, 518B: branch line

420. 720: gate driver X-GOA 430, 732: gate driver Y-GOA

450: pixels 540, 542: scanning transistor

550: capacitances 560, 570: period of time

820. 830, 840: antenna crossover region

1020. 1022, 1024, 1026, 1028, 1032, 1033, 1034, 1036, 1038, 1120, 1122, 1124, 1126, 1128, 1130, 1132, 1134, 1136, 1138: cross over part, overlap part

D1, D2, D3: data lines G1, G2, G3: gate line

Tx: transmitting antennas X1-Xm, Y1-Yn: scanning line

Odd _ CK: odd clock signal Even _ CK: even clock signal

V_COM、V_COM-1、V_COM-2、V_COM-3: potential of DC voltage

V_pixel: voltage Δ V of pixel: voltage difference

F1: first picture frame F2: second picture frame

BLK: blank periods W1, W30: width of

Detailed Description

The embodiments of the invention presented will be apparent from the description and drawings of embodiments thereof, and other variations and modifications which do not depart from the spirit and scope of the novel concept are intended to be covered by the invention.

The following detailed description of the embodiments of the present invention will be better understood when read in conjunction with the appended drawings, which are not intended to limit the scope of the invention, but rather to limit the sequence of operations performed by the embodiments, and any structures resulting from the rearrangement of elements, which have equivalent functions, are intended to cover the scope of the invention. Moreover, the drawings are for illustrative purposes only and are not drawn to scale in accordance with established standards and practice in the industry, and the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. In the following description, like elements will be described with like reference numerals for ease of understanding.

The words (terms) used throughout the specification and claims have the ordinary meaning as commonly understood in the art, in the context of the invention, and in the specific context, unless otherwise indicated. Certain words used to describe the invention are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention. For convenience, certain terms may be identified in a significant manner, such as by using italics and/or quotation marks. The manner of usage of the significant indicia has no effect on the scope and meaning of the terms; the scope and meaning of terms, whether or not expressly disclosed, are the same in the same context. It should be understood that the same thing can be discussed in more than one way. Thus, alternative language and synonyms may be used for any one or more of the terms discussed herein, and have no special meaning as to whether a term is set forth or discussed in detail herein. Synonyms for certain terms are provided. Recitation of one or more synonyms does not exclude the use of other synonyms. The implementations presented herein are for illustration only and in no way limit the scope and meaning of the invention or any other exemplary terms. As such, the present invention is not limited to the various embodiments set forth in this specification.

Also, when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in mutual engagement or interaction. Furthermore, although terms such as "first," "second," etc. may be used herein to describe various elements, such terms are used only to distinguish one element or operation from another element or operation described in the same technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer or imply an order or sequence nor are they intended to limit the invention.

Furthermore, as used herein, the terms "comprising," including, "" having, "" containing, "and the like are open-ended terms, i.e., mean" including, but not limited to. Further, as used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

Also, as used herein, comparative words such as "lower," "bottom," "upper," "top," "left," or "right," etc., are used merely to illustrate the illustrations in the embodiments referenced herein. Relative terms of orientation other than the orientation shown in the drawings are intended to be encompassed. For example, if the device is turned over in the drawings, the description of one element relative to another may vary from "lower" to "higher". Wherein the term "lower" may include two directional orientations, "lower" and "higher," depending only on the orientation of the figure. Similarly, if the device is turned over in the drawings, the description of one element relative to another may refer to "lower" or "lower" as opposed to "upper". The terms "lower" or "below" and the like may include two orientations in the up or down direction.

The terms "about", "approximately" and the like as used herein are generally expressed as being within 20%, or preferably within 10%, or more preferably within 5% of a constant or average value. Numerical values set forth herein are approximations that may be calculated to mean "about", "approximately", and the like.

The feeding end of the receiving antenna is referred to as the actual feeding end and is electrically connected to the corresponding signal line. Generally, a receiving antenna has an external feed terminal and an internal feed terminal, wherein one of the external feed terminal and the internal feed terminal is used as a "feed terminal", and the other of the external feed terminal and the internal feed terminal is used as a ground or is electrically connected to a reference voltage potential (e.g., a common voltage V provided by a common electrode)_COM)。

The embodiments described herein are described in conjunction with the figures. For the purposes of this document, a display panel and a display device for wireless signal transmission according to the present invention will be described in a specific and broad manner.

As described above, a display panel can employ a wireless transmission technology to achieve the effect of high data transmission speed. In one example, a magnetically coupled antenna can utilize a transmitter and a receiver for wireless transmission. For example, when the transmitting antenna Tx has a current, the transmitting antenna Tx generates a magnetic field. The magnetic field causes the receiving antenna Rx corresponding to the transmitting antenna Tx to generate an induced current. Accordingly, a signal is transmitted from the transmitting antenna Tx to the corresponding receiving antenna Rx. However, for larger display device requirements, a serious voltage drop problem (also called IR drop) is caused by current during data line transmission. Therefore, the present invention proposes a Block driving mechanism (Block driving mechanism) to solve the IR drop problem by splitting the display panel into a plurality of distinct blocks and driving each Block independently with different receiving antennas. In addition, the present invention also proposes a Tiled display apparatus (Tiled display apparatus).

Fig. 1A is an exploded perspective view of a display panel of a display device according to an embodiment of the invention. As shown in fig. 1A, the display panel 100 is a color Liquid Crystal Display (LCD) panel, and includes a display unit 110, a transmitting antenna structure 130, a receiving antenna structure 150, and a backlight module 170. The display unit 110 includes a first polarizer 112, a color filter layer 114, a liquid crystal layer 116, a thin film transistor array (TFT array)120, and a second polarizer 118 from an image display side (top of fig. 1A) to a backlight side (bottom of fig. 1A). The receiving antenna structure 150 is composed of a plurality of receiving antennas Rx, and the receiving antenna structure 150 is disposed on the tft array 120. The transmitting antenna structure 150 is composed of a plurality of transmitting antennas Tx, and the transmitting antenna structure 150 is disposed on the backlight module 170, so that a distance exists between the transmitting antenna structure 130 and the receiving antenna structure 150 to improve the wireless data transmission speed therebetween.

In the display unit 110, the tft array 120, the liquid crystal layer 116 and the color filter layer 114 define a pixel structure corresponding to a display area of the display panel 100. More specifically, the pixel structure includes a plurality of pixels, and the pixels are arranged in a matrix of M columns and N rows, where M and N are positive integers. Each of the pixels of the pixel structure corresponds to a Thin Film Transistor (TFT) of the TFT array 120 and a set of color filters of the color filter layer 114.

In one embodiment, the display panel 100 can include other layers or structures not shown in FIG. 1A. For example, a plurality of insulating films or layers (i.e., the tft array 120, the liquid crystal layer 116, and the color filter layer 114) can be further included in the display structure.

Fig. 1B is a schematic diagram of a portion of a tft array according to an embodiment of the invention. As shown in fig. 1B, the thin film transistor array 120 includes a plurality of Thin Film Transistors (TFTs) arranged in an array, and each of the TFTs corresponds to a pixel in the pixel structure. In other words, for the pixel structure including a plurality of pixels arranged in M columns and N rows, the tft array 120 also includes a plurality of tfts arranged in M columns and N rows. Furthermore, the pixel structure further has a plurality of Data lines (Data lines) D1, D2, and D3.. and a plurality of Gate lines (Gate lines) G1, G2, and G G3... each of the Data lines D1, D2, and D3 is electrically connected to the Source of the tft of the corresponding column (column), and each of the Gate lines G1, G2, and G3 is electrically connected to the Gate of the tft of the corresponding Row (Row). The gate driver 122 is electrically connected to the gate lines G1, G2, G3 for transmitting signals to the gate lines, and the data driver 124 is electrically connected to the data lines D1, D2, D3 for transmitting signals to the data lines. In some embodiments, the gate driver 122 may be provided in multiple configurations. Or in some embodiments, the data driver 124 may be provided in plurality.

Fig. 2A is a schematic diagram illustrating a connection relationship between an antenna matrix formed by a plurality of receiving antenna groups in a receiving antenna structure and corresponding scan lines according to an embodiment of the invention. As shown in fig. 2A, the pixel structure 200 is divided into a plurality of receiving antenna arrays 210, and each receiving antenna array 210 includes m × n pixels corresponding to the same receiving antenna (not shown), so that a data signal is transmitted to the m × n pixels, where m and n are positive integers. In addition, as shown in fig. 2A, in the peripheral region of the pixel structure 200, the Gate driver on array (GOA) 220 and 230 are respectively disposed along the horizontal direction and the vertical direction. Specifically, each of the X-gate driving arrays (X-GOAs) 220 represents a gate driving array (GOA) on the top side as shown in fig. 2A and electrically connected to m scan lines X1, X2, X3, and. Each Y-gate driving array (Y-GOA)230 represents a gate driving array (GOA) on the left side as viewed in fig. 2A, and is electrically connected to n scan lines Y1, Y2, Y3., Yn extending along the row direction (i.e., the Y direction). Here, the pixel in the pixel circuit can include a plurality of scan transistors or a plurality of switches corresponding to each of the pixels of one of the receiving antenna arrays 210, and at least one of the scan transistors is controlled by a scan signal along the X direction and corresponding to m of the scan lines X1, X2, X3, and Xm, and at least one of the scan transistors is controlled by a scan signal along the Y direction and corresponding to n of the scan lines Y1, Y2, Y3, and. Therefore, the pixel can be controlled by the scan signal to receive the data signal transmitted through the corresponding receiving antenna.

Fig. 2B is a schematic diagram illustrating connection among the receiving antenna, the pixel circuit of a specific pixel, and the scan transistor switches corresponding to the pixel according to an embodiment of the invention. As shown in fig. 2B, the receiving antenna 240 is electrically connected to the pixels of the pixel circuit, and includes an X-scan transistor 222, a Y-scan transistor 232, and two

circuit modules

252 and 254 connected in series. Generally, a pixel circuit includes circuit elements such as transistors, capacitors, diodes, or other circuits, and there may be different connection modes between the circuit elements. Accordingly, the

circuit modules

252 and 254 are shown in two blocks without detail shown. Specifically, as shown in fig. 2B, the X scan transistor 222 is electrically connected to the scan line Xm, and the Y scan transistor 232 is electrically connected to the scan line Yn. In other words, the pixel shown in fig. 2B corresponds to the scan lines Xm and Yn in fig. 2A.

It should be noted that although fig. 2B shows that the X-scan transistor 222, the Y-scan transistor 232 and the

circuit modules

252 and 254 are arranged in series, the electrical connection among the above elements may be arranged differently, and is not limited thereto.

Fig. 3 is a top view of an antenna according to an embodiment of the invention. Specifically, the antenna 300 shown in fig. 3 can be the receiving antenna Rx of the receiving antenna structure 150 in fig. 1A. As shown in fig. 3, the antenna 300 is wound from an external feed end 302 to an internal feed end 304 in a clockwise direction. In some embodiments, the winding direction of the antenna 200 may be clockwise or counterclockwise. In addition, the antenna 300 includes a plurality of vertical segments 310 and a plurality of horizontal segments 320, thereby forming a plurality of turns of conductive wires. As shown in fig. 3, the number of windings N of the antenna 300 is 3, which means that the antenna 300 has 3 turns of wire. In some embodiments, the number of windings N of the antenna 300 can be determined based on desired transmission characteristics of the antenna 300.

In some embodiments, induced decibels (dB) can be used as a transmission characteristic parameter of the antenna to reflect the transmission performance of the antenna. In the field of wireless transmission, the value of the induced decibel (dB) of the antenna is expressed as the ratio Rx/Tx, which is the ratio of the receiving antenna Rx to the transmitting antenna Tx. For example, if the power of Rx/Tx is X, the size of Rx/Tx is (X)1/2 and the induced decibel (dB) is 10 × log 10X. Generally, an antenna with an induced decibel greater than-10 dB indicates an acceptable wireless transmission performance, while an antenna with an induced decibel close to 0dB indicates an excellent wireless transmission performance (i.e., minimum transmission loss).

Referring to fig. 2B, the receiving antenna 240 is electrically connected to the pixel of the pixel circuit and is connected to the external feed terminal of the receiving antenna 240. In some embodiments, the receiving antenna can be electrically connected to the corresponding data line and connected to the external feed end or the internal feed end of the data line. The other external feed terminal and the internal feed terminal which are not electrically connected with the corresponding data line can be grounded or electrically connected with a reference voltage potential (such as a DC voltage potential V of a common electrode)_COMOr other reference voltage potentials such as VSS signal or VDD signal).

As described above, for the LCD device using the wireless transmission technology, in the LCD device having a large size (e.g., greater than 85 ") and a high resolution (e.g., more than 8K), the capacitive loading (RC loading) is important, and it does not have an antenna configuration that allows the pixel to perform a Dot inversion driving mode (Dot inversion driving mode). To overcome this drawback, the present invention provides a display panel for implementing the receiving antenna with Dot inversion (Dot inversion) and the corresponding pixel arrangement.

Fig. 4A is a schematic diagram of an antenna block of a receiving antenna structure according to an embodiment of the invention, and fig. 4B is the schematic diagram of the antenna block in fig. 4A. It should be noted that the lines shown in fig. 4A and 4B have different line widths for illustrative purposes. However, the line widths shown in fig. 4A and 4B are not represented as actual line widths or dimension sizes, and the devices shown in fig. 4A and 4B can actually have different dimension sizes, shapes and corresponding structural locations.

As shown in fig. 4A, the receiving antenna structure 400 includes a plurality of antenna blocks 410, and the antenna blocks 410 are arranged in a matrix, and each of the antenna blocks 410 corresponds to a gate driver X-GOA 420 and a gate driver Y-GOA 430. The gate driver X-GOA 420 is connected to a set of m X scan lines X1-Xm extending along the column direction (i.e., the X direction). The gate driver Y-GOA 430 is connected to a set of n Y scan lines Y1-Yn extending along the row direction (i.e., the Y direction). And m and n are positive integers. In other words, each of the antenna blocks 410 corresponds to m × n pixels. As shown in fig. 4B, each of the antenna blocks 410 includes an antenna 412, two

diodes

414A, 414B, two transistors (e.g., switch 416A and switch 416B), and a bridge 418. The antenna 412 also includes an inner feed 412A and an outer feed 412B. As shown in fig. 4A and 4B, the inner feed end 412A serves as a feed point of the antenna 412, the outer feed end 412B serves as a reference end of the antenna 412, and the outer feed end 412B is electrically connected to the common electrode V_COMFor the common electrode V_COMReceiving the DC voltage potential. The

diodes

414A, 414B are disposed in parallel and electrically connected to the feeding point 412A of the antenna 412, and the

diodes

414A, 414B are disposed in opposite directions. The

switches

416A, 416B electrically connect the

diodes

414A, 414B, respectively, to the bridge 418. The bridge 418 is comb-shaped and has a main line 418M and a plurality of branch lines 418B. The main line 418M is electrically connected to the

switches

416A, 416B, respectively, and the branch line 418B extends from the main line 418M along the row direction and is electrically connected to the pixel. Further, the diode 414A and the switch 416A on the upper side in fig. 4B refer to the first diode 414A and the first switch 416A, respectively, and the diode 414B and the switch 416B on the lower side in fig. 4B refer to the second diode 414B and the second switch 416B, respectively.

Fig. 4C is a schematic diagram illustrating connections among a plurality of pixels, a plurality of scan lines, and bridges in an antenna block according to an embodiment of the invention. Specifically, the antenna block 410 in the upper left portion of fig. 4C includes three X scanning lines X1, X2, X3 and three Y scanning lines Y1, Y2, Y3. Wherein the X scan lines and the Y scan lines cross (cross) the antenna 412 and are electrically connected to 3 × 3 pixels 450. Each pixel 450 is electrically connected to the corresponding branch 418B of the bridge 418, such that each pixel 450 is electrically connected to the antenna 412 through the bridge 418.

Fig. 5A is a schematic diagram illustrating an antenna block connected to a pixel according to an embodiment of the invention. As shown in fig. 5A, the antenna block includes a receive antenna Rx, two

diodes

514A, 514B, two transistors (e.g., switches 516A and 516B), and a branch 518B of a bridge structure. The receiving antenna Rx, the

diodes

514A, 514B and the transistors (e.g., switches 516A and 516B) correspond to and are the same elements as those in fig. 4A and 4B, including the antenna 412, the two

diodes

414A, 414B, and the two transistors (e.g., switch 416A and switch 416B), and therefore will not be described further. The pixel includes two

scan transistors

540 and 542 and a capacitor 550, and the

scan transistors

540 and 542 are respectively connected to the scan lines X1 and Y1. Further, one transmission antenna Tx is provided to correspond to one reception antenna Rx.

Fig. 5B is a timing diagram illustrating a plurality of scanning signals and a plurality of clock signals of the antenna block and the pixel in fig. 5A according to an embodiment of the invention. As shown in fig. 5B, each of the scan signals is provided by the scan lines X1 to Xm and Y1 to Yn, and the clock signals Odd _ CK and Even _ CK are Pulse wave signals (Pulse wave signals) and have corresponding fixed periods and fixed Pulse beam widths. The pulse signal has an on period (Conduction period) and an off period (Turn-off period). Specifically, the on period of each scan signal is indicated as high, and the off period of each scan signal is indicated as low, but the above-mentioned indications of potentials are not limited thereto. As shown in fig. 5B, the Odd clock signal Odd _ CK and the Even clock signal Even _ CK are in opposite phases (Phase-inverted) between consecutive frames (frames). Specifically, in the first frame F1, in the period 560, the scan signals X1 and Y1 are transmitted from the corresponding turn-on periods, so as to turn on the

corresponding scan transistors

540 and 542 in the pixel, as shown in fig. 5A. In the period 560, the Odd clock signal Odd _ CK is in the on period, and the Even clock signal Even _ CK is in the off period. In a second frame F2, in the period 570, the scan signals X1 and Y1 are transmitted from the corresponding turn-on periods, so as to turn on the

corresponding scan transistors

540 and 542 in the pixel, as shown in fig. 5A. In the period 570, the Odd clock signal Odd _ CK is in the off period, and the Even clock signal Even _ CK is in the on period. In other words, for the pixel 550 in consecutive frames, the Odd clock signal Odd _ CK and the Even clock signal Even _ CK are opposite in Phase (Phase-inverted) signals, thereby allowing the

diodes

514A, 514B and the

switches

516A, 516B to be alternately turned on to form a plurality of parallel channels.

FIG. 5C is a schematic diagram illustrating voltage transmission of the pixel in FIG. 5A in the first frame as shown in FIG. 5B when the odd clock signal is turned on according to the embodiment of the present invention. As shown in FIG. 5C, in the first frame F1, during the period 560, the Odd clock signal Odd _ CK is in the ON period, and the Even clock signal Even _ CK is in the OFF period. Thus, the first switch 516A is on and the second switch 516B is off (and thus not shown in fig. 5C). Herein, the common voltage V_COMWill be greater than the voltage V of the pixel_pixel. Therefore, when the receiving antenna Rx is induced by the transmitting antenna Tx to generate the voltage difference Δ V, the voltage level of the feeding terminal of the receiving antenna Rx becomes V_COM+ Δ V, thereby allowing the receive antenna Rx to charge the capacitor 550 of the pixel through the first parallel channel formed by the first diode 514A and the first switch 516A.

FIG. 5D is a schematic diagram illustrating voltage transmission of the pixel of FIG. 5A in the first frame of FIG. 5B with the even clock signal on according to one embodiment of the present invention. As shown in FIG. 5D, in the second frame F2, in the period 570, the Even clock signal Even _ CK is in the on period, and the Odd clock signal Odd _ CK is in the off period. Thus, the second switch 516B is turned on, and the first switch 516A is turned off (thus not shown in fig. 5D). Herein, the voltage of the pixelV_pixelWill be greater than the common voltage V_COM. Thus, the capacitor 550 of the pixel discharges the voltage stored on the receive antenna Rx through the second parallel path formed by the second diode 514B and the second switch 516B.

It should be noted that, as shown in fig. 5B, there is a blank period BLK between consecutive frames F1, F2, wherein all signals are asserted to the off period to allow the Odd clock signal Odd _ CK and the Even clock signal Even _ CK to be Reset (Reset) in the second frame F2 and to be switched to a different phase than in the first frame F1. The length of the blanking period BLK may vary. In some embodiments, the blanking period BLK is set to be not present between consecutive frames F1, F2 by setting the signal to be specific.

As in the previous embodiment, there is only one such common electrode V_COM. In some embodiments, the display panel includes a plurality of common electrodes disposed on different layers and not connected to each other. Here, each of the common electrodes has a different dc voltage potential. For example, fig. 6 is a schematic diagram of an antenna block of a receiving antenna structure according to another embodiment of the invention. As shown in fig. 6, the difference between the receiving antenna structure 600 and the receiving antenna structure 400 shown in fig. 4A is that the receiving antenna structure 600 has three different common electrodes V_COM-1、V_COM-2、V_COM-3. Therefore, the reference terminal of each antenna block 610 is allowed to be electrically connected to one of the common electrodes V_COM-1、V_COM-2、V_COM-3. The other structures, elements and layers of the receiving antenna structure 600 are corresponding to and identical to those of the receiving antenna structure 400 shown in fig. 4A, and will not be described again here. Specifically, as shown in fig. 6, in the top row of the antenna block, the antenna at the leftmost side of the antenna block is electrically connected to the common electrode V_COM-1, the antenna at the middle side of the antenna block is electrically connected to the common electrode V_COM-3, the antenna at the rightmost side of the antenna block is electrically connected to the common electrode V_COM-2. In the middle of the antenna blockThe antenna at the leftmost side of the antenna block is electrically connected to the common electrode V_COM-2, the antenna at the middle side of the antenna block is electrically connected to the common electrode V_COM-1, the antenna at the rightmost side of the antenna block is electrically connected to the common electrode V_COM-3. In the bottom row of the antenna block, the antenna at the leftmost side of the antenna block is electrically connected to the common electrode V_COM-3, the antenna at the middle side of the antenna block is electrically connected to the common electrode V_COM-2, the antenna at the rightmost side of the antenna block is electrically connected to the common electrode V_COM-1. Herein, any two adjacent antenna blocks 610, no matter in the row direction or the column direction, will be electrically connected to one of the common electrodes V respectively_COM-1、V_COM-2 or V_COM-3, and the common electrode is different.

As in the above embodiments, the gate driver is disposed in the peripheral region of the display panel. In some embodiments, the gate driver can be moved to the display area and disposed between the antenna blocks. Thereby reducing or eliminating the peripheral region of the display panel. For example, fig. 7 is a schematic diagram of an antenna block of a receiving antenna structure according to still another embodiment of the invention. As shown in fig. 7, the receiving antenna structure 700 includes a plurality of antenna blocks 710, and the antenna blocks 710 are arranged in a 2 × 2 matrix. Specifically, the gate driver X-GOA 720 is disposed between the antenna blocks 710 of two adjacent rows, and the gate driver Y-GOA 730 is disposed between the antenna blocks 710 of two adjacent columns. In other words, each gate driver is disposed between any two adjacent antenna blocks 710 in the display area. The structure and elements of the antenna block 710 correspond to and are the same as those of the antenna block 410 shown in fig. 4A and 4B, and thus will not be described further.

As described in the above embodiments, the X scan lines X1 to Xm and the Y scan lines Y1 to Yn can form the crossing regions with the antennas Rx. Specifically, the crossing region between the receiving Antenna and the scanning line is referred to as an "Antenna crossing region". For example, fig. 8A is a schematic diagram illustrating an intersection region between a receiving antenna and a scan line according to an embodiment of the invention. As shown in fig. 8A, the antenna block 800 has antennas 810, the antennas 810 correspond to 60X scan lines X1 to X60 and 27Y scan lines Y1 to Y27, and the number of windings N of the antennas 810 is 3. Among the X scan lines, the X scan line X1 at the leftmost side of the X scan line does not form the antenna crossing region with the antenna 810. And, the scan line X60 at the rightmost side of the X scan line forms only one antenna intersection region 840 with the antenna 810. However, the scan line X30 at the middle side of the X scan line, which forms six antenna intersection regions 820 in total with the antenna 810, is twice the number of windings N. Of the Y scan lines, the Y scan lines Y1 and Y27 at the top and bottom of the Y scan line do not form the antenna crossing region with the antenna 810. However, the Y scan line Y13 at the middle side of the Y scan line and the antenna 810 form six antenna intersection regions 830 in total. It should be noted that the scan lines located at the center and the corresponding antenna 810 should form more of the antenna intersection region 830, and the scan lines located adjacent to the peripheral region and the corresponding antenna 810 should form less of the antenna intersection region 830.

Fig. 8B is a schematic diagram illustrating an intersection region between a part of the horizontal receiving antenna and the X scanning line in fig. 8A according to an embodiment of the present invention, and fig. 8C is a schematic diagram illustrating an intersection region between a part of the vertical receiving antenna and the Y scanning line in fig. 8A according to an embodiment of the present invention. As shown in fig. 8B, the width of the X scanning line X30 is 6 μm, and the width of the horizontal segment of the antenna 810 is 50 μm. Thus, the antenna crossover region 820 is 300 μm². As shown in fig. 8C, the width of the Y scanning line Y13 is 6 μm, and the width of the vertical segment of the antenna 810 is 30 μm. Thus, the antenna crossover region 820 is 180 μm²。

As shown in the scan lines of FIG. 8A, the load (10 loading) of each scan line is associated with the crossover region of the scan line to which it corresponds. For example, fig. 8D is a timing chart of capacitance values of the X scan lines in fig. 8A according to an embodiment of the invention, and fig. 8E is a timing chart of capacitance values of the Y scan lines in fig. 8A according to an embodiment of the invention. As shown in fig. 8D, the X-scan line X1 (which does not form the cross-over region with the antenna 810) at the leftmost side of the X-scan line has a capacitance of about 5.5F, and the X-scan line X30 (which forms six cross-over regions with the antenna 810) at the middle side has a capacitance of about 6.5F. As shown in fig. 8E, the Y scan line Y1 (which does not form the crossover region with the antenna 810) at the top most side of the Y scan line has a capacitance of about 11.5F, and the Y scan line Y13 (which forms six crossover regions with the antenna 810) at the middle side has a capacitance of about 12.6F. The intersection region refers to a region where the water projection of the X scanning line or the Y scanning line overlaps or coincides with the vertical projection of the antenna coil. The cross-over or overlap is shown in fig. 8B and 8C.

It should be noted that fig. 8A only shows one antenna crossover region formed by the receiving antenna 810 and the scan line. Fig. 9 is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line in a display panel according to an embodiment of the invention. As shown in fig. 9, the display panel 900 includes a plurality of receiving antennas, and the receiving antennas are arranged in a matrix. Therefore, the number of the antenna crossing regions per one scan line increases, and the difference in the load between the scan lines is also amplified, thereby causing an uneven load structure. In order to compensate for the above-mentioned drawback, the present invention further provides a display panel, and the display panel has specific scan lines and common electrodes for compensating the load between the scan lines. In order to compensate for the problem of uneven load on the scanning line due to the area intersecting the antenna coil, the following technique can be used to solve the problem.

Fig. 10A is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line according to an embodiment of the invention. As shown in FIG. 10A, the common electrode V_COMHas a plurality of strip portions disposed around the receive antenna 1010. For the X scanning lines X1-X60, each X scanning line has a crossing portion, and each crossing portion overlaps the common electrode V_COMThe horizontal strip portion of (a). For example, the X scan line X30 at the middle side of the X scan line has a corresponding cross-over portion 1020, which is the most significant portion of the X scan lineThe X-ray X1 on the left side has the corresponding cross-over part 1022, and the X-ray X60 on the rightmost side has the corresponding cross-over part 1024. The other two X-scan lines X68 and X53 are shown in fig. 10A, and have the

corresponding cross sections

1026 and 1028, respectively. Similarly, for the Y scan lines Y1 through Yn, each of the Y scan lines has a crossing portion, and each of the crossing portions overlaps the common electrode V_COMPerpendicular to the strip portion. For example, the Y scan line Y13 at the middle side of the Y scan line has the corresponding cross portion 1030, the Y scan line Y1 at the top side of the Y scan line has the corresponding cross portion 1032, and the Y scan line Y27 at the bottom side of the Y scan line has the corresponding cross portion 1034. The other two Y scan lines Y5 and Y22 are shown as 10A, and have

corresponding crossing portions

1036 and 1038, respectively. Therefore, the width of the crossing portion of the X scanning line and the Y scanning line can be used for achieving the purpose of compensation. The above-mentioned crossover or overlap being the common electrode V_COMThe area of the X scanning line and the area of the Y scanning line in the horizontal projection direction are partially overlapped or overlapped. In order to compensate the uneven load, the scan line and the common electrode V outside the antenna coil are designed according to the embodiment of the present invention_COMThe scanning lines crossing the

parts

1022, 1034, etc. are arranged more inside the antenna coil than the scanning lines and the common electrode V_COMThe scan lines crossing the

sections

1020, 1030 have a large area.

Fig. 10B is a schematic diagram illustrating an intersection region between the X-scan line and the horizontal stripe portion of the common electrode in fig. 8A according to an embodiment of the invention. As shown in fig. 10B, in the X scanning line X30 on the middle side of the X scanning line, the width W30 of the crossing portion 1020 is equal to the width of the remaining portion. In other words, the X scan line X30 on the middle side of the X scan line, which is the center scan line of the X scan lines X1 to X60, has a constant width in the X scan line X30 and the crossing portion 1020. On the other hand, in the X scan line X1 at the leftmost side of the X scan line, the width W1 of the crossing portion 1022 is greater than the width of the remaining portion (also W30, since the crossing portions of all the X scan lines have the same width). Similarly, at the X-scan line X60 on the rightmost side of the X-scan line, the width of the cross portion 1024 is also greater than the width of the remaining portion (also W30). Referring to fig. 10A again, the widths of the

respective crossing portions

1026 and 1028 of the X scan line X8 and the X scan line X53 are respectively greater than the widths of the corresponding remaining portions. In addition, the width W1 of the crossing portion 1022 of the X-ray line X1 at the leftmost side of the X-ray line is W1 greater than the width of the crossing portion 1026 of the X-ray line X8. Moreover, the width of the crossing portion 1026 of the X scanning line X8 is greater than the width W30, wherein the width of the crossing portion 1020 of the X scanning line X30 at the middle side of the X scanning line is W30. Similarly, the width of the cross portion 1024 of the X scan line X60 at the rightmost side of the X scan line is greater than the width of the cross portion 1028 of the X scan line X53. Moreover, the width of the crossing portion 1028 of the X scanning line X53 is greater than the width W30, wherein the width of the crossing portion 1020 of the X scanning line X30 at the middle side of the X scanning line is W30. The width of the

crossing portions

1030 and 1038 of the Y scan lines is also the same as the above arrangement for the width thereof, which will not be described further herein.

In some embodiments, the width of the crossing portion of each scan line is determined by the total crossing area of the antenna crossing region corresponding to each scan line. For example, the width of the crossing portion 1020 of the X scan line X30 on the middle side of the X scan line, which has the largest number and largest crossing area of the antenna crossing area, does not need to be adjusted. In contrast, the X-scan lines X1, X60 at the leftmost and rightmost sides of the X-scan line, which have the smallest number and smallest crossover regions of the antenna crossover region, have widths of the

crossover portions

1022, 1024 that increase significantly as the loads of the X-scan lines X1 to X60 increase. In this way, the load distribution among the X-scan lines can be set evenly.

FIG. 10C is a timing diagram illustrating the compensation region of the X-scan line in FIG. 8A according to an embodiment of the present invention. FIG. 10D is a timing diagram illustrating the capacitance of the X scan line in FIG. 8A according to an embodiment of the present invention. As shown in FIG. 10C, the compensation region (i.e., the area of the crossing portion) of the X scan line X30 on the middle side of the X scan line is zero, because the width of the crossing portion 1020 is not increased by the X scan line X30 on the middle side of the X scan line. In contrast, the compensation region (i.e., the area of the crossing portion) of each of the X scan lines X1-X60 is maximized because the width of the

crossing portions

1022, 1024 is significantly increased for each of the X scan lines X1-X60. Therefore, as shown in fig. 10D, the capacitance of the X-ray line is provided to compensate to about 6.5pF, thereby allowing the X-ray line to have a uniform load.

FIG. 10E is a timing diagram illustrating the compensation region of the Y scan line in FIG. 8A according to an embodiment of the present invention. FIG. 10F is a timing diagram illustrating the capacitance of the Y scan line in FIG. 8A according to an embodiment of the invention. As shown in fig. 10E, the compensation region (i.e., the area of the crossing portion) of the Y scan line Y13 on the middle side of the Y scan line is zero, because the width of the crossing portion 1030 is not increased by the Y scan line Y13 on the middle side of the Y scan line. In contrast, the compensation region (i.e., the area of the crossing portion) of each of the Y scan lines Y1 through Y27 is maximized because the width of the

crossing portions

1032, 1034 of each of the Y scan lines Y1 through Y27 is significantly increased. Thus, as shown in FIG. 10F, the capacitance of the Y scan line is provided to compensate to about 12.6pF, thereby allowing the Y scan line to have a uniform load.

As shown in FIG. 10A, the width of the scan line at the crossing portion thereof is adjusted to compensate for the load. In some embodiments, the common electrode V_COMThe width of the frame is also adjusted. Fig. 11 is a schematic diagram illustrating an intersection region between a receiving antenna and a scanning line according to an embodiment of the invention. Specifically, compared to the structure 1100 and the corresponding structure 1000 shown in fig. 10A, there is a unique difference between the embodiments shown in fig. 11 and 10A, that is, the embodiment shown in fig. 11 can not only adjust the width of the crossing portion of the X scan line and the Y scan line, but also adjust the common electrode V_COMIs equal to the strip portion width. In particular, the common electrode V_COMThe horizontal stripe portions correspond to the X scan lines, and a plurality of Overlapping portions (Overlapping portions) 1122, 1124, 1126, and 1128 correspond to crossing portions (cross portions) of the X scan lines X1, X60, X8, and X53, respectively. And the widths of the overlapped

portions

1122, 1124, 1126 and 1128 are respectively greater than the widths of the corresponding common electrodes V_COMThe remaining portion of the horizontal strip portion. Similarly, the common electrode V_COMThe vertical stripe portion of (a) corresponds to the Y scan line, and a plurality of overlapping

portions

1132, 1134, 1136, and 1138 correspond to the Y scan lines Y1, Y27, Y5, and Y22, respectively. Moreover, the widths of the overlapping

portions

1132, 1134, 1136 and 1138 are respectively greater than the widths of the corresponding common electrodes V_COMThe remaining portion of the vertical strip portion.

The inventors conducted experiments and simulations with respect to the embodiment of the compensation structure shown in fig. 10A, thereby determining compensation parameters. For example, the receive antenna structure is modeled as 12 by 5, which is arranged in a matrix of 5 rows and 12 columns. The number of windings N of each of the receiving antennas is 12, and the sizes of the horizontal section and the vertical section of each of the receiving antennas are shown in fig. 8B and 8C. Here, as shown in fig. 10A, the number of the antenna crossing regions of the X scan line X30 on the center side of the X scan line is 120 (equal to 12 × 2 × 5), and the number of the antenna crossing regions of the Y scan line Y13 on the center side of the Y scan line is 288 (equal to 12 × 2 × 12).

Fig. 12A is a timing chart illustrating the compensation region corresponding to the X scanning line having the column of five receiving antennas in the case where the number of windings N of each receiving antenna is 12 according to the embodiment of the present invention. FIG. 12B is a timing diagram illustrating the capacitance of the compensation data of the X-scan line in FIG. 12A according to an embodiment of the present invention. As shown in FIG. 12A, the width of the crossing portion of the X-scan lines X1-X60 is adjusted so that the total crossing area of each X-scan line is 36000 μm²(equal to 120 x 300 μm)²). Here, as shown in FIG. 12B, the compensation structure results in the capacitance of the X-ray line being an average value in the range of 6.340-6.376 pF.

FIG. 12C is a schematic representation of an embodiment in accordance with the inventionThe embodiment shows a timing chart of the compensation region corresponding to the Y scanning line having the row of twelve receiving antennas in the case where the number of windings N of each receiving antenna is 12. FIG. 12D is a timing diagram illustrating the capacitance of the compensation data for the Y scan line of FIG. 12A according to an embodiment of the present invention. As shown in FIG. 12C, the width of the crossing portion of the Y scan lines Y1-Y27 is adjusted so that the total crossing area of each Y scan line is 51840 μm²(equal to 288 x 180 μm)²). Here, as shown in FIG. 12D, the compensation structure results in the capacitance of the Y scan line being an average value in the range of 12.649-12.676 pF.

As described above, embodiments of the display panel and the display device are provided for purposes of illustration and description. Although certain features may be described in the context of separate embodiments, these features may be combined to form additional embodiments without departing from the spirit and scope of the present invention.

The foregoing embodiments have been presented for the purposes of illustration and description of the invention and are not intended to limit the precise forms disclosed herein. Accordingly, many modifications and variations are intended to be included herein within the scope of this disclosure.

The embodiments were chosen and described in order to explain the principles of the invention and its practical application, to thereby enable others skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skill in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is defined by the claims as filed rather than the various exemplary embodiments described above.

Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display panel, comprising:

a pixel structure corresponding to the display area and having a plurality of pixels; and

A receiving antenna structure, disposed in the pixel structure, to provide a first signal to the pixel in a dot inversion driving mode, wherein the receiving antenna structure includes a plurality of antenna blocks, and each of the antenna blocks corresponds to the pixel in the pixel M*N pixels of , the M*N pixels are arranged in M columns and N rows, and M and N are positive integers;

Wherein, each of the antenna blocks includes:

The antenna has an inner feeding end and an outer feeding end, wherein one of the inner feeding end and the outer feeding end is used as a feeding end, and the other of the inner feeding end and the outer feeding end is electrically connected to the DC voltage bit as the reference terminal;

A first diode and a second diode are connected in parallel and electrically connected to the feeding end of the antenna, wherein the first diode and the second diode are arranged in opposite directions;

a first switch, electrically connected to the first diode and the M*N pixels, wherein a control terminal of the first switch is electrically connected to a first clock signal; and

The second switch is electrically connected to the second diode and the M*N pixels, wherein the control terminal of the second switch is electrically connected to a second clock signal, and the phase of the second clock signal is the same as the phase of the second clock signal. The first clock signal is opposite;

Wherein, in each of the M*N pixels, when in the first frame, the first switch is turned on and the second switch is turned off, and when in the second frame, the first switch is turned off and the second switch is turned off The switch is on.

2 . The display panel of claim 1 , wherein each of the antenna blocks further comprises a bridge, and the M*N pixels are respectively electrically connected to the first switch and the second switch through the bridge. 3 . a switch, the bridge has a main line and a plurality of branch lines, the main line is electrically connected to the first switch and the second switch respectively, and the branch line extends from the main line along the row direction and is electrically connected to the M*N switches pixel.

3. The display panel of claim 1, further comprising a common electrode, wherein the reference terminal of the antenna of each of the antenna blocks is electrically connected to the common electrode for receiving the DC voltage from the common electrode potential.

4. The display panel of claim 3, further comprising a plurality of scan lines extending and crossing the antenna of the antenna block, wherein the antenna of the antenna block has a plurality of antenna crossing areas, the antenna crossing The crossover area overlaps the scan line in the direction perpendicular to the pixel structure, and each scan line has a crossover portion, the crossover portion overlaps with the common electrode in the vertical direction, and each of the scan lines has a crossover portion. The width of the crossing portion of the scan line is greater than or equal to the width of the remaining portion of each scan line.

5 . The display panel of claim 4 , wherein the scan line further comprises a first scan line and a second scan line, the first scan line and the second scan line respectively correspond to the antenna crossing area. 6 . A first number and a second number of , and the second number is greater than the first number, and the width of the crossing portion of the first scan line is greater than the width of the crossing portion of the second scan line.

6 . The display panel of claim 5 , wherein the scan line further comprises a third scan line, the third scan line corresponds to a third number of the antenna crossing areas, and the third number is greater than the The first number is smaller than the second number, the width of the crossing portion of the third scan line is respectively greater than the width of the crossing portion of the second scan line and smaller than the crossing portion of the first scan line the width of the portion.

7 . The display panel of claim 4 , wherein the width of the crossing portion of each scan line is determined by the total crossing area of the corresponding antenna crossing area. 8 .

8 . The display panel of claim 4 , wherein each of the pixels further comprises a plurality of scan switches, and a control terminal of each of the scan switches is electrically connected to the corresponding scan line. 9 .

9. The display panel of claim 1, further comprising a plurality of common electrodes, and the reference terminal of each of the antennas of each of the antenna blocks is electrically connected to one of the common electrodes, and each of the common electrodes Has the corresponding DC voltage potential.

10 . The display panel of claim 9 , wherein two adjacent antenna blocks in the antenna block are electrically connected to the different common electrodes, respectively. 11 .

11. The display panel of claim 1, further comprising a plurality of scan lines and a plurality of gate drivers, the gate drivers are electrically connected to the scan lines, wherein at least one of the gate drivers is disposed in the display area and disposed between two adjacent antenna blocks.