JP5124297B2 - Thin film transistor array substrate and display device - Google Patents

Description

  The present invention relates to a thin film transistor array substrate and a display device on which the thin film transistor array substrate is mounted.

  A liquid crystal display device is one of thin panels, and is widely used in monitors of personal computers and portable information terminal devices, taking advantage of low power consumption and small size and light weight. It is also widely used for TV applications and is replacing the conventional cathode ray tube.

  The mainstream of recent liquid crystal display devices is that a plurality of scanning signal lines and a plurality of display signal lines are arranged in a lattice pattern, and a thin film transistor (hereinafter referred to as a switching element) is provided as a switching element in a pixel region surrounded by the display signal lines and the scanning signal lines. An active matrix type in which “TFT” (also referred to as “Thin Film Transistor”) is formed. The active matrix type generally has higher image quality than the passive matrix type, and is the mainstream in display devices such as organic EL display devices in addition to liquid crystal display devices.

  In an active matrix type liquid crystal display device, a TFT array substrate on which TFTs, alignment films, etc. are laminated and a counter substrate on which color filters, alignment films, etc. are laminated are usually overlapped at a predetermined interval using in-plane spacers. Has been. Then, a liquid crystal is filled in a seal pattern formed at the peripheral edge between the pair of counter substrates. Polarizing plates are disposed on the non-facing surface side of the TFT array substrate and the facing substrate, respectively, and a backlight or the like is disposed on one substrate side.

  In the display area of the TFT array substrate, scanning signal lines, display signal lines, pixel electrodes, and the like are arranged. The on / off state of the TFT is controlled by the scanning signal propagating through the scanning signal line. A display signal propagating through the display signal line is supplied to the pixel electrode via the TFT. When a display signal is supplied to the pixel electrode, a display voltage corresponding to the display signal is applied between the counter electrode and the pixel electrode, and the liquid crystal is driven.

  A scanning signal propagating through the scanning signal line and a display signal propagating through the display signal line are supplied from the driver circuit. The drive circuit is disposed in a frame area that is partitioned outside the display area of the TFT array substrate, and the scanning signal line formed in the display area and the display signal line are electrically connected via a lead wiring. It is connected. The routing wiring is arranged using the space in the frame area.

  FIG. 17 is a schematic plan view of the TFT array substrate 101 according to Conventional Example 1. FIG. The TFT array substrate 101 according to the conventional example 1 has a rectangular display area 150 and a frame area 160 partitioned outside thereof. The display area 150 is divided into two in the direction of the up and down arrows in FIG. 17 with the boundary line 155 as a boundary. Here, the display area 150 located on the lower side in FIG. 17 is referred to as a first display area 151, and the upper side is referred to as a second display area 152.

  A drive circuit 140 is mounted in the vicinity of one end portion located on the lower side of the frame region 160 in FIG. In order to supply a scanning signal from the driving circuit 140 to a scanning signal line (not shown) provided in the first display area 151, a lead wiring is provided. In the first routing wiring area 161 disposed in the left frame region 160 in FIG. 17, an L-scan routing for supplying a scanning signal to the scanning signal line disposed in the first display region 151. An R for supplying a scanning signal to a scanning signal line disposed in the second display area 152 is provided in the second routing wiring area 162 disposed in the right frame area 160 in FIG. -A scanning lead-out wiring 112 is provided.

  FIG. 18 is a schematic plan view of a TFT array substrate 101a according to Conventional Example 2. The drive circuit 140a according to Conventional Example 2 is disposed at a position on the left side of the frame region 160 disposed on the TFT array substrate 101a in the vicinity of the lower side edge in FIG. In the same manner as in the conventional example 1, in order to supply a scanning signal from the driving circuit 140a to a scanning signal line (not shown) arranged in the display area 150, a lead wiring is provided.

  The routing wiring is configured to be alternately connected to a plurality of scanning signal lines (not shown) from the first routing wiring area 161a and the second routing wiring area 162b. For example, when counting from the drive circuit 140a side, the even-numbered scanning signal lines are connected to the L-scanning routing lines 111 disposed in the first routing wiring area 161a, and the odd-numbered scanning signal lines ( (Not shown) is configured to be connected to the R-scanning routing wiring 112 disposed in the second routing wiring area 162.

  The wiring length of the routing wiring according to the conventional examples 1 and 2 varies depending on the mounting position of the driving circuit and the layout position of the routing wiring. In the conventional example 1, since the wiring length of the R-scanning lead wiring 112 is longer than that of the L-scanning lead wiring 111 in FIG. 17, the first display area 151 and the second display area 152 are Display unevenness is likely to occur. In the above-described conventional example 2, the drive circuit 140a is located on the left side, so that the wiring length of the R-scanning routing wire 112 adjacent thereto is longer than that of the L-scanning routing wire 111. As described above, since the scanning signal lines are alternately input from the left and right sides from the L-scanning wiring 111 and the R-scanning wiring 112, there is a difference in wiring length for each fine line. . As a result, the horizontal band unevenness is easily visually recognized.

  Also, there is usually an intersection in the frame area 160 where the scanning signal line routing wiring and the display signal line routing wiring intersect. The number and area of these intersections may differ locally. These are differences in the wiring load of the scanning signal line routing lines, causing a difference in the delay amount of the scanning signal, which may cause display unevenness.

  As a method of improving the display unevenness, Patent Document 1 proposes a method of adjusting the wiring length of the lead wiring. FIG. 19 is a schematic plan view of the TFT array substrate described in Patent Document 1. The display area 150 disposed on the TFT array substrate 101b described in Patent Document 1 includes a first display area 151 and a second display area 152 in the vertical direction in FIG.

  A scanning-driving circuit 141 and a display-driving circuit 142 are provided as driving circuits in the vicinity of one side edge located on the lower side of the frame region 160 in FIG. The scanning-driving circuit 141 is disposed on the right side in the vicinity of one side end portion in FIG. 19, and the display-driving circuit 142 is disposed on the left side in the vicinity of one side end portion in FIG. In the first routing wiring area 161 of the left frame area 160 in FIG. 19, an L-scanning routing wiring 111 for supplying a scanning signal to the scanning signal line 110 disposed in the first display area 151 is illustrated. In the second routing wiring area 162 of the right frame area 160 in FIG. 19, an R-scanning routing wiring 112 that supplies a scanning signal to the scanning signal line 110 disposed in the second display area 152 is disposed. ing.

  The R-scanning routing wiring 112 has a folded structure as shown in FIG. The scanning signal lines 110 in the first display area 151 closest to the boundary line 155 and the scanning signal lines 110 in the second display area 152 closest to the boundary line 155 are arranged to have substantially the same wiring length, and the wiring resistance We are working to reduce disparities. Patent Document 1 also proposes a method of reducing display unevenness by adjusting the overlapping area between the lead wiring and the conductive film facing the lead wiring in the frame region 160.

Note that this is not a method for reducing display unevenness due to the resistance difference between the lead wires, but by adjusting the area of the overlapping portion between the auxiliary capacitance line and the auxiliary capacitance semiconductor layer, the color filter color There has been proposed a method of reducing display unevenness by eliminating the difference in transmittance (Patent Document 2).
JP, 2005-266394, A FIG. JP, 2007-47615, A FIG. 1, FIG.

  Recently, there is a very high demand for high definition display panels. For this reason, there is a strong demand for the development of a technique for providing a display device with high display quality while suppressing the problem of display unevenness.

  As a method for reducing the difference in the wiring load of the routing wiring, there is a method of changing the wiring width according to the wiring length of the routing wiring. Further, as described in Patent Document 1, there is a method in which a folded portion is provided to adjust the wiring length, or a facing area between the lead wiring and the conductive film is adjusted in the frame region.

  However, with the recent downsizing of the outer shape of display panels, it has become increasingly difficult to ensure a sufficient space in the frame. For this reason, the surplus space is reduced, and it is difficult to adjust the resistance by means of changing the wiring width according to the wiring length. For the same reason, it is difficult to adjust the resistance by means of providing a folded portion in the lead wiring. Further, in the method of forming the facing region between the lead wiring and the conductive film in the frame region, there is a concern that the yield may be reduced due to an interlayer short circuit. There is also a problem that power consumption increases.

  The present invention has been made in view of the above background, and an object of the present invention is to provide a display device with high display quality while achieving a narrow frame.

  A thin film transistor array substrate according to a first aspect of the present invention includes a display region, a frame region partitioned outside the display region, a plurality of scanning signal lines provided in the display region, and the display region And a plurality of display signal lines arranged to intersect the scanning signal lines, and provided in the frame region corresponding to the scanning signal lines, and a voltage from a driving circuit is applied to the scanning signal. A plurality of lead wirings to be supplied to the line, the scanning signal line, a switching semiconductor layer connected to the display signal line, a pixel electrode connected to the switching semiconductor layer, and a part of the pixel electrode And an auxiliary capacitance electrode arranged, and the opposing area of the pixel electrode and the auxiliary capacitance electrode is adjusted so as to reduce a resistance difference between the plurality of lead wirings.

  A thin film transistor array substrate according to a second aspect of the present invention includes a display region, a frame region partitioned outside the display region, a plurality of scanning signal lines provided in the display region, and the display region And a plurality of display signal lines arranged to intersect the scanning signal lines, and provided in the frame region corresponding to the scanning signal lines, and a voltage from a driving circuit is applied to the scanning signal. A plurality of lead lines to be supplied to the line; the scanning signal line; a switching semiconductor layer connected to the display signal line; a gate electrode disposed opposite to the switching semiconductor layer; and disposed opposite to the gate electrode. A drain electrode, and an opposing area of the gate electrode and the drain electrode is adjusted so as to reduce a difference in resistance between the plurality of routing wires.

  According to the present invention, it is possible to provide a display device with high display quality while achieving a narrow frame.

  Hereinafter, an example of an embodiment to which the present invention is applied will be described. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention. In the following drawings, the size of each member is for convenience of explanation and is different from the actual one.

[Embodiment 1]
The display device according to the first embodiment is an active matrix type, and includes an inverted staggered type thin film transistor (TFT) as a switching element. Here, a transmissive liquid crystal display device will be described as an example of the display device. FIG. 1 is a cross-sectional view showing the configuration of the liquid crystal display device 100 according to the first embodiment, and FIG. 2 is a schematic plan view of the TFT array substrate 1 provided in the liquid crystal display device 100.

  As shown in FIG. 1, the liquid crystal display device 100 includes a liquid crystal display panel 80 and a backlight 77. The liquid crystal display panel 80 is configured to display an image based on an input display signal. The backlight 77 is disposed on the non-viewing side of the liquid crystal display panel 80 and is configured to irradiate light to the viewing side via the liquid crystal display panel 80. The backlight 77 may be of a general configuration including a light source, a light guide plate, a reflective sheet, a diffusion sheet, a prism sheet, a reflective polarizing sheet, and the like.

  As shown in FIG. 1, the liquid crystal display device 100 includes a thin film transistor array substrate (hereinafter referred to as “TFT array substrate”) 1, a counter substrate 9, a polarizing plate 71, a counter electrode 73, an alignment film 74, a liquid crystal 75, a spacer 76, A sealing material 78 and the like are included. Further, as shown in FIG. 2, the TFT array substrate 1 includes a scanning signal line 10, an L-scanning routing line 11, an R-scanning routing line 12, a display signal line 20, a display routing line 21, and a driving circuit. 40, an external terminal 45, and the like.

  As shown in FIG. 2, the TFT array substrate 1 has a display area 50 formed in a rectangular shape and a frame area 60 partitioned outside the display area 50. A plurality of scanning signal lines 10 and a plurality of display signal lines 20 are formed in the display area 50. The scanning signal lines 10 extend in the horizontal direction in FIG. 2 and are arranged in parallel in the vertical direction. The display signal lines 20 extend in the vertical direction in FIG. 2 and are arranged in parallel in the horizontal direction so as to intersect the scanning signal lines 10 via an insulating layer (not shown).

  Near the intersection of the scanning signal line 10 and the display signal line 20, TFTs 31 are provided in a matrix. A pixel electrode 6 (not shown) is formed in a region surrounded by the adjacent scanning signal lines 10 and display signal lines 20, and this region functions as the pixel 30. The gate, source, and drain constituting the TFT 31 are connected to the scanning signal line 10, the display signal line 20, and the pixel electrode 6, respectively. The pixel electrode 6 is formed of a transparent conductive thin film such as ITO (Indium Tin Oxide). A region where the plurality of pixels 30 are formed is a display region 50.

  In the frame area 60, as shown in FIG. 2, a drive circuit 40, an external terminal 45, a lead wiring, and the like are arranged. The drive circuit 40 is mounted by COG (Chip On Glass) technology. The drive circuit 40 and the external terminal 45 are connected via a wiring (not shown). External signals are supplied to the external terminals 45 from a flexible printed circuit board (“FPC”). Various external signals are supplied to the drive circuit 40 via the external terminal 45.

  The L-scanning lead wiring 11 is arranged in a first lead wiring area 61 provided on the left side of the frame area 60 in FIG. Similarly, the R-scanning lead wiring 12 is disposed in a second lead wiring area 62 provided on the right side of the frame region 60 in FIG. The display routing wiring 21 is disposed in the area from the drive circuit 40 to the display area 150 in the lower area of the frame area 60. By arranging the scanning routing wiring (L-scanning routing wiring 11 and R-scanning routing wiring 12) on both sides of the frame area 60 in about half each, the frame can be narrowed.

  The L-scanning lead wiring 11 is a scanning signal disposed in the first display area 51 located on the lower side when the display area 50 is divided into two in the vertical direction in FIG. A signal is supplied to the line 10. Similarly, the R-scanning lead wiring 12 supplies a signal to the scanning signal line 10 disposed in the second display area 52.

  The routing wiring according to the first embodiment has a wiring width that is just below the manufacturing limit, and the wiring width of all the routing wirings is the same. The L-scanning routing wiring 11 and the display routing wiring 21, and the R-scanning routing wiring 12 and the display routing wiring 21 are arranged so as to face each other via an insulating layer (not shown). It is arranged. Of course, the L-scanning lead wire 11 and the display lead wire 21 and the R-scan lead wire 12 and the display lead wire 21 may not be arranged to face each other.

  The drive circuit 40 supplies a scanning signal to the scanning signal line 10 through a scanning routing wiring based on a control signal from the outside. The scanning signal lines 10 are sequentially selected by this scanning signal. Further, the drive circuit 40 supplies a display signal to the display signal line 20 through the display routing wiring based on the control signal and display data from the outside. As a result, a display voltage corresponding to the display data can be supplied to each pixel electrode 6.

  Here, the drive circuit 40 is directly mounted on the TFT array substrate 1 by using the COG technique, but is not limited to this configuration. For example, the drive circuit may be connected to the TFT array substrate 1 by TCP (Tape Carrier Package).

  As shown in FIG. 1, in the liquid crystal display panel 80, a liquid crystal 75 is sealed in a space surrounded by a TFT array substrate 1 and a counter substrate 9 that are arranged to face each other and a sealing material 78 that bonds the two substrates together. . A distance between the two substrates is maintained by a spacer 76 so as to have a predetermined distance.

  In the TFT array substrate 1, an alignment film 74 is formed on each of the electrodes and wirings described above. On the other hand, a color filter (not shown), a BM (Black Matrix) (not shown), a counter electrode 73, an alignment film 74, and the like are formed on the surface of the counter substrate 9 facing the TFT array substrate 1. A polarizing plate 71 is attached to each of the outer surfaces of the TFT array substrate 1 and the counter substrate 9.

  The liquid crystal display device 100 having the above configuration is driven as follows, for example. A scanning signal is supplied from the driving circuit 40 to each scanning signal line 10. Each scanning signal turns on all the TFTs 31 connected to one scanning signal line 10 simultaneously. On the other hand, the display signal is supplied from the drive circuit 40 to each display signal line 20, and charges corresponding to the display signal are accumulated in the pixel electrode 6. The arrangement of liquid crystals between the pixel electrode 6 and the counter electrode 73 changes in accordance with the potential difference between the pixel electrode 6 and the counter electrode 73 to which the display signal is written. As a result, the amount of light transmitted through the liquid crystal display panel 80 changes. In this manner, a desired image can be displayed by changing the display voltage for each pixel 30.

  Next, the detailed configuration of the TFT array substrate 1 will be described in detail. FIG. 3 is a plan view showing a configuration of a main part for one pixel formed on the TFT array substrate 1. For convenience of explanation, illustration of a gate insulating film and a protective film, which will be described later, is omitted in FIG. As shown in FIG. 3, the TFT array substrate 1 includes a scanning signal line 10, a display signal line 20, a pixel electrode 6, a source electrode 22, a drain electrode 23, a contact hole 7, a semiconductor layer 3, an auxiliary capacitance electrode 14, and the like. .

  As shown in FIG. 3, the auxiliary capacitance electrode 14 for forming the capacitor is disposed so as to face a part of the pixel electrode 6. Thereby, the auxiliary capacitor Cs is formed. The auxiliary capacitance electrode 14 extends from the auxiliary capacitance electrode line 15. The auxiliary capacitance electrode line 15 is arranged in parallel with the scanning signal line 10 and is connected to a common wiring (not shown) in the frame region 51.

  When a signal is applied to the scanning signal line 10, the signal charge transmitted from the display signal line 20 is written into the pixel, and the charge is stored in the auxiliary capacitor Cs. At this time, the pixel electrode 6 applies a potential corresponding to the written signal to the liquid crystal to display a desired image. The pixel electrode 6 is used as one of the electrodes that store the signal charge of each pixel, and the auxiliary capacitance electrode 14 is used as the counter electrode. The auxiliary capacitance electrode 14 is formed of the same layer (first conductive film) as the scanning signal line 10 and is arranged so as to intersect the display signal line 20 via the gate insulating layer so as to be connected to all the pixels. Yes.

  FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. The TFT 31 according to the first embodiment is of an inverted stagger type and is manufactured by channel etching (CE). As shown in FIG. 4, the TFT 31 includes an insulating substrate 70, a gate electrode 13, a gate insulating film 2, a first semiconductor layer 3 and a second semiconductor layer 4 which are switching semiconductor layers (hereinafter simply referred to as “semiconductor layers”). , Source electrode 22, drain electrode 23, protective film 5, pixel electrode 6 and the like.

  As the insulating substrate 70, a transparent substrate such as a glass substrate or a quartz substrate is used. The gate electrode 13 extends from the scanning signal line 10. The gate electrode 13, the auxiliary capacitance electrode 14, and the auxiliary capacitance electrode line 15 are formed on the insulating substrate 70, and are in the same layer as the scanning signal line 10, the L-scanning routing wiring 11, and the R-scanning routing wiring 12. The first conductive film is formed.

  The gate insulating film 2 is formed in an upper layer so as to cover the scanning signal line 10, the L-scanning wiring 11, the R-scanning wiring 12, the gate electrode 13, the auxiliary capacitance electrode 14, and the auxiliary capacitance electrode line 15. Is formed. For the gate insulating film 2, silicon oxide, silicon nitride, or the like can be used. The first semiconductor layer 3 is formed on the gate insulating film 2, and at least a part of the first semiconductor layer 3 is disposed to face the gate electrode 13 with the gate insulating film 2 interposed therebetween. The second semiconductor layer 4 is formed in the upper layer of the first semiconductor layer 3. As the semiconductor layer, an a-Si film or a p-Si film can be used.

  A source electrode 22 extending from the display signal line 20 is formed on the upper layer of the semiconductor layer. Thereby, a source voltage can be supplied to the source region of the semiconductor layer. Furthermore, a drain electrode is formed on the drain region of the semiconductor layer. The source electrode and the drain electrode can be formed in the same process as the display signal line. For the scanning signal line and the display signal line, for example, a low-resistance metal material such as Al or Cr can be used. Thus, the scanning signal line 10 and the display signal line 20 are formed of different wiring layers.

  The source electrode 22 and the drain electrode 23 are arranged to face at least a part of the gate electrode 13 with the gate insulating film 2, the first semiconductor layer 3, and the second semiconductor layer 4 interposed therebetween. That is, in order to operate as a TFT, the thin film transistor region exists on the gate electrode 13 and is easily affected by an electric field when a voltage is applied to the gate electrode.

  The protective film 5 is formed so as to cover the channel region of the semiconductor layer, the source electrode 22 and the drain electrode 23 (see FIG. 3). A pixel electrode 6 is formed on the protective film 5. The drain electrode 23 and the pixel electrode 6 are electrically connected through a contact hole 7 formed in the protective film 5. Therefore, when a scanning signal is supplied to the scanning signal line, a gate voltage is applied to a predetermined gate electrode, the TFT is turned on, and an image display signal voltage is supplied from the source electrode to the pixel electrode via the drain electrode.

  As described above, the pixel electrode 6 is configured such that a part of the auxiliary capacitor electrode 14 is disposed opposite to the pixel electrode 6 and forms the auxiliary capacitor Cs. Further, as described above, the drain electrode 23 is configured such that a part of the region is opposed to the gate electrode 13 and forms a gate-drain capacitance Cgd. The first display area 51 and the second display area 52 have substantially the same area, and the same number of scanning signal lines 10 are provided. Of course, this is an example, and it goes without saying that the present invention is not limited thereto.

  As a result of extensive studies by the inventor in order to achieve the object of the present invention, the size of the auxiliary capacitor Cs is adjusted, thereby reducing the resistance difference between the scanning lead wires and achieving a narrow frame. I found out that I could do it. That is, it has been found that the difference in the wiring load of the scanning routing wiring can be canceled by adjusting the value of the auxiliary capacitance Cs.

  FIG. 5 shows the value of the auxiliary capacitance Cs constituted by the corresponding pixel electrode 6 and the auxiliary capacitance electrode 14 extended from the auxiliary capacitance electrode line 15 with respect to the display signal line address according to the first embodiment. The plotted figure is shown. Here, the display signal line address of the X axis indicates the arrangement of the display signal line when counted from the display area 50 side adjacent to the left side of the frame area 60 in FIG.

  In the TFT array substrate according to the first embodiment, as shown in FIG. 5, the auxiliary capacitance Cs formed by the auxiliary capacitance electrode 14 and the pixel electrode 6 disposed in the first display region 51 is the second display. The auxiliary capacitance is set to be larger than the auxiliary capacitance Cs formed by the auxiliary capacitance electrode 14 and the pixel electrode 6 disposed in the region 52. The auxiliary capacity Cs in the first display area 51 is substantially constant, and the auxiliary capacity Cs in the second display area 52 is also substantially constant in the same area. In other words, the value of the auxiliary capacitance Cs in the first display area 51 input from the L-scanning routing line 11 side is used as the auxiliary capacity in the second display area 52 input from the R-scanning routing line 12 side. It is set larger than the value of the capacity Cs.

  FIG. 6 shows a plot of the pixel electrode potential with respect to the display signal line address according to the first embodiment. FIG. 6 also shows a plot of pixel electrode potentials when the auxiliary capacitance Cs of the first display area 51 and the auxiliary capacitance Cs of the second display area 52 are substantially the same. 6A is a plot of the corresponding pixel electrode potential with respect to the display signal line address of the second display area 52, and FIG. 6B is a display signal line address of the first display area 51. Is a plot of the corresponding pixel electrode potential. On the other hand, (c) corresponds to the display signal line address of the first display area 51 when the auxiliary capacity Cs of the first display area 51 is substantially the same as the auxiliary capacity Cs of the second display area 52. The pixel electrode potential is plotted.

  First, the case where the auxiliary capacity Cs of the first display area 51 and the auxiliary capacity Cs of the second display area 52 are made substantially the same will be described. In this case, as shown in (a) and (c), the pixel electrode potential difference between the first display area 51 and the second display area 52 is particularly large in the area where the display signal line address is small.

  As shown in FIG. 6, when the scanning signal line 10 is input from the left side, the pixel electrode potential increases as the display signal address increases. On the other hand, when the scanning signal line 10 is input from the right side, the pixel electrode potential increases as the display signal address decreases. That is, it can be seen that the smaller the wiring load, the smaller the pixel electrode potential. A scanning signal is supplied to the first display area 51 from the L-scanning lead wiring 11 having a small wiring load. Therefore, the pixel electrode potential is relatively smaller than that supplied from the R-scanning lead wiring 12 having a relatively large wiring load (see (a) and (c) in FIG. 6).

  Therefore, in the first embodiment, the auxiliary capacitance Cs of the first display area 51 which is the area of the L-scanning lead wiring 11 input from the left side with respect to the scanning signal line 10 is used as the auxiliary capacity of the second display area 52. As shown in FIG. 5, it was set to be uniformly larger than Cs. As a result, the difference between the pixel electrode potential in the first display area 51 and the pixel electrode potential in the second display area 52 becomes smaller than in the cases (a) and (c). By adjusting the delay amount of the wiring load of the scanning lead wiring by the auxiliary capacitor Cs, it is possible to reduce the difference in pixel electrode potential and reduce display unevenness.

  As shown in FIGS. 6A and 6B, display unevenness such as color unevenness and brightness unevenness is reduced by reducing the difference in pixel electrode potential between the first display area 51 and the second display area 52. Can do. That is, by adjusting the auxiliary capacitor Cs according to the difference in the wiring load of the scanning lead wiring, the difference in pixel electrode potential can be reduced and display unevenness of the liquid crystal display device can be reduced.

Here, the reason why the display unevenness of the liquid crystal display device can be reduced by adjusting the value of the auxiliary capacitor Cs will be described. In general, in an active matrix display device using a TFT, the potential of the pixel electrode varies as shown in FIG. 7 at the fall of the scanning signal due to the parasitic gate-drain capacitance Cgd of the TFT. This fluctuation amount is called a field through voltage Vfd and can be generally expressed by the following formula <1>.
<Formula 1> Vfd = Cgd · ΔVg / (Clc + Cs + Cgd)
ΔVg is a scanning signal amplitude, Cs is a holding capacitor, and Clc is a liquid crystal capacitor.

  However, the above expression <1> is an expression when the scanning signal is an ideal pulse, and actually, the scanning signal input as a square wave is rounded by the time constant (resistance × capacitance) of the scanning wiring. Occurs. This rounding causes a delay from the beginning of the fall of the scanning signal until the transistor is turned off, and the pixel potential that is going to fluctuate due to field through is recovered to some extent.

  FIGS. 8A and 8B show an example of an actual falling image of the scanning signal. In the case where there is a delay in the scanning signal, as shown in FIG. 8, the pixel potential is restored to some extent to the potential of the display signal before the transistor is turned off. Therefore, when the delay of the scanning signal is large, the amount of recovery is large and the pixel potential is high.

  This recovery amount varies depending on the time constant of the scanning wiring, resulting in a difference in pixel potential. Therefore, Vfd can be adjusted by adjusting the auxiliary capacitance Cs in the above formula <1> according to the time constant (wiring load) of the scanning signal line. Specifically, Vfd can be reduced by increasing the auxiliary capacitance Cs. Further, display unevenness can be reduced by reducing the difference in pixel potential.

  In addition, since the routing wiring according to the first embodiment has all the routing wiring as the manufacturing limit wiring width and does not have a folded portion or the like as in Patent Document 1, it is possible to realize a narrow frame. it can. According to the present invention, it is possible to provide a display device with high display quality while achieving a narrow frame. In addition, since display unevenness can be reduced without adding a special configuration for reducing the resistance difference between the scanning lead wirings, a display device with high reliability can be provided without causing a decrease in yield.

  In the first embodiment, the example in which all the wiring widths of the routing wirings are the same has been described. However, it goes without saying that the wiring width can be changed without departing from the gist of the present invention. In the first embodiment, each of the first display area 51 and the second display area 52 is set to have a uniform auxiliary capacity Cs. In the second display area 52, the wiring distance varies depending on the individual scanning routing lines, so that a resistance difference occurs between the routing lines. Therefore, if this is taken into consideration and the auxiliary capacitances Cs in the first display area 51 and the second display area 52 are individually adjusted, it becomes possible to more effectively suppress display unevenness and improve quality. A high display device can be provided.

[Embodiment 2]
Next, an example of a liquid crystal display device different from the first embodiment will be described. In the following description, the same elements as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The liquid crystal display device according to the second embodiment has the same configuration and operation as the liquid crystal display device according to the first embodiment except for the following points. That is, in the first embodiment, the value of the auxiliary capacitance Cs in the first display area 51 and the second display area 52 is set to different values as shown in FIG. The first display area 51 and the second display area 52 are different in that the auxiliary capacitance Cs is the same. In the first embodiment, the first display area 51 and the second display area 52 are designed to have the same gate-drain capacitance Cgd, whereas in the second embodiment, The difference is that the values of the gate-drain capacitance Cgd of the first display area 51 and the second display area 52 are set to be different.

  FIG. 9 is a diagram in which the value of the corresponding gate-drain capacitance Cgd is plotted against the display signal line address according to the second embodiment. As shown in FIG. 9, in the TFT array substrate according to the second embodiment, the gate-drain capacitance Cgd formed by the gate electrode 13 and the drain electrode 23 disposed in the first display region 51 is 2 It is set to be smaller than the gate-drain capacitance Cgd formed by the gate electrode 13 and the drain electrode 23 arranged in the display area 52.

  In the second embodiment, the gate-drain capacitance Cgd in the first display region 51 is substantially constant, and the gate-drain capacitance Cgd in the second display region 52 is also substantially constant in the same region. Further, as described above, the auxiliary capacitance Cs is set to be substantially constant. In other words, the value of the gate-drain capacitance Cgd in the first display area 51 input from the L-scanning routing line 11 side is set to the second display area 52 input from the R-scanning routing line 12 side. It is set smaller than the value of the gate-drain capacitance Cgd.

  FIG. 10 shows a plot of the corresponding pixel electrode potential with respect to the display signal line address according to the second embodiment. FIG. 9 also shows a plot of the pixel electrode potential when the gate-drain capacitance Cgd of the first display region 51 and the gate-drain capacitance Cgd of the second display region 52 are substantially the same. 10A is a plot of the corresponding pixel electrode potential with respect to the display signal line address of the second display area 52, and FIG. 10B is the display signal line address of the first display area 51. FIG. Is a plot of the corresponding pixel electrode potential. On the other hand, (c) shows the display signal line address of the first display area 51 when the auxiliary capacity Cs of the first display area 51 and the gate-drain capacity Cgd of the second display area 52 are substantially the same. The corresponding pixel electrode potential is plotted.

  First, a case where the gate-drain capacitance Cgd of the first display region 51 and the gate-drain capacitance Cgd of the second display region 52 are substantially the same will be described. In this case, as shown in (a) and (c), the pixel electrode potential difference between the first display area 51 and the second display area 52 is particularly large in the area where the display signal line address is small.

  In the second embodiment, the gate-drain capacitance Cgd of the first display region 51 which is the region of the L-scanning lead wiring 11 inputted from the left side with respect to the scanning signal line 10 is used as the gate of the second display region 52. -It was set so as to be uniformly smaller than the drain-drain capacitance Cgd as shown in FIG. As a result, the difference between the pixel electrode potential in the first display area 51 and the pixel electrode potential in the second display area 52 becomes smaller than in the cases (a) and (c). By adjusting the gate-drain capacitance Cgd, the delay amount of the scanning load wiring can be adjusted, thereby reducing the difference in pixel electrode potential and reducing display unevenness.

  Since the difference in pixel electrode potential between the first display area 51 and the second display area 52 is reduced as shown in FIGS. 10A and 10B, display unevenness can be reduced. That is, by adjusting the gate-drain capacitance Cgd in the above formula <1> according to the wiring load difference of the lead wiring, the difference in pixel electrode potential is reduced and display unevenness of the liquid crystal display device is reduced. can do.

  In addition, since the routing wiring according to the second embodiment has all the routing wirings as the manufacturing limit wiring width and is not provided with a folded portion or the like as in Patent Document 1, a narrow frame can be realized. it can. According to the present invention, it is possible to provide a display device with high display quality while achieving a narrow frame. In addition, since display unevenness can be reduced without adding a special configuration for reducing the resistance difference between the scanning lead wirings, a display device with high reliability can be provided without causing a decrease in yield. Note that display unevenness may be more effectively reduced by combining the first and second embodiments.

[Embodiment 3]
The liquid crystal display device according to the third embodiment has the same configuration and operation as the liquid crystal display device according to the first embodiment except for the following points. That is, in the first embodiment, the value of the auxiliary capacitance Cs in the first display area 51 is substantially constant and the value of the auxiliary capacity Cs in the second display area 52 is substantially constant. Is different in that the value of the auxiliary capacitance Cs is adjusted in accordance with the position of the display signal line address in each of the first display area 51 and the second display area 52. In other words, the value of the auxiliary capacitor Cs disposed between the input end of the scan signal line connected to the scan lead wiring and the end of the scan signal line which is the opposite end is optimized. It is adjusted so that.

  FIG. 11 is a diagram in which the value of the corresponding auxiliary capacitor Cs is plotted against the display signal line address according to the third embodiment. In the same figure, the relative position of the auxiliary capacity Cs of the first display area 51 and the auxiliary capacity Cs of the second display area 52 in the first embodiment is also shown (see FIG. 5). FIG. 12 shows a plot of the corresponding pixel electrode potential with respect to the display signal line address according to the third embodiment.

  By optimizing the auxiliary capacitance Cs in accordance with the display signal line address, the difference in pixel electrode potential can be reduced as shown in FIG. Specifically, the facing area between the pixel electrode 6 and the auxiliary capacitance electrode 14 is set so as to decrease from the input side to the end of the scanning signal line 10. Thereby, the difference in pixel electrode potential due to the position between the same scanning signal lines can be reduced. Therefore, a higher quality liquid crystal display device can be provided. This is particularly effective when the display area is a large screen.

  Further, the auxiliary capacity Cs of the second display area 52 is located at a position away from the drive circuit 40 so that the auxiliary capacity Cs of the first display area 51 becomes smaller as the scanning signal line is located away from the drive circuit 40. By setting the scanning signal line to be smaller, the difference in pixel electrode potential can be more effectively reduced.

  When the folding portion is not provided as in Patent Document 1 described above, the scanning signal line routing distance differs individually depending on the arrangement of the scanning signal lines, and the wiring load differs individually. The value of the auxiliary capacitance Cs provided in the corresponding scanning signal line is set according to the wiring distance of each routing wiring. Thereby, the difference in pixel electrode potential due to the wiring distance of the lead wiring can be reduced.

  The amount of adjustment of the auxiliary capacitor Cs varies depending on the mounting position of the driving circuit, the wiring length of the scanning routing wiring, the wiring width, the crossing area with the display routing wiring, and the like. Adjust accordingly. A liquid crystal display device with higher display quality can be obtained by adjusting the auxiliary capacitance Cs according to the position of the TFT disposed in one scanning signal line or according to the resistance difference between the wirings of the scanning lead wiring. Can be provided.

[Embodiment 4]
The liquid crystal display device according to the fourth embodiment has the same configuration and operation as the liquid crystal display device according to the second embodiment except for the following points. That is, in the second embodiment, the value of the gate-drain capacitance Cgd in the first display region 51 is substantially constant, and the value of the gate-drain capacitance Cgd in the second display region 52 is substantially constant. On the other hand, the third embodiment is different in that the value of the gate-drain capacitance Cgd is adjusted according to the position of the display signal line address in each of the first display area 51 and the second display area 52. .

  FIG. 13 is a diagram in which the value of the corresponding gate-drain capacitance Cgd is plotted with respect to the display signal line address according to the fourth embodiment. In the same figure, the relative positions of the gate-drain capacitance Cgd of the first display region 51 and the gate-drain capacitance Cgd of the second display region 52 in the first embodiment are also shown (see FIG. 11). FIG. 14 shows a plot of the corresponding pixel electrode potential with respect to the display signal line address according to the fourth embodiment.

  By optimizing the gate-drain capacitance Cgd in accordance with the display signal line address, the difference in pixel electrode potential can be reduced as shown in FIG. In other words, by setting the facing area between the gate electrode 13 and the drain electrode 23 to increase from the input side to the end of the scanning signal line 10, the difference in pixel electrode potential between the same scanning signal lines can be reduced. Thus, a high-quality liquid crystal display device can be provided. This is particularly effective when the display area is a large screen.

  Further, the gate-drain capacitance Cgd of the second display region 52 is increased so that the gate-drain capacitance Cgd of the first display region 51 increases as the scanning signal line is located farther from the drive circuit 40. By setting the scanning signal line so as to be farther away from the scanning signal line 40, the difference in pixel electrode potential can be reduced.

  When the folding portion is not provided as in Patent Document 1 described above, the scanning signal line routing distance differs individually depending on the arrangement of the scanning signal lines, and the wiring load differs individually. The value of the gate-drain capacitance Cgd provided for each corresponding pixel is set according to the wiring distance of each routing wiring. Thereby, the difference in pixel electrode potential due to the wiring distance of the lead wiring can be reduced.

  The amount of adjustment of the gate-drain capacitance Cgd varies depending on the mounting position of the drive circuit, the wiring length of the scanning routing wiring, the wiring width, the crossing area with the display routing wiring, and the like. It adjusts suitably according to the aspect of an apparatus. Higher display quality can be achieved by adjusting the gate-drain capacitance Cgd in accordance with the position of the TFT arranged in one scanning signal line or in accordance with the resistance difference between the scanning lead wirings. A liquid crystal display device can be provided.

  According to the liquid crystal display device according to the fourth embodiment, by adjusting the gate-drain capacitance Cgd as shown in FIG. 13, the difference between the pixel electrode potentials as shown in FIG. It can be made smaller than that. As a result, a higher quality liquid crystal display device can be provided.

[Embodiment 5]
The liquid crystal display device according to the fifth embodiment has the same configuration and operation as the liquid crystal display device according to the first embodiment except for the following points. That is, in the first embodiment, one drive circuit is provided, but in the fifth embodiment, a scan-drive circuit that drives the scan signal line 10 and a display that drives the display signal 20. The difference is that the drive circuits are arranged separately; In the first embodiment, a substantially constant auxiliary capacitance Cs is set in each of the first display area 51 and the second display area 52, whereas in the fifth embodiment, the third embodiment is described. As described above, the difference is that the value of the auxiliary capacitor Cs is appropriately set according to the position of the TFT 31 of the display signal line address so that the difference in pixel electrode potential is small regardless of the position of the display signal line address. To do.

  FIG. 15 is a schematic plan view of the TFT array substrate 1a according to the fifth embodiment. As shown in FIG. 15, a scanning-driving circuit 41 and a display-driving circuit 42 are disposed on the TFT array substrate 1a in place of the driving circuit 40. The scanning-driving circuit 41 is disposed at the lower right position below the frame area 60, and the display-driving circuit 42 is also disposed at the lower left position below the frame area 60.

  In the fifth embodiment, according to the wiring load of the L-scanning routing wiring 11 and the R-scanning routing wiring 12, as in the third embodiment, the auxiliary capacitance Cs is set so that the potential difference of the pixel electrode potential is reduced. The value of is adjusted. Thereby, the effect similar to the said embodiment can be acquired. According to the present invention, the resistance difference between the scanning lead lines is adjusted by changing the size of the auxiliary capacitor Cs or / and the gate-drain capacitor Cgd. A display device with high display quality can be provided while being flexibly changed in accordance with the required use.

[Embodiment 6]
The liquid crystal display device according to the sixth embodiment has the same configuration and operation as the liquid crystal display device according to the fifth embodiment except for the following points. That is, in the fifth embodiment, a scanning signal is supplied from the L-scanning lead wiring 11 to the first display area 51 and from the R-scanning lead wiring 12 to the second display area 52. The sixth embodiment is different in that a signal is alternately supplied to the scanning signal lines 10 from both the left and right sides without dividing the display region 50.

  FIG. 16 is a schematic plan view of the TFT array substrate 1b according to the sixth embodiment. The L-scanning routing wiring 11b is disposed in the first routing wiring area 61b, and the R-scanning routing wiring 12b is disposed in the second routing wiring area 62b. In the sixth embodiment, according to the wiring load of the L-scanning lead wiring 11b and the R-scanning lead wiring 12b, as in the fifth embodiment, the auxiliary capacitance Cs is set so that the potential difference between the pixel electrode potentials becomes small. The value of is adjusted. As a result, it is possible to provide a display device with high display quality by suppressing fine horizontal band unevenness for each line.

  According to the present invention, as shown in the first to sixth embodiments, the value of the auxiliary capacitance Cs or / and the gate-drain capacitance Cgd is adjusted so as to reduce the resistance difference between the scanning routing lines. Accordingly, it is possible to provide a display device with high display quality by suppressing display unevenness. Further, by adjusting the value of the auxiliary capacitance Cs or / and the gate-drain capacitance Cgd according to the arrangement position (relative position of the scanning signal line) of the plurality of TFTs arranged for each pixel, it is more effective. Accordingly, display unevenness can be suppressed and a display device with high display quality can be provided.

  According to the present invention, the auxiliary capacitance and the gate-drain capacitance arranged in the pixel are adjusted instead of the method of adjusting the resistance difference between the scanning lead wirings by the wiring itself. Can be achieved. Therefore, it is particularly effective when there is no surplus space in the frame area. Moreover, even if there is a surplus space in the frame area, by applying the present invention, the space can be effectively used for other purposes.

  Embodiments 1 to 6 may be combined with each other. Various modifications can be made without departing from the spirit of the present invention. In the above embodiment, the example in which the drive circuit is disposed at one end of the frame region has been described. However, the present invention is not limited to this, and the drive circuit may be disposed near the end of a plurality of sides. . Further, although an example in which signals are input from both the right side and the left side of the frame area with respect to the scanning signal line has been described, the present invention is not limited to this, and the present invention can be applied even when a scanning signal is input from the vicinity of one side. Applicable.

  In the above embodiment, an example of a liquid crystal display device has been described as a display device. However, the present invention is not limited to this, and the present invention can be applied to various active matrix display devices such as an organic EL display device in general. It is. Further, although an example of an inverted stagger type TFT has been described as an example of the switching element, the switching element is not particularly limited and can be applied to a TFT having a stagger type structure.

FIG. 3 is a schematic cross-sectional view of the liquid crystal display device according to the first embodiment. 1 is a schematic plan view of a TFT array substrate according to Embodiment 1. FIG. FIG. 3 is a schematic plan view for one pixel of the TFT array substrate according to the first embodiment. FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3. FIG. 3 is a diagram illustrating an auxiliary capacitance Cs value with respect to a display signal line address of the liquid crystal display device according to the first embodiment. FIG. 3 is a diagram illustrating pixel electrode potentials with respect to display signal line addresses of the liquid crystal display device according to the first embodiment. Explanatory drawing of the scanning signal, display signal, and pixel electrode potential in the case of an ideal pulse. (A) And (b) is explanatory drawing which shows an example of an actual scanning signal, a display signal, and a pixel electrode potential. FIG. 6 is a diagram illustrating a gate-drain capacitance Cgd value with respect to a display signal line address of the liquid crystal display device according to the second embodiment. FIG. 6 is a diagram illustrating pixel electrode potentials with respect to display signal line addresses of the liquid crystal display device according to the second embodiment. FIG. 10 is a diagram illustrating an auxiliary capacitance Cs value with respect to a display signal line address of the liquid crystal display device according to the third embodiment. FIG. 6 is a diagram illustrating pixel electrode potentials with respect to display signal line addresses of a liquid crystal display device according to a third embodiment. FIG. 10 is a diagram illustrating a gate-drain capacitance Cgd value with respect to a display signal line address of the liquid crystal display device according to the fourth embodiment. FIG. 6 is a diagram illustrating pixel electrode potentials with respect to display signal line addresses of a liquid crystal display device according to a fourth embodiment. 6 is a schematic plan view of a TFT array substrate of a liquid crystal display device according to Embodiment 5. FIG. 7 is a schematic plan view of a TFT array substrate of a liquid crystal display device according to Embodiment 6. FIG. FIG. 7 is a schematic plan view of a TFT array substrate of a liquid crystal display device according to Conventional Example 1. FIG. 9 is a schematic plan view of a TFT array substrate of a liquid crystal display device according to Conventional Example 2. FIG. 6 is a schematic plan view of a TFT array substrate of a liquid crystal display device according to Patent Document 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 TFT array substrate 2 Gate insulating film 3 1st semiconductor layer 4 2nd semiconductor layer 5 Protective film 6 Pixel electrode 7 Contact hole 9 Opposite substrate 10 Scan signal line 11 L-scanning lead wiring 12 R-scanning lead wiring 13 Gate Electrode 14 Auxiliary capacitance electrode 15 Auxiliary capacitance electrode line 20 Display signal line 21 Display routing wiring 22 Source electrode 23 Drain electrode 30 Pixel region 31 TFT
40 drive circuit 41 external terminal 50 display area 51 first display area 52 second display area 55 border line 60 frame area 61 first lead wiring area 62 second lead wiring area 70 insulating substrate 71 polarizing plate 73 counter electrode 74 Alignment film 75 Liquid crystal 76 Spacer 77 Backlight 78 Sealing material 100 Liquid crystal display device

Claims (7)

A display area;
A frame area partitioned outside the display area;
A plurality of scanning signal lines provided in the display area;
A plurality of display signal lines provided in the display area and arranged to intersect the scanning signal lines;
A plurality of lead wirings provided in the frame region corresponding to the scanning signal lines and supplying a voltage from a driving circuit to the scanning signal lines;
The scanning signal line; and a switching semiconductor layer connected to the display signal line;
A pixel electrode connected to the switching semiconductor layer;
An auxiliary capacitance electrode disposed opposite to a part of the pixel electrode,
A thin film transistor array substrate in which a facing area between the pixel electrode and the auxiliary capacitance electrode is adjusted so as to reduce a resistance difference between the plurality of routing wires.   2. The thin film transistor array substrate according to claim 1, wherein a facing area between the pixel electrode and the auxiliary capacitance electrode is reduced as compared to a case where a wiring load of the routing wiring is large compared to a case where the wiring load is small. .   3. The thin film transistor array according to claim 1, wherein a facing area between the pixel electrode and the auxiliary capacitance electrode is made larger in the vicinity of the input side of the scanning signal line than in the vicinity of the termination side. substrate. A display area;
A frame area partitioned outside the display area;
A plurality of scanning signal lines provided in the display area;
A plurality of display signal lines provided in the display area and arranged to intersect the scanning signal lines;
A plurality of lead wirings provided in the frame region corresponding to the scanning signal lines and supplying a voltage from a driving circuit to the scanning signal lines;
The scanning signal line; and a switching semiconductor layer connected to the display signal line;
A gate electrode disposed opposite to the switching semiconductor layer;
A drain electrode disposed opposite to the gate electrode,
A thin film transistor array substrate in which a facing area between the gate electrode and the drain electrode is adjusted so as to reduce a resistance difference between the plurality of routing wires.   5. The thin film transistor array substrate according to claim 4, wherein a facing area between the gate electrode and the drain electrode is increased as compared to a case where a wiring load of the routing wiring is large compared to a case where the wiring load is small.   6. The thin film transistor array substrate according to claim 4, wherein a facing area between the gate electrode and the source electrode is made smaller in the vicinity of the input side of the scanning signal line than in the vicinity of the termination side. .   A display device on which the thin film transistor array substrate according to claim 1 is mounted.

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