CN110212912B - Multiple delay phase-locked loop with high-precision time-to-digital converter - Google Patents

Abstract

The invention discloses a multiple delay phase-locked loop with a high-precision time-to-digital converter, comprising a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit and a data selector. The digitizer processing module is provided with a coarse time-to-digital converter, a digital-to-time converter, a subtractor and a pulse reduction time-to-digital converter connected in sequence. The invention applies the high-precision time-to-digital converter module to the multiple delay phase-locked loop, and improves the precision of the time-to-digital converter by sampling-extraction-sampling to improve the quantization noise; The use of a time amplifier and the capture of rising and falling edges directly input the phase difference to the pulse reduction time-to-digital converter for the second sampling, without the need for additional time amplifiers to amplify the phase difference and improve the linearity of the time-to-digital conversion module degrees and its input range.

Description

A Multiple Delay Phase Locked Loop with High Precision Time-to-Digital Converter

technical field

The invention relates to the technical field of integrated circuits, in particular to a multiple delay phase-locked loop with a high-precision time-to-digital converter.

Background technique

The multiple delay phase-locked loop is a module related to the overall chip clock in the chip. Therefore, there are still many studies to propose how to reduce the jitter and spur of the multiple delay phase-locked loop to maintain the clock of the entire chip. The random error is within an acceptable and reasonable range. In the design of the multiple-delay phase-locked loop, the jitter generated by the voltage-controlled oscillator will accumulate with the loop, so the multiple-delay phase-locked loop re-inputs a new clock signal to the oscillator at regular intervals, to Reduce the jitter of the oscillator, but after a new clock signal is input, the detected phase difference is the largest at this time, so although the multiple delay phase-locked loop can reduce the jitter, it will also generate very large spurs.

The nonlinearity of the early analog multiple-delay phase-locked loop due to both the charge pump and the phase detector will affect the jitter of the multiple-delay phase-locked loop output. Therefore, the multiple-delay phase-locked loop tends to be more digital. The time-to-digital converter replaces the charge pump and phase detector to improve the shortcomings of the analog multiple delay phase-locked loop.

In order to improve the noise suppression ability, reference 1 (Helal et al., "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-DigitalConverter to Achieve Subpicosecond Jitter Performance", IEEE J.Solid-StateCircuits, vol.43, no.4, pp.855-863, Apr.2008) proposed to use a time-to-digital converter based on a gated ring oscillator, which is a high-precision digital converter with low quantization noise , but consumes a lot of power.

Reference 2 (P.Chen et al., "A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.47, no.9, pp.954- 958, Sep.2000) proposed a pulse shrinking time-to-digital converter (Pulse shrinking TDC), the pulse shrinking time-to-digital converter is a Vernier time-to-digital converter (Vernier TDC), and it is also a high-precision time-to-digital converter. Compared with the vernier time-to-digital converter, the pulse-reduced time-to-digital converter has advantages in area and power consumption, and the deviation produced by the pulse-reduced time-to-digital converter is also smaller.

Based on the above, it is necessary to provide a multiple delay phase-locked loop with a high-precision time-to-digital converter, to improve the accuracy of the time-to-digital converter to improve the quantization noise, and to improve the linearity and input range of the time-to-digital conversion module.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a multiple delay phase-locked loop with a high-precision time-to-digital converter. The time-to-digital converter can simplify the circuit complexity of the time-to-digital converter module; in the existing common two-step time-to-digital converter, the digital signal sampled by the time-to-digital converter is restored and subtracted by the digital time converter The phase difference is obtained, and then the time amplifier is used to amplify the phase difference for the second sampling. At this time, the rising and falling edges of the phase difference need to be captured and input to the time amplifier before the amplification; and the present invention uses the pulse reduction type time-to-digital conversion. The device can omit the use of time amplifiers and capture of rising and falling edges, and directly input the phase difference to the pulse-reduced time-to-digital converter for second sampling.

In order to achieve the above object, the present invention realizes through the following technical solutions:

A multiple delay phase-locked loop with a high-precision time-to-digital converter, comprising a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit, a data selector, and a time-to-digital converter The processing module is provided with a coarse adjustment time-to-digital converter, a digital-to-time converter, a subtractor and a pulse reduction time-to-digital converter connected in sequence; wherein, the coarse adjustment time-to-digital converter is input with a reference clock of a multiple delay phase-locked loop signal and the output signal of the previous feedback of the multiple delay phase-locked loop, and convert the input time difference between the reference clock signal and the output signal into a corresponding digital signal and output it to the digital time converter, the digital signal It is restored to a time-domain signal, and the digital-to-time converter outputs the restored time-domain signal to the subtractor and subtracts it from the reference clock signal to obtain the phase difference of the coarse-adjusted time-to-digital converter, so The subtractor sends the obtained phase difference to the pulse reduction time-to-digital converter to obtain a pulse output signal, and finally sends the digital signal and the pulse output signal to the digital-to-analog converter to obtain an analog output signal, which is used to control and The frequency of the output signal of the voltage-controlled oscillator connected to the digital-to-analog converter.

Preferably, the analog output signal is a voltage signal.

Preferably, the input range of the coarse time-to-digital converter is larger than the input range of the pulse reduction time-to-digital converter under the same number of bits.

Preferably, the coarse time-to-digital converter is a flash time-to-digital converter.

Preferably, the pulse reduction time-to-digital converter comprises:

A delay chain includes multi-stage buffers, each stage of the buffer is composed of two inverters with different delays; the input end of the delay chain inputs the phase difference of the subtractor in the previous stage, the The delay of the phase difference through each stage of the buffer in the delay chain is gradually reduced until the last stage of the buffer;

A D-type flip-flop, the input end of which is connected to the output end of the delay chain, which collects the pulse signal output by each stage of the delay chain buffer, and finally obtains the output of the pulse reduction time-to-digital converter. Pulse output signal.

Preferably, the formula calculated by the pulse reduction type time-to-digital converter is T=N*dt+error, where T represents the phase difference, N represents the number of D-type flip-flops whose output is 1, and dt is The precision of the pulse reduction time-to-digital converter, error is the quantization error of the pulse reduction time-to-digital converter.

Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The high-precision time-to-digital converter module of the present invention is applied to a multiple delay phase-locked loop, and the time-to-digital converter is improved by sampling-extraction-sampling. (2) The present invention uses the pulse reduction time-to-digital converter to omit the use of the time amplifier and the extraction of rising and falling edges, and directly input the phase difference to the pulse reduction time-to-digital converter for the first time-to-digital converter. Subsampling does not require additional time amplifiers to amplify the phase difference, improves the linearity of the time-to-digital conversion module and its input range, and can avoid the nonlinear characteristics caused by the use of time amplifiers.

Description of drawings

1 is a multiple delay phase-locked loop architecture diagram with a high-precision time-to-digital converter of the present invention;

FIG. 2 is a structural diagram of the pulse reduction time-to-digital converter of the present invention.

In the figure, 11. Time-to-digital converter processing module; 111. Coarse time-to-digital converter; 112. Digital-to-time converter; 114. Pulse reduction time-to-digital converter; 12. Digital-to-analog converter; 13. Voltage control Oscillator; 14. Digital control circuit; 15. Data selector; 16. Frequency divider; 21. Buffer (buffer composed of two inverters with different delays); 22. D-type flip-flop.

Detailed ways

The features, objects and advantages of the present invention will become more apparent upon reading the detailed description of the non-limiting embodiments made with reference to Figures 1-2. 1-2, which illustrate embodiments of the present invention, the present invention will be described in more detail below. However, the present invention may be embodied in many different forms and should not be construed as limited by the embodiments set forth herein.

As shown in FIG. 1-FIG. 2, the present invention provides a multiple delay phase-locked loop with a high-precision time-to-digital converter, including a time-to-digital converter processing module 11, a digital-to-analog converter 12, a data selector 15, a voltage control Oscillator 13 , frequency divider 16 , digital control circuit 14 .

The time-to-digital converter processing module 11 is connected to the digital-to-analog converter 12 , and the digital-to-analog converter 12 is connected to the voltage-controlled oscillator 13 . The time-to-digital converter processing module 11 obtains the digital signal of the time difference of the signal input through the first sampling by sampling-extraction-sampling, extracts the quantization noise on the time-to-digital converter, and performs the second sampling on the quantization noise , and output the corresponding digital signal to the digital-to-analog converter 12 to obtain an analog output signal (such as a signal in the form of voltage), which is used to adjust the frequency of the output signal of the voltage-controlled oscillator 13 and reduce the frequency of the output signal of the voltage-controlled oscillator 13 and Enter the error of the reference signal frequency.

A frequency divider 16 is inserted into the feedback branch output from the voltage controlled oscillator 13 to the time-to-digital converter processing module 11 , thereby obtaining the frequency multiplication delay phase locked loop of the present invention. The advantage of phase-locked frequency doubling is that the spectral purity is very pure, and the frequency doubling times can be made very high.

As shown in FIG. 1 , the time-to-digital converter processing module 11 includes a coarse time-to-digital converter 111 , a digital-to-time converter 112 , a subtractor 113 , and a pulse reduction time-to-digital converter 114 , which are connected in sequence.

The multiple delay phase-locked loop of the present invention is input with a reference clock signal REF, and the multiple delay phase-locked loop output signal OUT. In the coarse adjustment time-to-digital converter 111, the time difference between the input of the reference clock signal REF and the output signal OUT is converted into a digital signal Cout and output to the digital time converter 112, and the digital signal Cout is restored into a time domain signal, digital time The converter 112 continues to output the restored time domain signal to the subtractor 113 and subtracts it from the reference clock signal REF to obtain the phase difference (ie quantization noise) of the coarsely adjusted time-to-digital converter 111. The phase difference obtained by the subtractor 113 The difference is sent to the pulse reduction type time-to-digital converter 114 to obtain the output signal PSout, and finally the output signal Cout and the output signal PSout are sent to the digital-to-analog converter 12 to obtain the analog output signal DACsum, which is used to control the voltage controlled oscillator 13 (VCO). The frequency of the output signal OUT.

Among them, sel in FIG. 1 is the input signal of the data selector 15 , which is mainly used to determine whether the output of the data selector 15 uses the reference clock signal REF or the output signal OUT. The function of the multiple delay phase-locked loop of the present invention is to inject a new reference clock signal into the voltage-controlled oscillator 13 in a fixed period. This mechanism is mainly used to reduce the jitter generated by the multiple delay phase-locked loop. If a new reference clock is input, the jitter generated by the voltage-controlled oscillator 13 will accumulate all the time, causing the jitter generated by the overall circuit to become larger and larger. According to the above mechanism, the digital control circuit 14 is mainly used to generate a sel signal to control the data selector 15, and the control data selector 15 determines whether its output is a REF or an OUT signal by the sel signal.

The main function of the pulse reduction time-to-digital converter 114 of the present invention is to determine the accuracy of the time-to-digital converter processing module 11 , and the coarse adjustment of the time-to-digital converter 111 is mainly to increase the input range of the time-to-digital converter module 11 . Among them, the precision of the pulse reduction time-to-digital converter 114 is higher than that of the coarse adjustment time-to-digital converter 111. Therefore, when the coarse adjustment time-to-digital converter 111 and the pulse reduction time-to-digital converter 114 have the same number of bits, the pulse reduction time The input range of the digital converter 114 is smaller than that of the coarse time-to-digital converter 111 , so the present invention needs to increase the coarse time-to-digital converter 111 to ensure the input range of the entire time-to-digital converter processing module 11 .

Preferably, the coarse time-to-digital converter 111 is a flash time-to-digital converter, so it can be used to increase the input range of the time-to-digital converter of the multiple delay phase-locked loop of the present invention.

FIG. 2 is an architecture diagram of the pulse reduction type time-to-digital converter of the present invention. The pulse reduction time-to-digital converter 114 of the present invention is a high-precision time-to-digital converter, which includes a delay chain and a D-type flip-flop 22 . The delay chain includes multi-stage buffers 21, each stage of buffer 21 includes two inverters with different delays, and the delays of the two inverters are t1 and t2 respectively. Wherein, td=t1-t2, td is the precision of the pulse reduction type time-to-digital converter, so the precision required by the present invention can be obtained only by designing the two inverters in the delay chain. At the same time, the delay error caused by the mismatch of the inverters of the present invention is lower than that of the typical vernier time-to-digital converter, and the power consumption and area consumption are also smaller.

As shown in FIG. 2 , the input signal din of the pulse reduction type time-to-digital converter 114 is the output pulse of the subtractor 113 composed of the XOR gate at the previous stage, and the output pulse represents the output pulse of the coarse adjustment time-to-digital converter 111 after digital time conversion. The phase difference obtained by the converter 112 and subtracted from the reference clock signal REF also represents the quantization error (ie, quantization noise) of the coarse adjustment time-to-digital converter 111 . The delay of the input signal din of the pulse reduction time-to-digital converter 114 after passing through each stage of the buffer in the delay chain gradually decreases (for example, PS0>PS1>PS2>...>PSn). At this time, the obtained The reduced pulse of each stage of buffer is sampled by the D-type flip-flop 22, and the digital output signal PSout of the pulse reduction time-to-digital converter 114 can be obtained. The PSout refers to multiple outputs, namely PS0, PS1, PS2 , ... and PSn.

Among them, the formula calculated by the pulse reduction type time-to-digital converter 114 is T=N*dt+error, where T represents the phase difference, N represents the number of D-type flip-flops whose output is 1, and dt is the pulse reduction The precision of the pulse reduction time-to-digital converter 114, error is the quantization error of the pulse reduction time-to-digital converter. For example, assuming that the input phase difference is about 23ps, and the pulse reduction time-to-digital converter 114 The precision dt is 5ps, then by the formula It can be known that N=4, error=3ps, which means that the outputs PS0-PS3 of the pulse reduction time-to-digital converter 114 are 1, the other PS4-PSn are 0, and the quantization error is 3ps.

To sum up, in the design of the digital multiple delay phase-locked loop, the noise mainly comes from the quantization noise of the time-to-digital conversion. The time-to-digital converter processing module in the multiple delay phase-locked loop proposed by the present invention The above-mentioned coarse adjustment time-to-digital converter 111 converts the time difference between the input of the reference clock signal REF and the output signal OUT into a digital signal Cout)-extraction (that is, the above-mentioned digital time converter 112 restores the digital signal Cout to a time domain signal , the digital time converter 112 continues to output the restored time domain signal to the subtractor 113 and subtracts it from the reference clock signal REF to obtain the phase difference of the coarse adjustment time digital converter 111 )-sampling (that is, the above-mentioned phase difference transmission To the pulse reduction type time-to-digital converter 114 to obtain the output signal PSout), the precision of the time-to-digital converter is improved to improve the quantization noise. In addition, the present invention uses the pulse reduction type time-to-digital converter, and does not need to use an additional time amplifier to reduce the phase difference. Amplification, the linearity of the time-to-digital converter processing module is increased, and the input range can also be increased, that is, the present invention replaces the time amplifier, and can avoid the nonlinear characteristics caused by the use of the time amplifier.

While the content of the present invention has been described in detail by way of the above preferred embodiments, it should be appreciated that the above description should not be construed as limiting the present invention. Various modifications and alternatives to the present invention will be apparent to those skilled in the art upon reading the foregoing. Accordingly, the scope of protection of the present invention should be defined by the appended claims.

Claims (6)

1. A multiple delay phase-locked loop with a high-precision time-to-digital converter comprises a time-to-digital converter processing module (11), a digital-to-analog converter (12), a voltage-controlled oscillator (13), a frequency divider (16), a digital control circuit (14) and a data selector (15), and is characterized in that the time-to-digital converter processing module (11) is provided with a coarse-tuning time-to-digital converter (111), a digital-to-time converter (112), a subtracter (113) and a pulse reduction time-to-digital converter (114) which are sequentially connected; the coarse-tuning time digital converter (111) inputs a reference clock signal (REF) with a multiple delay phase-locked loop and an output signal (OUT) fed back last time of the multiple delay phase-locked loop, converts a time difference input by the reference clock signal (REF) and the output signal (OUT) into a corresponding digital signal (Cout) and outputs the digital signal (Cout) to the digital time converter (112), reduces the digital signal (Cout) into a time domain signal, the digital time converter (112) outputs the reduced time domain signal to the subtracter (113) and subtracts the time domain signal from the reference clock signal (REF) to obtain a phase difference of the coarse-tuning time digital converter (111), the subtracter (113) sends the obtained phase difference to the pulse reduction time digital converter (114) to obtain a pulse output signal (PSout), and finally sends the digital signal (Cout) and the pulse output signal (PSout) to the digital-to-analog converter (12) to obtain an analog time digital converter (D/A) -an output signal (DACsum) for controlling the frequency of the output signal of a voltage controlled oscillator (13) connected to the digital to analog converter (12).

2. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,

the analog output signal is a voltage signal.

3. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,

the input range of the coarse time-to-digital converter (111) is larger than the input range of the pulse reduction time-to-digital converter (114) under the same number of bits.

4. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1 or 3,

the coarse time-to-digital converter (111) is a flash time-to-digital converter.

5. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,

the pulse-reduction time-to-digital converter (114) comprises:

a delay chain comprising a plurality of buffers, each buffer comprising two inverters with different delays; the input end of the delay chain inputs the phase difference of the subtracter (113) of the previous stage, and the phase difference is gradually reduced through the delay of each stage of buffer in the delay chain until the last stage of buffer is reached;

and the input end of the D-type flip-flop is connected with the output end of the delay chain, and the D-type flip-flop collects pulse signals output by each stage of buffer of the delay chain and finally obtains pulse output signals (PSout) output by the pulse reduction type time-to-digital converter (114).

6. The multiple delay locked loop with high precision time-to-digital converter of claim 5,

the formula calculated by the pulse reduction time-to-digital converter (114) is T-N-dt + error, wherein T represents the phase difference, N represents the number of D-type flip-flop outputs as 1, dt is the precision of the pulse reduction time-to-digital converter, and error is the quantization error of the pulse reduction time-to-digital converter.

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