CN110212912A - A kind of multiple delay phase-locked loop with High-precision time-to-digital converter - Google Patents

Abstract

The invention discloses a multiple delay phase-locked loop with a high-precision time-to-digital converter, which includes a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit, and a data selector. The digitizer processing module is provided with a coarse time-to-digital converter, a digital-to-time converter, a subtractor and a pulse reduction time-to-digital converter connected in sequence. The present invention applies the high-precision time-to-digital converter module in the multiple delay phase-locked loop, and improves the precision of the time-to-digital converter to improve the quantization noise through the sampling-extraction-sampling mode; the use of the pulse reduction type time-to-digital converter can be omitted The use of time amplifiers and the capture of rising and falling edges directly input the phase difference to the pulse-reduced time-to-digital converter for the second sampling, without additional use of time amplifiers to amplify the phase difference and improve the linearity of the time-to-digital conversion module degree and its input range.

Description

A Multiple Delay Locked Loop with High Precision Time-to-Digital Converter

technical field

The invention relates to the technical field of integrated circuits, in particular to a multiple delay phase-locked loop with a high-precision time-to-digital converter.

Background technique

The multiple delay phase-locked loop is a module related to the overall chip clock in the chip, so there are still many researches to propose how to reduce the jitter and low spurious (spur) of the multiple delay phase-locked loop to maintain the clock of the entire chip The random error is within an acceptable and reasonable range. In the design of the multiple delay phase-locked loop, the jitter generated by the voltage-controlled oscillator will be accumulated along with the loop, so the multiple delay phase-locked loop re-inputs a new clock signal into the oscillator at regular intervals to Reduce the jitter of the oscillator, but after inputting a new clock signal, the phase difference detected at this time is the largest, so although the multiple delay phase-locked loop can reduce the jitter, it will also generate very large spurs.

The nonlinearity of the early analog multiple delay phase-locked loop caused by both the charge pump and the phase detector will affect the jitter of the multiple delay phase-locked loop output, so the multiple delay phase-locked loop tends to be digital, and the digital multiple delay phase-locked loop A time-to-digital converter is used to replace the charge pump and phase detector to improve the shortcomings of the analog multiple delay locked loop.

In order to improve the noise suppression ability, reference 1 (Helal et al., "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance", IEEE J.Solid-State Circuits, vol.43, no.4, pp.855-863, Apr.2008) proposed to use a time-to-digital converter based on a gated ring oscillator, which is a high-precision digital converter with small quantization noise , but consumes a lot of power.

Reference 2 (P.Chen et al., "A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.47, no.9, pp.954- 958, Sep.2000) proposed a pulse shrinking time-to-digital converter (Pulse shrinking TDC). Compared with vernier-type time-to-digital converters, pulse-reduced time-to-digital converters have advantages in both area and power consumption. In addition, pulse-reduced time-to-digital converters have smaller deviations.

Based on the above, it is necessary to provide a multiple delay phase-locked loop with a high-precision time-to-digital converter, improve the precision of the time-to-digital converter to improve the quantization noise, and improve the linearity and input range of the time-to-digital conversion module.

Contents of the invention

The object of the present invention is to provide a kind of multiple delay phase-locked loop with high-precision time-to-digital converter, and the pulse reduction type time-to-digital converter is applied in the multiple delay phase-locked loop as a high-precision time-to-digital converter; type time-to-digital converter can simplify the circuit complexity of the time-to-digital converter module; The phase difference is obtained, and then the time amplifier is used to amplify the phase difference for the second sampling. At this time, the rising edge and falling edge of the phase difference need to be captured and input to the time amplifier before amplification; and the present invention uses pulse reduction type time-to-digital conversion The device can omit the use of the time amplifier and the capture of the rising and falling edges, and directly input the phase difference to the pulse-reducing time-to-digital converter for the second sampling.

In order to achieve the above object, the present invention is achieved through the following technical solutions:

A multiple delay phase-locked loop with a high-precision time-to-digital converter, including a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit and a data selector, and a time-to-digital converter The processing module is provided with a sequentially connected coarse time-to-digital converter, a digital time converter, a subtractor and a pulse reduction type time-to-digital converter; wherein, the coarse time-to-digital converter is input with a reference clock of a multiple delay phase-locked loop The output signal of the last feedback of the signal and the multiple delay phase-locked loop, and the time difference between the input of the reference clock signal and the output signal is converted into a corresponding digital signal and output to the digital time converter, and the digital signal Restored to a time-domain signal, the digital-to-time converter outputs the restored time-domain signal to the subtracter and subtracts it from the reference clock signal to obtain the phase difference of the coarse time-to-digital converter, so The subtractor sends the obtained phase difference to the pulse reduction time-to-digital converter to obtain a pulse output signal, and finally sends the digital signal and the pulse output signal to the digital-to-analog converter to obtain an analog output signal, which is used for control and The frequency of the output signal of the voltage controlled oscillator connected to the digital-to-analog converter.

Preferably, the analog output signal is a voltage signal.

Preferably, the input range of the coarse time-to-digital converter is larger than the input range of the pulse reduction time-to-digital converter with the same number of bits.

Preferably, the coarse time-to-digital converter is a flash time-to-digital converter.

Preferably, the pulse reduction time-to-digital converter comprises:

A delay chain comprises multi-stage buffers, and each stage buffer is made up of two inverters with different time delays; the input end of the delay chain inputs the phase difference of the described subtractor of the preceding stage, the The phase difference gradually decreases through the delay of each stage buffer in the delay chain until reaching the last stage buffer;

A D-type flip-flop, whose input end is connected with the output end of the described time-delay chain, it collects the pulse signal output by each stage buffer of the described time-delay chain, and finally obtains the pulse signal output by the pulse reduction type time-to-digital converter Pulse output signal.

Preferably, the formula for calculating the pulse reduction time-to-digital converter is T=N*dt+error, where T represents the phase difference, N represents the number of D-type flip-flops outputting 1, and dt is Accuracy of the pulse-reducing time-to-digital converter, error is the quantization error of the pulse-reducing time-to-digital converter.

Compared with the prior art, the beneficial effects of the present invention are: (1) the high-precision time-to-digital converter module of the present invention is applied in a multiple delay phase-locked loop, and improves the time-to-digital converter by sampling-extracting-sampling. (2) The present invention can omit the use of the time amplifier and the capture of rising and falling edges by using the pulse reduction type time-to-digital converter, and directly input the phase difference to the pulse reduction type time-to-digital converter for the first step The second sampling does not need to use additional time amplifiers to amplify the phase difference, improves the linearity of the time-to-digital conversion module and its input range, and can avoid the nonlinear characteristics caused by the use of time amplifiers.

Description of drawings

Fig. 1 is the frame diagram of multiple delay phase-locked loop with high-precision time-to-digital converter of the present invention;

FIG. 2 is a structure diagram of the pulse reduction type time-to-digital converter of the present invention.

In the figure, 11. Time-to-digital converter processing module; 111. Coarse time-to-digital converter; 112. Digital-to-time converter; 114. Pulse reduction time-to-digital converter; 12. Digital-to-analog converter; 13. Voltage control Oscillator; 14. Digital control circuit; 15. Data selector; 16. Frequency divider; 21. Buffer (a buffer composed of two inverters with different delays); 22. D-type flip-flop.

Detailed ways

The features, objects and advantages of the present invention will become more apparent by reading the detailed description of a non-limiting embodiment made with reference to FIGS. 1-2 . Referring to Figs. 1-2 which illustrate embodiments of the present invention, the present invention will be described in more detail below. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

As shown in Figures 1-2, the present invention provides a multiple delay phase-locked loop with a high-precision time-to-digital converter including a time-to-digital converter processing module 11, a digital-to-analog converter 12, a data selector 15, a voltage control Oscillator 13, frequency divider 16, digital control circuit 14.

The time-to-digital converter processing module 11 is connected to a digital-to-analog converter 12 , and the digital-to-analog converter 12 is connected to a voltage-controlled oscillator 13 . The time-to-digital converter processing module 11 obtains the digital signal of the time difference of the signal input through sampling-extraction-sampling for the first time, extracts the quantization noise on the time-to-digital converter, and performs a second sampling on the quantization noise , and output the corresponding digital signal to the digital-to-analog converter 12 to obtain an analog output signal (such as a signal in the form of a voltage), which is used to adjust the frequency of the output signal of the voltage-controlled oscillator 13, and reduce the frequency of the output signal of the voltage-controlled oscillator 13 and The error in the frequency of the input reference signal.

A frequency divider 16 is inserted into the feedback branch of the voltage-controlled oscillator 13 output to the time-to-digital converter processing module 11, thereby obtaining the multiplier delay phase-locked loop of the present invention, and the frequency multiplication times are equal to the frequency division times of the frequency divider 16. The advantage of phase-locked frequency multiplication is that the frequency spectrum is very pure, and the number of frequency multiplication can be made very high.

As shown in FIG. 1 , the time-to-digital converter processing module 11 includes a coarse time-to-digital converter 111 , a digital-to-time converter 112 , a subtractor 113 , and a pulse-reduced time-to-digital converter 114 connected in sequence.

The multiple delay phase-locked loop input of the present invention has a reference clock signal REF, and the multiple delay phase-locked loop output signal OUT, and the reference clock signal REF and the output signal OUT are simultaneously input to the coarse time-to-digital converter 111 of the time-to-digital converter processing module 11 Among them, the coarse time-to-digital converter 111 converts the time difference between the input of the reference clock signal REF and the output signal OUT into a digital signal Cout and outputs it to the digital-time converter 112, and restores the digital signal Cout to a time-domain signal, and the digital time The converter 112 continues to output the restored time-domain signal to the subtractor 113 and subtract it from the reference clock signal REF to obtain the phase difference (ie quantization noise) of the coarse time-to-digital converter 111, and the subtractor 113 obtains the phase difference The difference is sent to the pulse reduction type time-to-digital converter 114 to obtain the output signal PSout, and finally the output signal Cout and the output signal PSout are sent to the digital-to-analog converter 12 to obtain the analog output signal DACsum, which is used to control the voltage-controlled oscillator 13 (VCO) The frequency of the output signal OUT.

Wherein, sel in FIG. 1 is an input signal of the data selector 15, which is mainly used to determine whether the output of the data selector 15 uses the reference clock signal REF or the output signal OUT. The function of the multiple delay phase-locked loop of the present invention is to inject a new reference clock signal to the voltage-controlled oscillator 13 in a fixed cycle. This mechanism is mainly used to reduce the jitter generated by the entire multiple delay phase-locked loop, because if not If a new reference clock is input, the jitter generated by the voltage-controlled oscillator 13 will always accumulate, causing the jitter generated by the whole circuit to become larger and larger. According to the above mechanism, the digital control circuit 14 is mainly used to generate a sel signal to control the data selector 15, and the control data selector 15 determines whether its output is REF or OUT signal by means of the sel signal.

The main function of the pulse reduction type time-to-digital converter 114 of the present invention is to determine the precision of the time-to-digital converter processing module 11 , and the coarse adjustment of the time-to-digital converter 111 is mainly to increase the input range of the time-to-digital converter module 11 . Wherein, the precision of the pulse reduction type time-to-digital converter 114 is higher than that of the coarse adjustment time-to-digital converter 111, so when the coarse adjustment time-to-digital converter 111 and the pulse reduction type time-to-digital converter 114 have the same number of bits, the pulse reduction type time-to-digital converter 114 has the same number of bits. The input range of the digital converter 114 is smaller than that of the coarse time-to-digital converter 111 , so the present invention needs to add the coarse time-to-digital converter 111 to ensure the input range of the entire time-to-digital converter processing module 11 .

Preferably, the coarse time-to-digital converter 111 is a flash time-to-digital converter, so it can be used to increase the input range of the time-to-digital converter of the multiple delay locked loop of the present invention.

FIG. 2 is a structure diagram of the pulse reduction type time-to-digital converter of the present invention. The pulse reduction type time-to-digital converter 114 of the present invention is a high-precision time-to-digital converter, which includes a delay chain and a D-type flip-flop 22 . Wherein, the delay chain includes multi-stage buffers 21, and each stage of buffer 21 includes two inverters with different delays, and the delays of the two inverters are t1 and t2 respectively. Wherein, td=t1-t2, td is the precision of the pulse reduction type time-to-digital converter, so as long as the two inverters in the delay chain are designed, the required precision of the present invention can be obtained. At the same time, the delay error caused by the mismatch of the inverter is lower than that of a typical vernier type time-to-digital converter, and the power consumption and area consumption are also smaller.

As shown in Figure 2, the input signal din of the pulse reduction type time-to-digital converter 114 is the output pulse of the subtractor 113 composed of XOR gates in the previous stage, and the output pulse represents the output of the coarse-tuning time-to-digital converter 111 after digital-to-time conversion The phase difference obtained by restoring and subtracting the reference clock signal REF by the converter 112 also represents the quantization error (ie quantization noise) of the coarse time-to-digital converter 111 . The input signal din of the pulse reduction type time-to-digital converter 114 gradually decreases through the delay of each stage buffer in the delay chain (for example, PS0>PS1>PS2>...>PSn), and the obtained The reduced pulses of each stage buffer are sampled by the D-type flip-flop 22 to obtain the digital output signal PSout of the pulse-reduced time-to-digital converter 114, and the PSout refers to a plurality of outputs, namely PS0, PS1, PS2 , ... and PSn.

Wherein, the formula calculated by the pulse reduction type time-to-digital converter 114 is T=N*dt+error, where T represents the phase difference, N represents the number of D-type flip-flops outputting 1, and dt represents the pulse reduction The precision of the time-to-digital converter 114, error is the quantization error of the pulse reduction time-to-digital converter, for example, assuming that the input phase difference is about 23ps, the precision dt of the pulse reduction time-to-digital converter 114 is 5ps, then by the formula It can be known that N=4, error=3ps, which means that the output PS0-PS3 of the pulse reduction type time-to-digital converter 114 is 1, the other PS4-PSn are 0, and the quantization error is 3ps.

In summary, in the design of digital multiple delay phase-locked loop, its noise mainly comes from the quantization noise of time-to-digital conversion, the time-to-digital converter processing module in the multiple delay phase-locked loop that the present invention proposes, by sampling (namely The above-mentioned coarse time-to-digital converter 111 converts the input time difference between the reference clock signal REF and the output signal OUT into a digital signal (Cout)-extraction (that is, the above-mentioned digital-to-time converter 112 restores the digital signal Cout to a time-domain signal , the digital-to-time converter 112 continues to output the restored time-domain signal to the subtractor 113 and subtract it from the reference clock signal REF to obtain the phase difference of the coarse time-to-digital converter 111)-sampling (that is, the above-mentioned phase difference sending To the pulse reduction type time-to-digital converter 114 to obtain the output signal PSout), the accuracy of the time-to-digital converter is improved to improve the quantization noise. In addition, the present invention uses a pulse reduction type time-to-digital converter, which does not need to use additional time amplifiers to convert the phase difference Amplification, the linearity of the time-to-digital converter processing module is increased, and the input range can also be enlarged, that is, the present invention replaces the time amplifier, and the non-linear characteristics caused by the use of the time amplifier can be avoided.

Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as limiting the present invention. Various modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the above disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (6)

1. A multiple delay phase-locked loop with a high-precision time-to-digital converter, comprising a time-to-digital converter processing module (11), a digital-to-analog converter (12), a voltage-controlled oscillator (13), a frequency divider (16 ), digital control circuit (14) and data selector (15), it is characterized in that, described time-to-digital converter processing module (11) is provided with successively connected rough time-to-digital converter (111), digital time converter (112), subtractor (113) and pulse reduction type time-to-digital converter (114); wherein, the reference clock signal (REF) and multiple Delay the output signal (OUT) of the last feedback of the phase-locked loop, and convert the time difference between the input of the reference clock signal (REF) and the output signal (OUT) into a corresponding digital signal (Cout) and output it to the A digital-to-time converter (112) restores the digital signal (Cout) to a time-domain signal, and the digital-to-time converter (112) outputs the restored time-domain signal to the subtractor (113) and is combined with the The reference clock signal (REF) is subtracted to obtain the phase difference of the coarse time-to-digital converter (111), and the subtractor (113) sends the obtained phase difference to the pulse reduction time-to-digital converter ( 114) to obtain the pulse output signal (PSout), and finally send the digital signal (Cout) and the pulse output signal (PSout) into the digital-to-analog converter (12) to obtain an analog output signal (DACsum), which is used for control and the digital The frequency of the output signal of the voltage-controlled oscillator (13) connected to the analog-to-analog converter (12). 2. have the multiple delay phase-locked loop of high-accuracy time-to-digital converter as claimed in claim 1, it is characterized in that, The analog output signal is a voltage signal. 3. have the multiple delay phase-locked loop of high precision time-to-digital converter as claimed in claim 1, it is characterized in that, The input range of the coarse time-to-digital converter (111) is larger than that of the pulse reduction type time-to-digital converter (114) with the same number of bits. 4. as claimed in claim 1 or 3 with the multiple delay phase-locked loop of high-accuracy time-to-digital converter, it is characterized in that, The coarse time-to-digital converter (111) is a flash time-to-digital converter. 5. have the multiple delay phase-locked loop of high precision time-to-digital converter as claimed in claim 1, it is characterized in that, The pulse reduction type time-to-digital converter (114) comprises: A time-delay chain comprises multi-stage buffers, and each stage buffer is made up of two inverters with different delays; the input end of the time-delay chain inputs the phase of the described subtractor (113) of the preceding stage difference, the phase difference gradually decreases through the delay of each stage buffer in the delay chain until reaching the last stage buffer; A D-type flip-flop, whose input end is connected with the output end of the described time-delay chain, and it collects the pulse signal output by each stage buffer of the described time-delay chain, finally obtains the described pulse reduction type time-to-digital converter (114 ) output pulse output signal (PSout). 6. have the multiple delay phase-locked loop of high-accuracy time-to-digital converter as claimed in claim 5, it is characterized in that, The formula calculated by the pulse reduction type time-to-digital converter (114) is T=N*dt+error, wherein, what T represents is the phase difference, and what N represents is the number of D-type flip-flop output as 1, and dt is Accuracy of the pulse-reducing time-to-digital converter, error is the quantization error of the pulse-reducing time-to-digital converter.