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CN110209360B - M.2-form storage device based on PCIe signal-to-eMMC - Google Patents

M.2-form storage device based on PCIe signal-to-eMMC Download PDF

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Publication number
CN110209360B
CN110209360B CN201910574441.5A CN201910574441A CN110209360B CN 110209360 B CN110209360 B CN 110209360B CN 201910574441 A CN201910574441 A CN 201910574441A CN 110209360 B CN110209360 B CN 110209360B
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port
capacitor
emmc
resistor
module
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CN110209360A (en
Inventor
马保军
张治宇
谭小兵
汪川川
韦西妙
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Emdoor Digital Technology Co ltd
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Emdoor Digital Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The invention provides an M.2-form storage device based on conversion of PCIe signals into eMMC, which comprises a golden finger module, a PCIe-to-eMMC controller module and an eMMC module which are connected with a host-side M.2 connector, wherein the eMMC module comprises an eMMC storage chip, and the PCIe-to-eMMC controller module converts PCIe signals input by the golden finger module into eMMC signals and outputs the eMMC signals to the eMMC module for storage. By adopting the technical scheme of the invention, a PCIe-to-eMMC signal controller and an eMMC storage device are integrated on a standard M.2 card, so that a novel storage device and a storage selection mode are realized, the structure is small and exquisite, the performance is better, the cost of the storage scheme is reduced, and the cost performance advantage is enhanced.

Description

M.2-form storage device based on PCIe signal-to-eMMC
Technical Field
The present invention relates to a memory device, and more particularly, to a memory device in m.2 format based on PCIe signal to eMMC.
Background
With the continuous development of computers, the types of computer storage devices are more and more, the speed is faster and the price is higher. At present, most of computers in the market support SSDs with PCIe NVMe M.2 interfaces, and simultaneously are compatible with SSDs with SATA interfaces, so that users can replace the SSDs conveniently. The cost of the scheme merchant or the integrated merchant is relatively high when the whole machine is matched with SSD for shipment, and the price of the scheme merchant or the integrated merchant is sensitive to the price under the condition of homogeneous appearance and performance.
Disclosure of Invention
Aiming at the technical problems, the invention discloses a memory device in an M.2 form based on converting PCIe signals into eMMC, which has obvious cost advantage compared with SSD; compared with a mechanical hard disk, the performance and the structure size of the hard disk have great advantages.
In this regard, the invention adopts the following technical scheme:
The utility model provides a memory device based on M.2 forms of eMMC is changeed to PCIe signal, its golden finger module, PCIe that includes being connected with host computer end M.2 connector change eMMC controller module, eMMC module, the eMMC module contains eMMC memory chip, PCIe changes eMMC controller module to the PCIe signal of golden finger module input and changes eMMC signal output into eMMC module and store.
As a further improvement of the invention, the golden finger module comprises a circuit compatible with the M.2B-KEY and the M-KEY.
As a further improvement of the invention, the golden finger module comprises a golden finger J1 and a power supply circuit, wherein the golden finger J1 comprises a 3.3V power interface, a KEY B interface and a KEY M interface, the 3.3V power interface is connected with the eMMC module through the power supply circuit for supplying power, and the 3.3V power interface is connected with the PCIe-to-eMMC controller module for supplying power.
As a further improvement of the invention, the power supply circuit comprises an LDO chip U3, a resistor R27, a capacitor C19, a capacitor C20 and a capacitor C21, wherein the LDO chip U3 comprises a VIN end, a VOUT end, an EN end, a NC end and a GND end, the 3.3V power interface is connected with one end of the resistor R27, one end of the capacitor C19 and the VIN end, the other end of the resistor R27 is connected with one end of the capacitor C20 and the EN end, and the VOUT end is connected with one end of the eMMC module and one end of the capacitor C21; the VOUT terminal, the other terminal of the capacitor C19, the other terminal of the capacitor C20, and the other terminal of the capacitor C21 are grounded.
Further, the model of the LDO chip U3 is WL2803E18-5/TR.
Further, the model number of the golden finger J1 is NASM0-M6701-TP15.
As a further improvement of the invention, the PCIe to eMMC controller module includes a control chip U1,
The control chip U1 includes a pe_rext port, a pe_rxm port, a pe_rxp port, a pe_txp port, a pe_txm port, a pe_ REFCLKM port, a pe_ REFCLKP port, a pe_rst# port, a clkreq# port, an io0_ LDOSEL port, a pe_33VCCAIN port, an ldo_vin port, a 33vin_1 port, a 33vin_2 port, an mmc_io_18vin_1 port, an mmc_io_18vin_2 port, an ldo_12VOUT port, a pe_pdl_12 VCCAIN port, a core_12VCCD port, an ldo_cap port, an mmc_clk port, an mmc_cmd_port, an mmc_d0 port to an mmc_d7 port, an nc_1 port to an nc_15 port;
The golden finger J1 comprises PERN0/SATA_BP port, PERP0/SATA_BN port, PETN0/SATA_AN port, PETP0/SATA_A+ port, REFCLKN port, REFCLKP port, CLKREQ port and PERST port;
The PE_REXT port is connected with a resistor and then grounded; the PE_RXM port is connected with a PETN0/SATA_AN port, the PE_RXP port is connected with a PETP0/SATA_A+ port, the PE_TXP port is connected with a PERP0/SATA_BN port, the PE_TXM port is connected with a PERN0/SATA_BP port, the PE_ REFCLKM port is connected with a REFCLKN port, the PE_ REFCLKP port is connected with a REFCLKP port, the PE_RST# port is connected with a PERST# port, the CLKREQ# port is connected with a CLKREQ# port, and the IO0_ LDOSEL port is connected with a 3.3V power interface;
The PE_33VCCAIN port is connected with one end of a magnetic bead FB2 and one end of a capacitor C9, the other end of the magnetic bead FB2 is connected with a 3.3V power interface and one end of a capacitor C1, and the other end of the capacitor C9 and the other end of the capacitor C1 are grounded; the LDO_VIN port, the 33VIN_1 port and the 33VIN_2 port are connected with a 3.3V power interface; the MMC_IO_18VIN_1 port is connected with the VOUT end of the LDO chip U3 and one end of a capacitor C2, and the other end of the capacitor C2 is grounded; the MMC_IO_18VIN_2 port is connected with the VOUT end of the LDO chip U3, one end of the capacitor C3 and one end of the capacitor C4, and the other end of the capacitor C3 and the other end of the capacitor C4 are grounded.
The LDO_1P2A_EMMC signal output end is formed by connecting the port of the LDO_12VOUT with one end of the capacitor C5, and the other end of the capacitor C5 is grounded; the PE_PDLL_12VCCAIN port is connected with one end of a capacitor C6 and one end of a magnetic bead FB1, the other end of the magnetic bead FB1 is connected with a +V1P2A_EMMC signal output end, the core_12VCCD port is connected with one end of a capacitor C7 and a +V1P2A_EMMC signal output end, and the other end of the capacitor C6 and the other end of the capacitor C7 are grounded; the LDO_CAP port is connected with one end of a capacitor C8, and the other end of the capacitor C8 is grounded.
As a further improvement of the present invention, the eMMC module includes an eMMC memory chip U2, where the memory chip U2 includes a CLK port, a CMD port, an RSTN port, a DAT0 port to DAT7 port, a VCCQ port, a VCC port, a VDDI port, and a VSS port, the CLK port is connected to the mmc_clk port of the control chip U1, the CMD port is connected to the mmc_cmd port of the control chip U1, and the mmc_d0 port to mmc_d7 port are connected to the DAT0 port to DAT7 port, respectively.
The PE_RST# port of the control chip U1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the RSTN port and one end of a resistor R3, and the other end of the resistor R3 is grounded; the CMD port is connected with one end of a resistor R7, the DAT0 port is connected with one end of a resistor R8, the DAT1 port is connected with one end of a resistor R9, the DAT2 port is connected with one end of a resistor R10, the DAT3 port is connected with one end of a resistor R11, the DAT4 port is connected with one end of a resistor R12, the DAT5 port is connected with one end of a resistor R13, the DAT6 port is connected with one end of a resistor R14, the DAT7 port is connected with one end of a resistor R15, and the other ends of the resistors R7-R15 are connected with the VOUT end of an LDO chip U3; the VCCQ port is connected with the VOUT end of the LDO chip U3, the capacitor C14 and the capacitor C15, and the capacitor C14 and the capacitor C15 are grounded; the VCC port is connected with the 303V power interface, the capacitor C16 and the capacitor C17, and the capacitor C16 and the capacitor C17 are grounded; the VDDI port is connected with a capacitor C18; the VSS port is grounded.
As a further improvement of the present invention, the control chip U1 is of model BH720.
Compared with the prior art, the invention has the beneficial effects that:
By adopting the technical scheme of the invention, a PCIe-to-eMMC signal controller and an eMMC storage device are integrated on a standard M.2 card, so that a new form of storage equipment and a storage selection mode are realized, the cost of the storage scheme is reduced, the whole machine shipment cost of the scheme manufacturer is reduced, and the cost performance advantage is enhanced; compared with SSD, the storage device has obvious cost advantage; compared with a mechanical hard disk, the structure is smaller, and the performance is better; the scheme or the integration manufacturer has more options in shipment.
Drawings
FIG. 1 is a block diagram of one embodiment of the invention.
FIG. 2 is a circuit diagram of a golden finger module and a power supply circuit according to an embodiment of the present invention.
Fig. 3 is a circuit diagram of a PCIe to eMMC controller module according to one embodiment of the invention.
Fig. 4 is a circuit diagram of an eMMC module according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention are described in further detail below.
As shown in fig. 1-4, a storage device in m.2 form based on converting PCIe signals into eMMC signals, which includes a golden finger module connected with a host end m.2 connector, a PCIe converting eMMC controller module, and an eMMC module, where the eMMC module includes an eMMC memory chip, and the PCIe converting eMMC controller module converts PCIe signals input by the golden finger module into eMMC signals and outputs the eMMC signals to the eMMC module for storage.
The golden finger module comprises a circuit compatible with the M.2B-KEY and the M-KEY. The golden finger module comprises a golden finger J1 and a power supply circuit, wherein the golden finger J1 comprises a 3.3V power interface, a KEY B interface and a KEY M interface, the 3.3V power interface is connected with the eMMC module through the power supply circuit for supplying power, and the 3.3V power interface is connected with the PCIe-to-eMMC controller module for supplying power.
The power supply circuit comprises an LDO chip U3, a resistor R27, a capacitor C19, a capacitor C20 and a capacitor C21, wherein the LDO chip U3 comprises a VIN end, a VOUT end, an EN end, an NC end and a GND end, the 3.3V power interface is connected with one end of the resistor R27, one end of the capacitor C19 and the VIN end, the other end of the resistor R27 is connected with one end of the capacitor C20 and the EN end, and the VOUT end is connected with the eMMC module and one end of the capacitor C21; the VOUT terminal, the other terminal of the capacitor C19, the other terminal of the capacitor C20, and the other terminal of the capacitor C21 are grounded.
The PCIe to eMMC controller module includes a control chip U1, where the control chip U1 includes a pe_rext port, a pe_rxm port, a pe_rxp port, a pe_txp port, a pe_txm port, a pe_ REFCLKM port, a pe_ REFCLKP port, a pe_rst# port, a clkreq# port, an io0_ LDOSEL port, a pe_33VCCAIN port, an ldo_vin port, an 33vin_1 port, an 33vin_2 port, an mmc_io_18vin_1 port, an mmc_io_18vin_2 port, an ldo_12VOUT port, a pe_pdll_12VCCAIN port, a core_12VCCD port, an ldo_cap port, an mmc_clk port, an mmc_cmd port, an mmc_d0 port to an mmc_d7 port, and an nc_1 port to nc_15 port;
The golden finger J1 comprises PERN0/SATA_BP port, PERP0/SATA_BN port, PETN0/SATA_AN port, PETP0/SATA_A+ port, REFCLKN port, REFCLKP port, CLKREQ port and PERST port;
The PE_REXT port is connected with a resistor and then grounded; the PE_RXM port is connected with a PETN0/SATA_AN port, the PE_RXP port is connected with a PETP0/SATA_A+ port, the PE_TXP port is connected with a PERP0/SATA_BN port, the PE_TXM port is connected with a PERN0/SATA_BP port, the PE_ REFCLKM port is connected with a REFCLKN port, the PE_ REFCLKP port is connected with a REFCLKP port, the PE_RST# port is connected with a PERST# port, the CLKREQ# port is connected with a CLKREQ# port, and the IO0_ LDOSEL port is connected with a 3.3V power interface;
The PE_33VCCAIN port is connected with one end of a magnetic bead FB2 and one end of a capacitor C9, the other end of the magnetic bead FB2 is connected with a 3.3V power interface and one end of a capacitor C1, and the other end of the capacitor C9 and the other end of the capacitor C1 are grounded;
the LDO_VIN port, the 33VIN_1 port and the 33VIN_2 port are connected with a 3.3V power interface;
The MMC_IO_18VIN_1 port is connected with the VOUT end of the LDO chip U3 and one end of a capacitor C2, and the other end of the capacitor C2 is grounded; the MMC_IO_18VIN_2 port is connected with the VOUT end of the LDO chip U3, one end of the capacitor C3 and one end of the capacitor C4, and the other end of the capacitor C3 and the other end of the capacitor C4 are grounded.
The LDO_1P2A_EMMC signal output end is formed by connecting the port of the LDO_12VOUT with one end of the capacitor C5, and the other end of the capacitor C5 is grounded; the PE_PDLL_12VCCAIN port is connected with one end of a capacitor C6 and one end of a magnetic bead FB1, the other end of the magnetic bead FB1 is connected with a +V1P2A_EMMC signal output end, the core_12VCCD port is connected with one end of a capacitor C7 and a +V1P2A_EMMC signal output end, and the other end of the capacitor C6 and the other end of the capacitor C7 are grounded; the LDO_CAP port is connected with one end of a capacitor C8, and the other end of the capacitor C8 is grounded.
The eMMC module comprises an eMMC memory chip U2, wherein the memory chip U2 comprises a CLK port, a CMD port, a RSTN port, a DAT0 port-DAT 7 port, a VCCQ port, a VCC port, a VDDI port and a VSS port,
The CLK port is connected with the MMC_CLK end of the control chip U1, the CMD port is connected with the MMC_CMD port of the control chip U1, and the MMC_D0 port-MMC_D7 port are respectively connected with the DAT0 port-DAT7 port;
The PE_RST# port of the control chip U1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the RSTN port and one end of a resistor R3, and the other end of the resistor R3 is grounded;
The CMD port is connected with one end of a resistor R7, the DAT0 port is connected with one end of a resistor R8, the DAT1 port is connected with one end of a resistor R9, the DAT2 port is connected with one end of a resistor R10, the DAT3 port is connected with one end of a resistor R11, the DAT4 port is connected with one end of a resistor R12, the DAT5 port is connected with one end of a resistor R13, the DAT6 port is connected with one end of a resistor R14, the DAT7 port is connected with one end of a resistor R15, and the other ends of the resistors R7-R15 are connected with the VOUT end of an LDO chip U3; the VCCQ port is connected with the VOUT end of the LDO chip U3, the capacitor C14 and the capacitor C15, and the capacitor C14 and the capacitor C15 are grounded; the VCC port is connected with the 303V power interface, the capacitor C16 and the capacitor C17, and the capacitor C16 and the capacitor C17 are grounded; the VDDI port is connected with a capacitor C18; the VSS port is grounded.
In this embodiment, the model of the control chip U1 is BH720. The model of the LDO chip U3 is WL2803E18-5/TR. The model of the golden finger J1 is NASM0-M6701-TP15.
The embodiment is an implementation scheme of a memory device with a standard m.2 interface, which integrates a PCIe to eMMC signal controller and an eMMC memory device on a standard m.2 card, so that the structure of the memory device is smaller and the cost is lower.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (6)

1. A memory device of m.2 form based on PCIe signal to eMMC, characterized in that: the device comprises a golden finger module, a PCIe-to-eMMC controller module and an eMMC module, wherein the golden finger module, the PCIe-to-eMMC controller module and the eMMC module are connected with a host M.2 connector, the eMMC module comprises an eMMC memory chip, and the PCIe-to-eMMC controller module converts PCIe signals input by the golden finger module into eMMC signals and outputs the eMMC signals to the eMMC module for storage;
The PCIe to eMMC controller module includes a control chip U1,
The control chip U1 includes a pe_rext port, a pe_rxm port, a pe_rxp port, a pe_txp port, a pe_txm port, a pe_ REFCLKM port, a pe_ REFCLKP port, a pe_rst# port, a clkreq# port, an io0_ LDOSEL port, a pe_33VCCAIN port, an ldo_vin port, a 33vin_1 port, a 33vin_2 port, an mmc_io_18vin_1 port, an mmc_io_18vin_2 port, an ldo_12VOUT port, a pe_pdl_12 VCCAIN port, a core_12VCCD port, an ldo_cap port, an mmc_clk port, an mmc_cmd_port, an mmc_d0 port to an mmc_d7 port, an nc_1 port to an nc_15 port;
The golden finger J1 comprises PERN0/SATA_BP port, PERP0/SATA_BN port, PETN0/SATA_AN port, PETP0/SATA_A+ port, REFCLKN port, REFCLKP port, CLKREQ port and PERST port;
The PE_REXT port is connected with a resistor and then grounded; the PE_RXM port is connected with a PETN0/SATA_AN port, the PE_RXP port is connected with a PETP0/SATA_A+ port, the PE_TXP port is connected with a PERP0/SATA_BN port, the PE_TXM port is connected with a PERN0/SATA_BP port, the PE_ REFCLKM port is connected with a REFCLKN port, the PE_ REFCLKP port is connected with a REFCLKP port, the PE_RST# port is connected with a PERST# port, the CLKREQ# port is connected with a CLKREQ# port, and the IO0_ LDOSEL port is connected with a 3.3V power interface;
The PE_33VCCAIN port is connected with one end of a magnetic bead FB2 and one end of a capacitor C9, the other end of the magnetic bead FB2 is connected with a 3.3V power interface and one end of a capacitor C1, and the other end of the capacitor C9 and the other end of the capacitor C1 are grounded;
the LDO_VIN port, the 33VIN_1 port and the 33VIN_2 port are connected with a 3.3V power interface;
The MMC_IO_18VIN_1 port is connected with the VOUT end of the LDO chip U3 and one end of a capacitor C2, and the other end of the capacitor C2 is grounded; the MMC_IO_18VIN_2 port is connected with the VOUT end of the LDO chip U3, one end of the capacitor C3 and one end of the capacitor C4, and the other end of the capacitor C3 and the other end of the capacitor C4 are grounded;
The LDO_1P2A_EMMC signal output end is formed by connecting the port of the LDO_12VOUT with one end of the capacitor C5, and the other end of the capacitor C5 is grounded; the PE_PDLL_12VCCAIN port is connected with one end of a capacitor C6 and one end of a magnetic bead FB1, the other end of the magnetic bead FB1 is connected with a +V1P2A_EMMC signal output end, the core_12VCCD port is connected with one end of a capacitor C7 and a +V1P2A_EMMC signal output end, and the other end of the capacitor C6 and the other end of the capacitor C7 are grounded; the LDO_CAP port is connected with one end of a capacitor C8, and the other end of the capacitor C8 is grounded.
2. The memory device of claim 1 in m.2 form based on PCIe signaling eMMC, wherein: the golden finger module comprises a circuit compatible with the M.2B-KEY and the M-KEY.
3. The memory device of m.2 form based on PCIe signaling eMMC according to claim 2, wherein: the golden finger module comprises a golden finger J1 and a power supply circuit, wherein the golden finger J1 comprises a 3.3V power interface, a KEY B interface and a KEY M interface, the 3.3V power interface is connected with the eMMC module through the power supply circuit for supplying power, and the 3.3V power interface is connected with the PCIe-to-eMMC controller module for supplying power.
4. The memory device of m.2 form based on PCIe signaling eMMC according to claim 3, wherein: the power supply circuit comprises an LDO chip U3, a resistor R27, a capacitor C19, a capacitor C20 and a capacitor C21, wherein the LDO chip U3 comprises a VIN end, a VOUT end, an EN end, an NC end and a GND end, the 3.3V power interface is connected with one end of the resistor R27, one end of the capacitor C19 and the VIN end, the other end of the resistor R27 is connected with one end of the capacitor C20 and the EN end, and the VOUT end is connected with the eMMC module and one end of the capacitor C21; the VOUT terminal, the other terminal of the capacitor C19, the other terminal of the capacitor C20, and the other terminal of the capacitor C21 are grounded.
5. The memory device of claim 1 in m.2 form based on PCIe signaling eMMC, wherein: the eMMC module comprises an eMMC memory chip U2, wherein the memory chip U2 comprises a CLK port, a CMD port, a RSTN port, a DAT0 port-DAT 7 port, a VCCQ port, a VCC port, a VDDI port and a VSS port,
The CLK port is connected with the MMC_CLK end of the control chip U1, the CMD port is connected with the MMC_CMD port of the control chip U1, and the MMC_D0 port-MMC_D7 port are respectively connected with the DAT0 port-DAT7 port;
The PE_RST# port of the control chip U1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the RSTN port and one end of a resistor R3, and the other end of the resistor R3 is grounded;
The CMD port is connected with one end of a resistor R7, the DAT0 port is connected with one end of a resistor R8, the DAT1 port is connected with one end of a resistor R9, the DAT2 port is connected with one end of a resistor R10, the DAT3 port is connected with one end of a resistor R11, the DAT4 port is connected with one end of a resistor R12, the DAT5 port is connected with one end of a resistor R13, the DAT6 port is connected with one end of a resistor R14, the DAT7 port is connected with one end of a resistor R15, and the other ends of the resistors R7-R15 are connected with the VOUT end of an LDO chip U3;
The VCCQ port is connected with the VOUT end of the LDO chip U3, the capacitor C14 and the capacitor C15, and the capacitor C14 and the capacitor C15 are grounded;
the VCC port is connected with the 303V power interface, the capacitor C16 and the capacitor C17, and the capacitor C16 and the capacitor C17 are grounded;
The VDDI port is connected with a capacitor C18; the VSS port is grounded.
6. The memory device of m.2 form based on PCIe signaling eMMC according to claim 2, wherein: the model of the control chip U1 is BH720, and the model of the LDO chip U3 is WL2803E18-5/TR.
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