CN110112206A - A kind of gallium oxide junction field effect transistor - Google Patents

Abstract

The invention discloses a gallium oxide junction field effect transistor and relates to the technical field of semiconductor devices. Aiming at the disadvantages of large gate leakage or poor gate control characteristics in transistors made of gallium oxide in the prior art, this technical solution is proposed. A p-type oxide semiconductor layer is arranged between the gate and the gallium oxide channel layer to form a heterogeneous PN junction, which can ensure good gate control characteristics while effectively reducing gate leakage current.

Description

A gallium oxide junction field effect transistor

technical field

The invention relates to the technical field of semiconductor devices, in particular to a gallium oxide junction field effect transistor.

Background technique

Gallium oxide (Ga ₂ O ₃ ) semiconductor has an ultra-wide bandgap of up to 4.8eV and an ultra-large critical breakdown field strength of 8MV/cm, much higher than the traditional semiconductor materials silicon, silicon carbide and gallium nitride, which means that the same device GaO-based field-effect transistors (FETs) have higher withstand voltage characteristics at a lower size. In addition, gallium oxide field effect transistors also have the advantages of high temperature resistance, radiation resistance, high reliability and low cost.

However, the existing gallium oxide field effect transistors all use Schottky gates or metal-insulator-semiconductor (MIS) structure gates (see literature M. Higashiwaki, et al., Gallium oxide (Ga ₂ O ₃ ) metal- semiconductor field-effect transistors on single-crystalβ-Ga ₂ O ₃ (010) substrates, Applied Physics Letters 100(1), 013504, 2011, literature N. Moser, et al., Ge-Dopedβ-Ga2O3 MOSFETs, IEEE Electron Device letters 38(6), 775,2017 and Chinese patent CN107742647A), there are disadvantages of large gate leakage or poor gate control characteristics.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the object of the present invention is to provide a gallium oxide junction field effect transistor, which realizes low gate leakage and good gate control characteristics of the device by adopting a heterogeneous PN junction gate structure.

A gallium oxide junction field effect transistor according to the present invention comprises a substrate and a gallium oxide channel layer which are sequentially stacked, and the side of the gallium oxide channel layer away from the substrate is provided with a source and a drain A p-type oxide semiconductor layer is also provided between the source and the drain, so that the p-type oxide semiconductor layer and the gallium oxide channel layer form a heterogeneous PN junction; the p-type oxide semiconductor layer- One side is connected to the gallium oxide channel layer, and the other side is provided with a gate.

Preferably, the p-type oxide semiconductor layer and the gate are Ohmic contacts or Schottky contacts.

Preferably, the p-type oxide semiconductor layer has an amorphous or polycrystalline structure.

Preferably, the p-type oxide semiconductor layer has a single-layer or multi-layer structure.

Preferably, the hole concentration of the p-type oxide semiconductor layer is 1×10 ¹⁷ /cm ³ to 1×10 ²⁰ /cm ³ .

Preferably, the p-type oxide semiconductor layer is made of NiO or Cu ₂ O.

Preferably, the gallium oxide channel layer has a single crystal structure.

Preferably, the doping concentration of the gallium oxide channel layer is 5×10 ¹⁵ cm ^-3 to 1×10 ¹⁸ cm ^-3 .

Preferably, the gallium oxide channel layer has a thickness of 10 nm˜10 μm.

Preferably, the source is in ohmic contact with the gallium oxide channel layer, and the drain is in ohmic contact with the gallium oxide channel layer.

A gallium oxide junction field effect transistor according to the present invention has the advantage of forming a heterogeneous PN junction by using an amorphous or polycrystalline p-type oxide semiconductor layer and a single crystal gallium oxide channel layer at the gate , while effectively reducing the gate leakage current, it can ensure good gate control characteristics.

Description of drawings

FIG. 1 is a schematic structural diagram of a gallium oxide junction field effect transistor according to the present invention.

Description of drawings: 101-substrate; 102-gallium oxide channel layer; 103-source; 104-drain; 105-p-type oxide semiconductor layer; 106-gate.

Detailed ways

As shown in FIG. 1 , a gallium oxide junction field effect transistor according to the present invention includes a substrate 101 and a gallium oxide channel layer 102 stacked in sequence, and the gallium oxide channel layer 102 is far away from the substrate 101 A source 103 and a drain 104 are provided on one side. A p-type oxide semiconductor layer 105 is further provided between the source electrode 103 and the drain electrode 104, so that the p-type oxide semiconductor layer 105 and the gallium oxide channel layer 102 form a heterogeneous PN junction. One side of the p-type oxide semiconductor layer 105 is connected to the gallium oxide channel layer 102 , and the other side is provided with a gate 106 .

The p-type oxide semiconductor layer 105 can be prepared by magnetron sputtering, solution method, metal oxide method, physical or chemical vapor deposition and other methods. The material can be NiO, Cu ₂ O or other single-layer or multi-layer p-type oxide semiconductors, or amorphous or polycrystalline structure. The hole concentration of the p-type oxide semiconductor layer 105 is 1×10 ¹⁷ /cm ³ to 1×10 ²⁰ /cm ³ .

The gallium oxide channel layer 102 has a single crystal structure with a thickness of 10 nm to 10 μm, and its n-type doping concentration is 5×10 ¹⁵ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ .

The substrate 101 is an insulating substrate, which may be materials such as gallium oxide, aluminum oxide, diamond, silicon carbide, or silicon.

The source 103 and the drain 104 can be manufactured by depositing Ti/Au alloy or Ti/Al/Ni/Au alloy by magnetron sputtering or electron beam evaporation, respectively forming ohmic contacts with the surface of the gallium oxide channel layer 102 .

The gate 106 can be made by depositing Ni/Au alloy or Pt/Au alloy by means of magnetron sputtering or electron beam evaporation, and forms an ohmic or Schottky contact with the surface of the p-type oxide semiconductor layer 105 .

A gallium oxide junction field effect transistor proposed in the present invention forms a heterogeneous PN junction by using an amorphous or polycrystalline p-type oxide semiconductor layer 105 and a single crystal gallium oxide channel layer 102 to form a junction gate pole structure. When a negative voltage is applied to the gate 106, the heterogeneous PN junction is reverse-biased, the gallium oxide channel layer 102 is depleted, and the transistor is turned off; when a positive voltage is applied to the gate 106, the heterogeneous PN junction is forward-biased, and the gallium oxide channel layer 102 is turned off. The depletion depth of the channel layer 102 is reduced to realize effective control of the transistor current; the junction gate structure can effectively reduce the leakage current of the gate 106 while ensuring that the transistor has good gate control characteristics.

For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and ideas described above, and all these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims (10)

1. a kind of gallium oxide junction field effect transistor, including the substrate (101) being cascading and gallium oxide channel layer (102), the gallium oxide channel layer (102) is equipped with source electrode (103) and drain electrode (104) far from the side of substrate (101)；It is special Sign is, is additionally provided with p-type oxide semiconductor layer (105) between the source electrode (103) and drain electrode (104), so that p-type aoxidizes Object semiconductor layer (105) and gallium oxide channel layer (102) form PN heterojunction；The p-type oxide semiconductor layer (105) one Side is connect with gallium oxide channel layer (102), and the other side is equipped with grid (106).

2. gallium oxide junction field effect transistor according to claim 1, which is characterized in that the p-type oxide is partly led Body layer (105) and grid (106) are Ohmic contact or Schottky contacts.

3. gallium oxide junction field effect transistor according to claim 1 or claim 2, which is characterized in that the p-type oxide half Conductor layer (105) is amorphous or polycrystalline structure.

4. gallium oxide junction field effect transistor according to claim 3, which is characterized in that the p-type oxide is partly led Body layer (105) is single or multi-layer structure.

5. according to claim 1 or the 4 gallium oxide junction field effect transistors, which is characterized in that the p-type oxide half The hole concentration of conductor layer (105) is 1 × 10¹⁷/cm³~1 × 10²⁰/cm³。

6. according to any gallium oxide junction field effect transistor of claim 5, which is characterized in that the p-type oxide Semiconductor layer (105) is by NiO or Cu₂O is made.

7. gallium oxide junction field effect transistor according to claim 1, which is characterized in that the gallium oxide channel layer It (102) is mono-crystalline structures.

8. gallium oxide junction field effect transistor according to claim 7, which is characterized in that the gallium oxide channel layer (102) doping concentration is 5 × 10¹⁵cm^-3~1 × 10¹⁸cm^-3。

9. gallium oxide junction field effect transistor according to claim 7, which is characterized in that the gallium oxide channel layer (102) with a thickness of 10nm~10 μm.

10. gallium oxide junction field effect transistor according to claim 1, which is characterized in that the source electrode (103) and oxygen Changing gallium channel layer (102) is Ohmic contact, and the drain electrode (104) and gallium oxide channel layer (102) are Ohmic contact.