CN110571275A - Preparation method of gallium oxide MOSFET - Google Patents

Abstract

A gallium oxide MOSFET semiconductor device, comprising: a gallium oxide-based substrate; a drain and a source disposed on the gallium oxide-based substrate; at least the region below the drain and the source in the gallium oxide-based substrate Highly doped gallium oxide is provided with a doping concentration of 10 ¹⁷ ‑10 ²⁰ cm ^‑3 ; a gate dielectric layer is provided on the gallium oxide-based substrate not covering the source and drain regions; the gate is provided on the over the gate dielectric layer. Compared with the original MOSFET device using metal with low work function as the source-drain electrode, using the device of the present invention can effectively improve the problem of excessive device threshold voltage or low switching ratio existing in the original device.

Description

Preparation method of gallium oxide MOSFET

technical field

The invention relates to the field of semiconductors, and further relates to a preparation method of gallium oxide MOSFET.

Background technique

At present, gallium oxide materials are still difficult to achieve effective P-type doping, which makes it difficult to easily obtain a high switching ratio for enhancement mode gallium oxide MOSFETs. As for the depletion mode gallium oxide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), although it can be easily realized without using complicated structures or processes, the existing devices also have too high threshold voltage (> 30V) has seriously affected the practical application of the device. Gallium oxide (Ga ₂ O ₃ ) has wide application prospects in high-power devices due to its excellent characteristics, including ultra-wide bandgap (4.8eV) and large breakdown electric field (8MV/cm), and is expected to become a new A generation of semiconductor materials.

However, gallium oxide power enhancement MOSFET has the problems of low current switching ratio and high turn-off threshold voltage of depletion MOSFET. This hinders the effective utilization of gallium oxide materials, so there is an urgent need for a method to improve the switching ratio of gallium oxide devices. The currently proposed method for improving the switching ratio of the enhancement-mode MOSFET is realized through a gate-trough structure or a FinFET (FinField-effect transistor) structure.

At present, gallium oxide materials are difficult to achieve effective P-type doping, so unintentionally doped gallium oxide can only be used as the channel when making enhancement-mode MOSFETs. Unintentionally doped gallium oxide will unintentionally introduce some donor impurities during the material preparation process, resulting in poor insulating properties. Therefore, the leakage current of the enhanced gallium oxide MOSFET is large when it is off, and the device switching ratio is not high.

The fabrication process of MOSFETs with a gate-groove structure and a FinFET structure is complicated, which increases the difficulty and cost of mass production of devices. At the same time, both methods require an etching process, which will introduce a large number of defects and surface states, which will have a greater impact on the performance of the device. Affecting the transport of carriers increases the on-resistance and also makes the contact between the gate dielectric and gallium oxide more prone to breakdown. However, for this method, the process for fabricating the device is simple, and at the same time, no etching process is required.

In addition, for the depletion-type gallium oxide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), although it can be easily realized without using complicated structures or processes, the existing devices also have a threshold voltage that is too high (> 30V ) problem seriously affects the practical application of the device.

Contents of the invention

(1) Technical problems to be solved

In view of this, the object of the present invention is to provide a method for preparing a gallium oxide MOSFET, so as to at least partially solve the above technical problems.

(2) Technical solution

According to one aspect of the present invention, a gallium oxide MOSFET semiconductor device is provided, including:

Gallium oxide-based substrate;

a drain and a source disposed on a gallium oxide-based substrate;

The gallium oxide-based substrate is provided with highly doped gallium oxide at least in the region below the drain and source, with a doping concentration of 10 ¹⁷ -10 ²⁰ cm ^-3 ;

The gate dielectric layer is disposed on the gallium oxide-based substrate not covering the source and drain regions;

The gate is arranged on the gate dielectric layer.

In a further embodiment, the gallium oxide-based substrate is a substrate for making an enhancement-mode gallium oxide MOSFET, including: a semi-insulating β-gallium oxide layer; unintentionally doped β-gallium oxide, disposed on the semi-insulating β-gallium oxide layer above; the doped gallium oxide is arranged in the partial region of the non-intentionally doped β-gallium oxide, and the region is located below the source and the drain.

In a further embodiment, the gallium oxide-based substrate is a substrate for making a depletion-type MOSFET, including: a semi-insulating layer of β-gallium oxide; unintentionally doped β-gallium oxide, disposed on the semi-insulating layer of β-gallium oxide on; doped gallium oxide, disposed on the non-intentionally doped β-gallium oxide.

In a further embodiment, the source and drain metals are high work function metals, such as nickel, platinum or palladium or other metals with a work function higher than 4.5 eV.

In a further embodiment, the doping element for doping gallium oxide is silicon Si, tin Sn or other elements that can make gallium oxide exhibit N-type conductivity.

According to another aspect of the present invention, a method for preparing a gallium oxide enhanced or depleted MOSFET semiconductor device is provided, including:

Prepare a gallium oxide-based substrate;

Doped gallium oxide is provided in at least a part of the gallium oxide-based substrate, with a doping concentration of 10 ¹⁷ -10 ²⁰ cm ^-3 , arranged under the drain and the source on the gallium oxide-based substrate;

Forming the drain and source on top of doped gallium oxide on a gallium oxide substrate,

forming a gate dielectric layer on the gallium oxide-based substrate not covering the source and drain regions;

A gate is formed on the gate dielectric layer.

In a further embodiment, preparing a gallium oxide-based substrate includes: forming a semi-insulating layer of β-gallium oxide; forming an unintentionally doped β-gallium oxide on the semi-insulating layer of β-gallium oxide; Doped gallium oxide is formed in the portion of the gallium that underlies the source and drain electrodes.

In a further embodiment, preparing a gallium oxide-based substrate includes: forming a semi-insulating layer of β-gallium oxide; forming an unintentionally doped β-gallium oxide on the semi-insulating layer of β-gallium oxide; The entire surface area of gallium oxide forms doped gallium oxide.

In a further embodiment, the source and drain metals are metals with a work function higher than 4.5 eV.

In a further embodiment, the doping element for doping gallium oxide is silicon Si, tin Sn or other elements that can make gallium oxide exhibit N-type conductivity.

(3) Beneficial effects

In the present invention, the originally used low work function source-drain electrode metal is replaced by the high work function metal in this solution, which can increase the switching ratio of the device and reduce the leakage current of the device in the off state.

Compared with the more common devices with gate groove structure and FinFET structure, the present invention does not need to use etching process on the working part of gallium oxide in the preparation process, so the etching process causes large gate leakage current and gate leakage current to the device. Problems such as premature breakdown and reduced channel mobility no longer exist in the new scheme.

Compared with the original depletion MOSFET device using metal with low work function as source and drain electrodes, the present invention can effectively improve the problem of excessive device threshold voltage existing in the original device.

The device preparation process is simple and mature, and the process steps used in the device are all mature semiconductor device preparation processes, and has the advantage of being compatible with the silicon material device preparation process.

Description of drawings

1-6 are flow charts of the method for fabricating an enhanced gallium oxide MOSFET according to an embodiment of the present invention.

7-12 are flow charts of the fabrication method of the depleted gallium oxide MOSFET according to the embodiment of the present invention.

13 and 14 are schematic diagrams of an isolation forming method in a method for manufacturing a gallium oxide MOSFET according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In the present invention, the technical terms involved have the following meanings:

MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect transistor that can be widely used in analog circuits and digital circuits.

Work function: Also known as work function and work function, it is defined in solid physics as the minimum energy required to move an electron from the interior of a solid to the surface of the object. In general, the work function refers to the work function of the metal.

Compared with devices that do not use gate-trough structures and FinFET structures, unintentionally doped gallium oxide will unintentionally introduce some donor impurities during material preparation, resulting in poor insulation performance. Therefore, the leakage current of the enhanced gallium oxide MOSFET is large when it is off, and the device switching ratio is not high. If the originally used low work function source and drain electrode metals are replaced with high work function metals in this solution, the switching ratio of the device can be increased and the leakage current of the device in the off state can be reduced.

In view of the above technical shortcomings, the present invention proposes a new device structure, which solves the above problems by using high work function metals and highly doped gallium oxide to form tunneling source-drain contacts. Use the high work function metal used to form the Schottky contact as the source and drain electrode material, and at the same time do a higher concentration of doping on the gallium oxide in contact with the electrode to change the original source and drain contact properties, in order to expect the formation of the source and drain Two potential barriers that are prone to tunneling form a tunneling source-drain contact, thereby achieving the purpose of improving the switching ratio of the enhanced device and reducing the threshold voltage of the depleted device.

An embodiment of the present invention provides a gallium oxide MOSFET semiconductor device, which includes:

Gallium oxide-based substrate;

a drain and a source disposed on a gallium oxide-based substrate;

The gallium oxide-based substrate is provided with doped gallium oxide at least in the area below the drain and the source, and the doping concentration is 10 ¹⁷ -10 ²⁰ cm ^-3 ;

The gate dielectric layer is disposed on the gallium oxide-based substrate not covering the source and drain regions;

The gate is arranged on the gate dielectric layer.

Among them, the gallium oxide substrate can be a substrate based on an enhancement MOSFET or a depletion MOSFET, for example, a gallium oxide-based substrate is an enhancement gallium oxide MOSFET substrate, including: semi-insulating layer β gallium oxide; unintentional doping β Gallium oxide is disposed on the semi-insulating layer of β-gallium oxide; doped gallium oxide is disposed in a partial region of the non-intentionally doped β-gallium oxide, and the region is located below the source and the drain. Among them, the preparation process of the semi-insulating substrate can be β gallium oxide single crystal grown by pulling and growing, and the unintentionally doped gallium oxide buffer layer can be grown by HVPE (hydride vapor phase epitaxy) method, and the growth thickness can be 1 μm. On the (010) surface of the doped β-gallium oxide semi-insulating substrate, the doped gallium oxide is formed by implanting Si atoms into a specific area of gallium oxide through patterned ion implantation. The implantation depth is at least 100nm, and the doping concentration of the implanted area is At 10 ¹⁷ -10 ²⁰ cm ^-3 ; the source and drain electrode metals can be grown by electron beam evaporation deposition or magnetron sputtering; the gate dielectric layer can be prepared by atomic layer deposition (ALD), with a thickness of 30nm; the final gate metal It is grown by electron beam evaporation deposition or magnetron sputtering. The etching process in the manufacturing process is implemented by inductively coupled plasma etching (ICP).

For example, the gallium oxide-based substrate is a depletion-type MOSFET substrate, including: a semi-insulating layer of β-gallium oxide; unintentionally doped β-gallium oxide, which is placed on the semi-insulating layer of β-gallium oxide; doped gallium oxide, which is placed on the unintentionally doped β-gallium oxide. Among them, the preparation process of the semi-insulating substrate can be β gallium oxide single crystal grown by pulling and growing, and the unintentionally doped gallium oxide buffer layer can be grown by HVPE (hydride vapor phase epitaxy) method, and the growth thickness can be 1 μm. On the (010) surface of the doped β-gallium oxide semi-insulating substrate, the doped gallium oxide is formed by implanting Si atoms into the gallium oxide by ion implantation, or can be directly epitaxially grown by epitaxial methods such as MOCVD or MBE to obtain high Doped gallium oxide thin layer, the implantation depth or epitaxial film thickness is at least 100nm; the source and drain electrode metals can be grown by electron beam evaporation deposition or magnetron sputtering, and the gate dielectric layer can be prepared by atomic layer deposition (ALD), The thickness is 30nm; the final gate metal is grown by electron beam evaporation deposition or magnetron sputtering. The etching process in the manufacturing process is implemented by inductively coupled plasma etching (ICP).

In an embodiment of the present invention, the source and drain metals may be one of nickel, platinum or palladium, or other metals with a work function greater than 4.5 eV.

Among them, for doped gallium oxide, the doping element of doped gallium oxide is Si, if the doped gallium oxide is grown by epitaxial growth, it is Sn or Si, and the doping concentration is in the range of 10 ¹⁷ -10 ²⁰ cm ^-3 ' Both can achieve the purpose of the embodiments of the present invention, that is, form two potential barriers prone to tunneling at the source and drain, and form a tunneling source-drain contact, so as to improve the switching ratio of the enhanced device and reduce the threshold voltage of the depleted device.

In order to better understand the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings, but it should be understood that the specific details of the following examples are only used to describe the technical solutions of the present invention, and should not be construed as an explanation of the present invention. limit.

Accompanying drawing 1-6 is a kind of preparation method of enhanced gallium oxide MOSFET, can comprise: carry out inductively coupled plasma (ICP) etch to gallium oxide base substrate, to realize device isolation, etching gas is Cl2 and Ar, The gas flow rate is 15sccm and 5sccm respectively, the radio frequency (RF) power during the etching process is 400W, the etching power is 60W, and the etching depth is >300nm

Partial ion implantation and activation, the window for ion implantation is made through photolithography and development steps, that is, the place where no implantation is performed is covered with photoresist, and then Si atoms are implanted into gallium oxide using an ion implanter, with an implantation depth of at least 100nm. The highest energy is 95keV. After the implantation is completed, heat treatment is carried out at 950° C. for 30 mins in an N ₂ atmosphere to activate the atoms implanted into the gallium oxide.

High work function metal source and drain electrodes are grown and peeled off; a window for metal electrode growth is made through photolithography and development steps, that is, the place where no electrode is grown is covered with photoresist. Finally, use the method of electron beam evaporation deposition or magnetron sputtering to grow the metal nickel Ni film with high work function, and then soak the product in acetone, so the excess metal will fall off, which is called peeling.

Grow gate dielectric; use atomic layer deposition (ALD) to grow gate dielectric Al ₂ O ₃ with a film thickness of 30nm

The gate metal is grown and peeled off; the window for metal electrode growth is made through photolithography and development steps, that is, the place where no electrode is grown is covered with photoresist. Finally, use electron beam evaporation deposition or magnetron sputtering to grow a low work function metal titanium Ti film, and then soak the product in acetone, so the excess metal will fall off, which is called peeling.

Etching the source-drain metal upper gate dielectric, this step can be prepared by using inductively coupled plasma (ICP).

Accompanying drawing 7-12 is a kind of preparation method of depletion mode gallium oxide MOSFET, can comprise the following steps:

Etching realizes device isolation Carry out inductively coupled plasma (ICP) etching to gallium oxide base substrate, to realize device isolation, etching gas is Cl2 and Ar, gas flow rate is respectively 15 sccm and 5 sccm, radio frequency ( RF) power is 400W, etching power is 60W, etching depth > 300nm

Ion implantation and activation, using an ion implanter to implant Si atoms into the gallium oxide, the implantation depth is at least 100nm, and the highest implanted energy is 95keV. After the implantation is completed, heat treatment is carried out at 950° C. for 30 mins in an N ₂ atmosphere to activate the atoms implanted into the gallium oxide.

Grow high work function metal source and drain electrodes, and peel off the window for metal electrode growth through photolithography and development steps, that is, the place where no electrode is grown is covered with photoresist. Finally, use the method of electron beam evaporation deposition or magnetron sputtering to grow the metal nickel Ni film with high work function, and then soak the product in acetone, so the excess metal will fall off, which is called peeling.

Grow gate dielectric Use atomic layer deposition (ALD) method to grow gate dielectric Al ₂ O ₃ , the film thickness is 30nm

The gate metal is grown, and the window for metal electrode growth is made through photolithography and development steps, that is, the place where no electrode is grown is covered with photoresist. Finally, use electron beam evaporation deposition or magnetron sputtering to grow a low work function metal titanium Ti film, and then soak the product in acetone, so the excess metal will fall off, which is called peeling.

Etching the gate dielectric on the source and drain metals can be prepared by inductively coupled plasma (ICP) etching.

Figure 13 and Figure 14 are a method for fabricating a depleted gallium oxide substrate in an embodiment, that is, epitaxially grow a highly doped oxide layer on an unintentionally doped gallium oxide layer by using epitaxial methods such as MOCVD or MBE. The gallium layer is then etched for device isolation.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. A gallium oxide MOSFET semiconductor device, comprising:

A gallium oxide-based substrate;

a drain electrode and a source electrode arranged on the gallium oxide substrate;

Highly doped gallium oxide with a doping concentration of 10 is arranged in the gallium oxide-based substrate at least in the lower regions of the drain electrode and the source electrode¹⁷-10²⁰cm^-3；

The grid dielectric layer is arranged in the area which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;

And the grid electrode is arranged on the grid dielectric layer.

2. The device of claim 1,

The gallium oxide-based substrate is used for manufacturing an enhanced gallium oxide MOSFET and comprises:

a semi-insulating beta gallium oxide layer;

unintentionally doped beta gallium oxide, arranged on the semi-insulating beta gallium oxide layer;

and the doped gallium oxide is arranged in a partial region of the unintentionally doped beta gallium oxide, and the partial region is positioned below the source electrode and the drain electrode.

3. the device of claim 1,

the gallium oxide-based substrate is used for manufacturing a depletion type MOSFET and comprises:

semi-insulating layer beta gallium oxide;

unintentionally doped beta gallium oxide, disposed on the semi-insulating layer beta gallium oxide;

Doped gallium oxide disposed over the unintentionally doped beta gallium oxide.

4. The device of claim 1, wherein the source and drain metals are high work function metals, such as nickel, platinum or palladium or other metals with work function higher than 4.5 eV.

5. The device of claim 1, wherein the doping element of the doped gallium oxide is silicon (Si), tin (Sn) or other element that can cause gallium oxide to exhibit N-type conductivity.

6. A method for preparing a gallium oxide enhancement type or depletion type MOSFET semiconductor device comprises the following steps:

preparing a gallium oxide-based substrate;

The gallium oxide-based substrate is provided with doped gallium oxide in at least partial region with the doping concentration of 10¹⁷-10²⁰cm^-3A gate electrode disposed on the gallium oxide-based substrate;

A drain and a source are formed over the doped gallium oxide of the gallium oxide substrate,

Forming a gate dielectric layer in a region which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;

And forming a grid electrode on the grid dielectric layer.

7. The method of claim 6,

Preparing a gallium oxide-based substrate comprising:

Forming a semi-insulating layer beta gallium oxide;

forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide;

And forming doped gallium oxide in the part of the area which is not intentionally doped with the beta gallium oxide, wherein the area is positioned below the source electrode and the drain electrode.

8. The method of claim 6,

Preparing a gallium oxide-based substrate comprising:

forming a semi-insulating layer beta gallium oxide;

Forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide;

And forming doped gallium oxide on the whole surface area of the unintentionally doped beta gallium oxide.

9. The method of claim 6, wherein the source and drain metals are metals with work functions higher than 4.5 eV.

10. The method according to claim 6, wherein the doping element of the doped gallium oxide is silicon (Si), tin (Sn) or other elements capable of enabling the gallium oxide to show N-type conductivity.