CN110098150A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate, the substrate includes a first region and a second region, the first region has a first source-drain doped region in the substrate; in the first region forming a first protective layer on the base and the first source-drain doped region; after forming the first protective layer, forming a second source-drain doped region in the base of the second region; forming the second source-drain After doping the region, removing the first protective layer; after removing the first protective layer, forming a dielectric layer on the substrate, the first source-drain doped region and the second source-drain doped region; removing part of the dielectric layer, A contact hole is formed in the dielectric layer until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed. The method can reduce damage to the top surface of the second source-drain doped region when forming the contact hole.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, the fabrication of semiconductor devices is constrained by various physical limits due to the pursuit of high device density, high performance, and low cost in semiconductor processes and progress to nanotechnology process nodes.

Manufacturing and design challenges as CMOS devices continue to shrink have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, the fin field effect transistor has more superior performance in terms of channel control and reducing shallow channel effects; the planar gate structure is arranged above the channel, and the fin field effect transistor In the effect transistor, the gate structure is arranged around the fin, therefore, static electricity can be controlled from three sides, and the performance in static electricity control is more prominent.

However, the performance of fin field effect transistors prepared in the prior art is still poor.

Contents of the invention

The technical problem solved by the invention is to provide a semiconductor structure and its forming method to improve the performance of semiconductor devices.

In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, and the first region has a first source-drain doping in the substrate region; forming a first protective layer on the substrate of the first region and the first source-drain doped region; after forming the first protective layer, forming a second source-drain doped region in the substrate of the second region ; After forming the second source-drain doped region, removing the first protective layer; after removing the first protective layer, forming a dielectric layer on the substrate, the first source-drain doped region and the second source-drain doped region and removing part of the dielectric layer until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, and forming a contact hole in the dielectric layer.

Optionally, the thickness of the first protective layer is 3 nanometers to 5 nanometers.

Optionally, the size of the second doped source and drain region along the direction perpendicular to the line connecting the first doped source and drain region and the second doped source and drain region is: 100 nm to 120 nm.

Optionally, the substrate of the first region further has a first gate structure, and the substrates on both sides of the first gate structure have the first source-drain doped regions; the substrate of the second region also has It has a second gate structure, and the substrate on both sides of the second gate structure has the second source-drain doping region.

Optionally, the first protective layer also covers the sidewall of the second gate structure; the step of forming the first protective layer includes: on the substrate and the first source-drain doped region, the first gate The sidewall and top surface of the structure, and the sidewall and top surface of the second gate structure form a first protective film; remove the first protective film on the base of the second region and the top surface of the second gate structure, and form the first The protective layer.

Optionally, the step of forming the first source-drain doped region and the second source-drain doped region includes: forming a first epitaxial layer in the substrate on both sides of the first gate structure; A first protective layer is formed on the base of the region and the first epitaxial layer, on the sidewall and top surface of the first gate structure, and on the sidewall of the second gate structure; after the formation of the first protective layer, the second forming a second epitaxial layer in the substrates on both sides of the gate structure; forming a first photoresist on the substrate of the second region and the second epitaxial layer, as well as the sidewall and top surface of the second gate structure; The first photoresist is a mask, and first dopant ions are doped into the first epitaxial layer to form a first source-drain doped region; after the first source-drain doped region is formed, the first photoresist is removed resist; after removing the first photoresist, form a second photoresist on the base of the first region and the first source-drain doped region, and on the sidewall and top surface of the first gate structure; The second photoresist is a mask, and second doping ions are doped into the second epitaxial layer to form a second source-drain doping region.

Optionally, after forming the second epitaxial layer and before forming the first photoresist, the forming method further includes: forming oxide layer.

Optionally, after forming the first photoresist and before doping the first dopant ions into the first epitaxial layer, the forming method further includes: removing the oxide layer in the first region to expose the first protection layer.

Optionally, the material of the oxide layer includes: silicon oxide; the thickness of the oxide layer is: 20 angstroms-40 angstroms.

Optionally, the material of the first protection layer includes: silicon nitride.

Optionally, the process of removing the first protective layer includes: a wet etching process; parameters of the wet etching process include: the etchant includes phosphoric acid.

Optionally, the substrate further has an isolation structure; the material of the isolation structure includes: silicon oxide.

Optionally, after forming the contact hole, the forming method further includes: forming a plug in the contact hole.

Optionally, the first region is used for PMOS transistors, and the second region is used for forming NMOS transistors.

The present invention also provides a semiconductor structure, which is characterized in that it includes: a base, the base includes a first region and a second region, the base of the first region has a first source-drain doped region; The second source-drain doped region in the substrate; the dielectric layer on the substrate, the dielectric layer has a contact hole exposing the top surface of the first source-drain doped region and the second source-drain doped region.

Optionally, the size of the second doped source and drain region along the direction perpendicular to the line connecting the first doped source and drain region and the second doped source and drain region is: 100 nm to 120 nm.

Optionally, the semiconductor structure further includes: a plug located in the contact hole.

Optionally, the first region is used for PMOS transistors, and the second region is used for forming NMOS transistors.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first region is used to form a PMOS transistor, and the second region is used to form an NMOS transistor. Mobility of electrons, after forming the first source-drain doped region, the second source-drain doped region is formed. In the process of forming the second source-drain doped region, in order to protect the devices in the first region, before forming the second source-drain doped region, a first A protective layer. After forming the second source-drain doped region, removing the first protective layer can reduce the thickness difference between the first source-drain doped region and the top surface material of the second source-drain doped region, and then remove the first source-drain region subsequently. When part of the dielectric layer in the drain doped region and the second source-drain doped region can avoid over-etching the second source-drain doped region, it is beneficial to improve the performance of the device in the second region.

Further, in the process of removing the first protection layer, part of the isolation structure is also removed. After forming the second epitaxial layer and before forming the first photoresist, an oxide layer is formed on the substrate, the first protective layer, the second epitaxial layer and the second gate structure. The oxide layer is used to supplement the loss of the isolation structure, and when the first ion implantation process and the second ion implantation process are subsequently performed, the isolation structure can be prevented from being broken down and causing damage to the substrate at the bottom of the isolation structure.

Description of drawings

1 to 3 are structural schematic diagrams of each step of a method for forming a semiconductor structure;

4 to 19 are structural schematic diagrams of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

As mentioned in the background, the performance of FinFETs is still poor.

1 to 3 are structural schematic diagrams of steps in a method for forming a semiconductor structure.

Referring to FIG. 1, a substrate 100 is provided, the substrate 100 includes a PMOS region and an NMOS region, the PMOS region has a first gate structure 101 on the substrate 100, and the NMOS region has a second gate structure 102 on the substrate 100; Form a first protective film (not shown in the figure) on the substrate 100; remove the first protective film on the substrate 100 and the first gate structure 101 in the PMOS region, and the side walls of the first gate structure 101 and the NMOS A first protective layer 103 is formed on the substrate 100 ; after the first protective layer 103 is formed, a first source-drain doped region 104 is formed in the substrate 100 on both sides of the first gate structure 101 .

Referring to FIG. 2 , a second protective film (not shown in the figure) is formed on the substrate 100, the first source-drain doped region 104, the first gate structure 101 and the second gate structure 102; remove the NMOS The second protection film on the region substrate 100 and the second gate structure 102, forming a second protection layer 105 on the sidewall of the second gate structure 102 and the PMOS region substrate 100; forming the second protection layer 105 Afterwards, a second source-drain doped region 106 is formed in the substrate 100 on both sides of the second gate structure 102 .

Referring to FIG. 3 , a dielectric layer 107 is formed on the substrate 100 , the first source-drain doped region 104 , the second source-drain doped region 106 , the first gate structure 101 and the second gate structure 102 ; A source-drain doped region 104 and a part of the dielectric layer 107 on the second source-drain doped region 106 form a contact hole 108, and the bottom of the contact hole 108 exposes the first source-drain doped region 104 and the second source-drain doped region 104. The top surface of the impurity region 106.

In the above method, the first protective layer 103 is used to define the position of the first source-drain doped region 104, and the first protective layer 103 and the second protective layer 105 are used to define the position of the second source-drain doped region 106. position, the first channel is formed between the first source-drain doped region 104 at the bottom of the first gate structure 101, and the second channel is formed between the second source-drain doped region 106 at the bottom of the second gate structure 102. Therefore, the length of the first channel is smaller than the length of the second channel. The PMOS region is used to form a PMOS transistor, the NMOS region is used to form an NMOS transistor, the carriers in the first channel are holes, the carriers in the second channel are electrons, and the transfer of electrons rate is greater than the mobility of holes. Therefore, in order to increase the mobility of carriers in the PMOS region and the NMOS region at the same time, after the first source-drain doped region 104 is formed, the second source-drain doped region 106 is formed.

However, the second protective layer 105 only covers the top surface of the first source-drain doped region 104, but does not cover the top surface of the second source-drain doped region 106, so that the first source-drain doped region 104 and the second The tops of the two source-drain doped regions 106 have different thickness differences, then in the process of removing the dielectric layer 107 at the tops of the first source-drain doped regions 104 and the second source-drain doped regions 106 to form contact holes 108, when the second When the top of the source-drain doped region 106 is exposed, the top of the first source-drain doped region 104 also covers the second protection layer 105 . In order to expose the top surface of the first source-drain doped region 104 , the second protection layer 105 needs to be etched continuously. In the process of etching the second protection layer 105, the second source-drain doped region 106 is over-etched, so that the performance of the second source-drain doped region 106 is poor, which is not conducive to improving the performance of devices in the NMOS region. performance.

In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising: forming a first protection layer on the base of the first region and the first source-drain doped region; forming the first protection layer Afterwards, forming a second source-drain doped region in the substrate of the second region; after forming the second source-drain doped region, removing the first protection layer. The method can reduce damage to the top of the second source-drain doped region when the plug is subsequently formed.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 19 are structural schematic diagrams of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIG. 4 , a substrate 200 including a first region A and a second region B is provided.

The first region A is used to form a PMOS transistor, and the second region B is used to form an NMOS transistor.

In this embodiment, the base 200 includes: a substrate 201 and a fin 202 on the substrate 201 . In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.

The forming step of the substrate 200 includes: providing an initial substrate, on which a first mask layer is provided, and the first mask layer exposes a part of the top surface of the initial substrate; The layer is a mask, and the initial substrate is etched to form a substrate 201 and fins 202 on the substrate 201 .

In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the substrate 201 and the fin portion 202 is silicon. In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon-on-insulator or germanium-on-insulator. Materials for the fins include germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator.

The material of the first mask layer includes silicon nitride, and the formation process of the first mask layer includes: a chemical vapor deposition process. The first mask layer is used to form a mask for the substrate 201 and the fin portion 202 .

Using the first mask layer as a mask, the process of etching the initial substrate includes: one or both of a dry etching process and a wet etching process.

The base 200 also has an isolation structure (not shown in the figure) covering the fin 202 , the top surface of the isolation structure is lower than the top surface of the fin 202 and covers part of the sides of the fin 202 wall.

The material of the isolation structure includes: silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride, silicon nitride.

The isolation structure is used to realize electrical isolation between different semiconductor devices.

Referring to FIG. 5 , a first gate structure 203 is formed across the fin 202 in the first region A; a second gate structure 204 is formed across the fin 202 in the second region B. Referring to FIG.

In this embodiment, the first gate structure 203 and the second gate structure 204 are formed simultaneously, and the forming steps of the first gate structure 203 and the second gate structure 204 include: on the substrate 200 Forming a gate dielectric film; forming a gate film on the gate dielectric film, having a second mask layer on the gate film, and the second mask layer exposes a part of the gate film; using the second mask The film layer is a mask, the gate film and the gate dielectric film are etched, the first gate structure 203 is formed on the substrate 200 in the first region A, and the second gate structure 203 is formed on the substrate 200 in the second region B. pole structure 204 .

The material of the gate dielectric film includes silicon oxide, and the formation process of the gate dielectric film includes: chemical vapor deposition process.

The material of the gate film includes silicon, and the forming process of the gate film includes: a chemical vapor deposition process.

Referring to FIG. 6 , a second protection film 205 is formed on the substrate 200 , sidewalls and top surfaces of the first gate structure 203 , and sidewalls and top surfaces of the second gate structure 204 .

The material of the second protection film 205 includes: silicon nitride, and the formation process of the second protection film 205 includes: an atomic layer deposition process.

The second protection film 205 is used for subsequent formation of a second protection layer.

Please refer to FIG. 7 , remove the second protective film 205 (as shown in FIG. 6 ) on the substrate 200 and the first gate structure 203 in the first region A, and the sidewall and the second region of the first gate structure 203 The sidewalls and top surfaces of the B substrate 200 and the second gate structure 204 form a second protection layer 206 .

The process of removing the second protection film 205 on the substrate 200 and the first gate structure 203 in the first region A includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, during the process of removing the first protective film 205 on the substrate 200 and the first gate structure 203 in the first region A, part of the isolation structure is removed.

The material of the second protection layer 206 includes silicon nitride.

The second protection layer 206 located on the sidewall of the first gate structure 203 is used to define the position where the first source-drain doped region will be formed later.

The second protective layer 206 located on the sidewall of the second gate structure 204 and the subsequently formed first protective layer serve as positions for subsequent formation of the second source-drain doped region.

Please refer to FIG. 8 , a first source and drain opening (not shown in the figure) is formed in the substrate 200 on both sides of the first gate structure 203 and the first protection layer 206; The first epitaxial layer 207 .

In the process of forming the first epitaxial layer 207 , the second protective layer 206 is used to protect the substrate 200 in the second region B and the sidewall and top surface of the second gate structure 204 .

The forming process of the first source-drain opening includes: one or a combination of a dry etching process and a wet etching process.

The material of the first epitaxial layer 207 is related to the type of transistor.

In this embodiment, the first region A is used to form a PMOS transistor, therefore, the material of the first epitaxial layer 207 includes: silicon germanium or silicon.

In other embodiments, the first region is used to form an NMOS transistor, therefore, the material of the first epitaxial layer includes: silicon carbide or silicon.

The forming process of the first epitaxial layer 207 includes: an epitaxial growth process.

Referring to FIG. 9 , a first protection film 208 is formed on the substrate 200 , the first epitaxial layer 207 , the first gate structure 203 and the first protection layer 206 .

The material of the first protective film 208 includes: silicon nitride, and the formation process of the first protective film 208 includes: an atomic layer deposition process.

The first protection film 208 is used for subsequent formation of a first protection layer.

The thickness of the first protective film 208 is 3 nanometers to 5 nanometers. The first protective film 208 is used to subsequently form a first protective layer, and the thickness of the first protective film 208 determines the thickness of the subsequently formed first protective layer.

Please refer to FIG. 10 , remove the first protection film 208 on the substrate 200 and the second gate structure 204 in the second region B (as shown in FIG. , the first epitaxial layer 207 , and the sidewalls and top surfaces of the first gate structure 203 form a first protection layer 209 .

The process of removing the second protective film 208 on the substrate 200 and the second gate structure 204 in the second region B includes: one or a combination of a dry etching process and a wet etching process.

During the process of removing the first protection film 208 on the substrate 200 and the second gate structure 204 in the second region B, part of the isolation structure is removed.

The second protection layer 206 and the first protection layer 209 on the sidewall of the second gate structure 204 are used to subsequently define the position of the second source-drain doped region. The first protective layer 209 in the first region A is used to protect the substrate 200 , the surface of the first epitaxial layer 207 , and the sidewall and top surface of the first gate structure 203 in the first region A.

The thickness of the first protective layer 209 is 3 nanometers to 5 nanometers.

Referring to FIG. 11 , a second epitaxial layer 210 is formed in the substrate 200 on both sides of the second gate structure 204 , the second passivation layer 206 and the first passivation layer 209 .

During the process of forming the second epitaxial layer 210 , the first protective layer 209 is used to protect the device in the first region A.

The material of the second epitaxial layer 210 is related to the type of transistor.

In this embodiment, the second region A is used to form an NMOS transistor, therefore, the material of the second epitaxial layer 210 includes: silicon carbide or silicon.

In other embodiments, the second region is used to form a PMOS transistor, therefore, the material of the second epitaxial layer includes: silicon germanium or silicon.

The formation process of the second epitaxial layer 210 includes: an epitaxial growth process.

Referring to FIG. 12 , an oxide film 211 is formed on the substrate 200 , the isolation structure, the second epitaxial layer 210 , the first protective layer 209 and the second gate structure 204 .

The material of the oxide film 211 includes: silicon oxide, and the formation process of the oxide film 211 includes: a fluid chemical vapor deposition process.

The oxide film 211 is used to compensate the loss of the isolation structure during the process of removing the second protective film 205 and the first protective film 208, so as to prevent the isolation structure from being too thin when the first ion implantation process and the second ion implantation process are subsequently performed. Damage to the substrate 200 is beneficial to improve the performance of the semiconductor device.

The thickness of the oxide film 211 is: 20 Ř40 Å.

The oxide film 211 is used for subsequent formation of an oxide layer.

Please refer to FIG. 13 , a first photoresist 212 is formed on the substrate 200 in the second region B; using the first photoresist 212 as a mask, the oxide film 211 in the first region A is etched until the first region A is exposed. The first protection layer 209 on the substrate 200 in the first region A, and the oxide layer 213 is formed on the substrate 2000 in the second region B.

The first photoresist 212 is used to protect the substrate 200 , the second epitaxial layer 210 and the second gate structure 204 in the second region B.

Using the first photoresist 212 as a mask, the process of etching the oxide film 211 in the first region A includes: one or a combination of a dry etching process and a wet etching process.

Removing the oxide film 211 in the first region A is beneficial to expose the first protection layer 209 on the first region A, and further facilitates subsequent removal of the first protection layer 209 on the first region A.

The material of the oxide layer 213 includes silicon oxide. The thickness of the oxide layer 213 is: 20 Ř40 Å.

Please refer to FIG. 14 , after the oxide layer 213 is formed, a first ion implantation process is performed on the first epitaxial layer 207 (see FIG. 13 ) using the first photoresist 212 as a mask to form a first source-drain doped region. 214.

The first ion implantation process includes first dopant ions, and the conductivity type of the first dopant ions is related to the conductivity type of the transistor.

In this embodiment, the first region A is used to form a PMOS transistor, therefore, the first dopant ions are P-type ions, such as boron ions or indium ions.

In other embodiments, the first region is used to form an NMOS transistor, therefore, the first dopant ions are N-type ions, such as phosphorous ions or arsenic ions.

In the process of forming the first source-drain doped region 214, the first photoresist 2112 is used to protect the second epitaxial layer 210 from being implanted with the first ions, so that the first doping ions do not affect the second region B device performance.

Please refer to FIG. 15, after forming the first source-drain doped region 214, remove the first photoresist 212 (as shown in FIG. 14); after removing the first photoresist 212, in the first region A second photoresist 215 is formed on the substrate 200 ; using the second photoresist 215 as a mask, a second ion implantation process is performed on the second epitaxial layer 210 to form a second source-drain doped region 216 .

The process of removing the first photoresist 212 includes: an ashing process.

The second photoresist 215 is used to protect the substrate 200 in the first region A, the first source-drain doped region 214 and the first gate structure 203 .

The second ion implantation process includes second doping ions, and the conductivity type of the second doping ions is related to the conductivity type of the transistor.

In this embodiment, the second region A is used to form an NMOS transistor, therefore, the second dopant ions are N-type ions, such as phosphorus ions or arsenic ions.

In other embodiments, the second region is used to form a PMOS transistor, therefore, the second dopant ions are P-type ions, such as boron ions or indium ions.

The size of the second source-drain doped region along the direction perpendicular to the surface of the substrate is: 100nm-120nm.

Please refer to FIG. 16, after forming the second source-drain doped region 216, remove the second photoresist 215; after removing the second photoresist 215, remove the first region A substrate 200, the first source-drain doped region 214 and the first protection layer 209 on the first gate structure 203 .

The process of removing the photoresist 215 includes: an ashing process.

The material of the first protection layer 209 is different from the material of the first source-drain doped region 214, and the first protection layer 209 and the first source-drain doped region 214 have different etching selectivity ratios. Therefore, the removal of the first When the first protective layer 209 is formed on the source-drain doped region 214 , the damage to the top surface of the first source-drain doped region 214 can be reduced.

The process of removing the first protective layer 209 on the substrate 200 in the first region A, the first source-drain doped region 214 and the first gate structure 203 includes: a wet etching process; when the material of the first protective layer is When silicon nitride is used, the parameters of the wet etching process include: the etchant includes phosphoric acid.

When the first protective layer 209 on the top surface of the first source-drain doped region 214 is removed, the oxide layer 213 located on the top of the second source-drain doped region 216 is also removed. At this time, the first source-drain doped region 214 and the top of the second source-drain doped region 216 are not free of material layer coverage, then the difference in thickness of the subsequent material layer located on the first source-drain doped region 214 and the second source-drain doped region 216 is relatively small. Then, when removing part of the dielectric layer of the first source-drain doped region and the second source-drain doped region, over-etching the second source-drain doped region can be avoided, which is beneficial to improve the density of the second source-drain doped region. performance.

Please refer to FIG. 17 , after removing the first protective layer 209 on the substrate 200 , the first source-drain doped region 214 and the first gate structure 203 in the first region A, in the substrate 200 , the first source-drain doped region 214, the second source-drain doped region 216, the sidewall and top surface of the first gate structure 203, and the sidewall and top surface of the second gate structure 204 form a stop layer 217; dielectric layer 218 .

The material of the stop layer 217 includes: silicon nitride, and the formation process of the stop layer 217 includes: a chemical vapor deposition process.

The stop layer 217 is used as a stop layer when openings are subsequently formed.

The material of the dielectric layer 218 includes: silicon oxide, and the formation process of the dielectric layer 218 includes: a fluid chemical vapor deposition process.

Please refer to FIG. 18 , remove part of the dielectric layer 218 to form an opening (not shown in the figure), the opening exposes the stop layer 217 on the top of the first source-drain doped region 214 and the second source-drain doped region 216; The stop layer 217 at the bottom of the opening forms a contact hole 219 .

The process for forming the opening includes: one or a combination of a dry etching process and a wet etching process.

The process of removing the bottom stop layer 217 of the opening includes: one or a combination of a dry etching process and a wet etching process.

The difference in thickness between the stopper layer 217 and the dielectric layer 218 at the top of the first source-drain doped region 214 and the second source-drain doped region 216 is small, so in the process of forming the contact hole 219, the first source-drain doped The top surfaces of the impurity region 214 and the second source-drain doped region 216 are less damaged, and the performance of the device in the first region A and the second region B is better.

Referring to FIG. 19 , a plug 220 is formed in the contact hole 219 (shown in FIG. 18 ).

The forming step of the plug 220 includes: forming a plug material layer on the contact hole 219 and the dielectric layer 218; planarizing the plug material layer until the top surface of the dielectric layer 218 is exposed, and the contact A plug 220 is formed in the hole 219 .

The material of the plug material layer is metal.

In this embodiment, the material of the plug material layer is tungsten. In other embodiments, the material of the plug material layer includes: aluminum, copper, titanium, silver, gold, lead or nickel.

The process of planarizing the plug material layer includes: a chemical mechanical polishing process.

Correspondingly, the present invention also provides a semiconductor structure formed by the above method, please continue to refer to FIG. 18 , including:

A substrate 200, the substrate 200 includes a first region A and a second region B, the first region A has a first source-drain doped region 214 in the substrate 200;

A second source-drain doped region 216 located in the second region B of the substrate 200;

The dielectric layer 218 on the substrate 200 has a contact hole 219 exposing top surfaces of the first source-drain doped region 214 and the second source-drain doped region 216 in the dielectric layer 218 .

The size of the second source-drain doped region 216 along the direction of connecting the first source-drain doped region 214 and the second source-drain doped region 216 is: 100 nanometers to 120 nanometers. The semiconductor structure further includes: plugs in the contact holes 219.

The first region A is used for PMOS transistors, and the second region B is used for forming NMOS transistors.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

1. a kind of forming method of semiconductor structure characterized by comprising

Substrate is provided, the substrate includes the firstth area and the secondth area, has the first source and drain doping area in firstth area substrate；

The first protective layer is formed in firstth area substrate and the first source and drain doping area；

It is formed after first protective layer, forms the second source and drain doping area in the substrate in secondth area；

It is formed after second source and drain doping area, removes the first protective layer；

After removing the first protective layer, dielectric layer is formed in the substrate, the first source and drain doping area and the second source and drain doping area；

The part dielectric layer is removed, until the top surface in the first source and drain doping area and the second source and drain doping area is exposed, Contact hole is formed in the dielectric layer.

2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of first protective layer Are as follows: 3 nanometers~5 nanometers.

3. the forming method of semiconductor structure as described in claim 1, which is characterized in that second source and drain doping area is along vertical Directly in the size in the first source and drain doping area and the second source and drain doping area line direction are as follows: 100 nanometers~120 nanometers.

4. the forming method of semiconductor structure as described in claim 1, which is characterized in that also have in firstth area substrate First grid structure, the substrate of first grid structure two sides is interior to have first source and drain doping area；Secondth area base Also there is second grid structure on bottom, there is second source and drain doping area in the substrate of second grid structure two sides.

5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that first protective layer also covers The side wall of two gate structures；The forming step of first protective layer includes: in the substrate and the first source and drain doping area, The side wall and top surface of one gate structure and the side wall and top surface of second grid structure form the first protective film；It goes Except the first protective film of second area's substrate and second grid structural top surface, first protective layer is formed.

6. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that first source and drain doping area and The forming step in two source and drain doping areas includes: that the first epitaxial layer is formed in the substrate of first grid structure two sides；Institute It states on first area's substrate and the first epitaxial layer, the side of the side wall of first grid structure and top surface and second grid structure Wall forms the first protective layer；It is formed after first protective layer, forms in the substrate of second grid structure two sides Two epitaxial layers；In secondth area substrate and the second epitaxial layer and the side wall and top surface of second grid structure are formed First photoresist；Using first photoresist as exposure mask, using the first ion implantation technology, mixed in first epitaxial layer First Doped ions form the first source and drain doping area；It is formed after first source and drain doping area, removes the first photoresist；It goes After first photoresist, in firstth area substrate and the first source and drain doping area and the side of first grid structure Wall and top surface form the second photoresist；Using second photoresist as exposure mask, using the second ion implantation technology, described The second Doped ions are mixed in second epitaxial layer, form the second source and drain doping area.

7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that formed second epitaxial layer it Afterwards, it is formed before the first photoresist, the forming method further include: in the substrate, the first protective layer, the second epitaxial layer and the Oxide layer is formed on two gate structures.

8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that it is formed after the first photoresist, In first epitaxial layer before the first Doped ions of incorporation, the forming method further include: first area's oxide layer of removal, exposure First protective layer out.

9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the material of the oxide layer includes: Silica；The thickness of the oxide layer are as follows: 20 angstroms~40 angstroms.

10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first protective layer It include: silicon nitride.

11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that removal first protective layer Technique includes: wet-etching technology；When the material of first protective layer is silicon nitride, the parameter of the wet-etching technology It include: etching agent include phosphoric acid.

12. the forming method of semiconductor structure as described in claim 1, which is characterized in that also have isolation in the substrate Structure；The material of the isolation structure includes: silica.

13. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed after the contact hole, institute State forming method further include: form plug in the contact hole.

14. the forming method of semiconductor structure as described in claim 1, which is characterized in that firstth area is brilliant for PMOS Body pipe, secondth area are used to form NMOS transistor.

15. a kind of semiconductor structure characterized by comprising

Substrate, the substrate include the firstth area and the secondth area, have the first source and drain doping area in firstth area substrate；

Positioned at intrabasement second source and drain doping area, the secondth area；

Dielectric layer in substrate has in the dielectric layer and exposes the first source and drain doping area and the second source and drain doping area top The contact hole on portion surface.

16. semiconductor structure as claimed in claim 15, which is characterized in that mixed along the first source and drain in second source and drain doping area Size in miscellaneous area and the second source and drain doping area line direction are as follows: 100 nanometers~120 nanometers.

17. semiconductor structure as claimed in claim 15, which is characterized in that the semiconductor structure further include:

Plug in the contact hole.

18. semiconductor structure as claimed in claim 15, which is characterized in that firstth area is used for PMOS transistor, described Secondth area is used to form NMOS transistor.