CN110085583B - Semiconductor device and operating method - Google Patents

Abstract

The present disclosure relates to a semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device may be arranged for bi-directional operation. The semiconductor device arrangement may comprise: a field effect transistor including a first input terminal and a second input terminal; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first and second terminals are configured and arranged to be connected to respective signal lines.

Description

Semiconductor device and operating method

Technical Field

The present disclosure relates to semiconductor devices and operating methods. Specifically, the present disclosure relates to bidirectional devices and associated operating methods. More specifically, the present disclosure relates to bidirectional ESD protection devices.

Background technique

Electrostatic discharge (ESD) protection semiconductor devices can generally be classified as unidirectional or bidirectional. Unidirectional ESD protection devices can be suitable for protecting circuits where ESD events are generally above or below a predetermined reference voltage. Therefore, unidirectional devices are characterized by an asymmetric IV (current-voltage) characteristic; for one polarity, the breakdown voltage is defined by the forward biased pn junction, and for the other opposite polarity, the breakdown voltage is much larger. Bidirectional ESD protection devices can be suitable for protecting circuits where ESD events are above and below a predetermined reference voltage. Therefore, bidirectional devices are characterized by a symmetrical IV (current-voltage) characteristic; for both polarities, the breakdown voltage is much greater than the forward voltage.

For some applications, the breakdown voltage of the bidirectional device may be less than 6 V, for example in the range of 2 V to 4 V. At the same time, the leakage current should be small; this means that the leakage current is less than 1 μA, preferably less than 1 nA.

Bidirectional ESD protection can be provided by two Zener diodes connected back to back (i.e., anode to anode or cathode to cathode). However, with such an arrangement, it is not possible to achieve a breakdown voltage much below 6 volts and at the same time achieve low leakage current, since Zener tunneling is the dominant breakdown mechanism.

Metal oxide semiconductor (MOS) diodes are known to have low switching voltage and low leakage current, thus making them suitable for ESD protection devices. However, since the gate of a MOS transistor must be connected to one of two terminals (drain or source), bidirectional functionality is not possible.

Summary of the invention

According to an embodiment, a semiconductor device arrangement is provided for bidirectional operation, the semiconductor device arrangement comprising: a field effect transistor comprising a first input terminal and a second input terminal; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to corresponding signal lines.

Optionally, the anode of the first diode is connected to the first terminal and the cathode of the first diode is connected to the control terminal, and the anode of the second diode is connected to the first terminal and the cathode of the second diode is connected to the control terminal.

Optionally, the cathode of the first diode is connected to the first terminal and the anode of the first diode is connected to the control terminal, and the cathode of the second diode is connected to the second terminal and the anode of the second diode is connected to the control terminal.

The field effect transistor may also include a semiconductor substrate of a first conductivity type; a first terminal region and a second terminal region separated by the semiconductor region are formed of a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; and a main terminal is connected to the semiconductor substrate.

Optionally, the semiconductor substrate may include: a first body diode arranged between the body terminal and the first terminal region; and a second body diode arranged between the body terminal and the second terminal region. The semiconductor substrate may include: a first body diode arranged between the body terminal and the first terminal region; and a second body diode arranged between the body terminal and the second terminal region.

An electrostatic discharge protection arrangement may include the semiconductor device arrangement according to an embodiment.

The integrated circuit may include a first domain and a second domain. According to an embodiment, the first domain may be connected to the second domain through a semiconductor device arrangement.

According to an embodiment, a method for operating a semiconductor device arrangement is provided, comprising: connecting the first terminal of the device to a first signal line carrying a first bias voltage, and connecting the second terminal to a second signal line carrying a second bias voltage; forward biasing a first diode connected between the first terminal and a control terminal, and reverse biasing a second diode connected between the second terminal and the control terminal; wherein the voltage on the control terminal is substantially equal to the voltage on the first terminal.

Optionally, the voltage on the control terminal may be equal to the bias voltage minus the forward voltage of the first diode. The first terminal, the second terminal, and the control terminal may be terminals of a field effect transistor. The field effect transistor may also include a first body diode and a second body diode, wherein the first body diode is in a blocking mode and the second body diode is in a forward mode, so that the voltage of the other terminal region of the field effect transistor is substantially equal to the voltage on the second terminal. Optionally, the voltage on the other terminal may be higher than the voltage on the second terminal by a voltage equal to the forward voltage of the second body diode.

According to an embodiment, a method for manufacturing a semiconductor device arrangement for bidirectional operation is also provided, the method comprising: forming a field effect transistor, the field effect transistor comprising a first input terminal, a second input terminal, and a control terminal; arranging a first diode to be connected between the first terminal and the control terminal; arranging a second diode to be connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to corresponding signal lines.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings and the following description, like reference numerals refer to like features.

The present invention is further described hereinafter by way of example only with reference to the accompanying drawings, in which:

FIG. 1a is a schematic diagram of a semiconductor device for bidirectional operation according to an embodiment;

FIG. 1 b is a schematic diagram of a semiconductor device for bidirectional operation according to an embodiment;

FIG. 2 shows an equivalent circuit of a semiconductor device for bidirectional operation according to the embodiment of FIG. 1 a ;

FIG3 shows a graph of potential difference V _gate-body versus bias voltage V _bias ;

FIG. 4 shows typical current-voltage (I-V) characteristics of a semiconductor device according to an embodiment;

FIG5 shows an equivalent circuit to FIG2 including an arrangement of anti-parallel diodes;

FIG. 6 shows an application of a semiconductor device according to an embodiment for ESD protection in an integrated circuit arrangement; and

FIG. 7 shows a series arrangement of the semiconductor components according to FIG. 2 .

Detailed ways

FIG. 1 a shows a semiconductor device 100 for bidirectional ESD protection according to an embodiment. The semiconductor device 100 includes a semiconductor substrate 102 formed of a first conductivity type. A first terminal region 104 and a second terminal region 106 are formed in the semiconductor substrate 102 such that the first terminal region 104 is separated from the second terminal region 106 by a partition of the semiconductor substrate 102. The partition of the semiconductor substrate 102 creates a channel (or reverse) region 108 of the semiconductor device 100 during operation.

The control terminal 110 is arranged above a dividing portion of the semiconductor substrate 102 where the channel (or inversion) region 108 is formed. A first terminal 112 is formed on the first terminal region 104, and a second terminal 114 is formed on the second terminal region 106. An additional terminal region 116 may be formed on the semiconductor substrate 102, opposite to the control terminal 110, the first terminal region 104, and the second terminal region 106.

The control terminal of the MOS structure is formed by forming an oxide 118 (e.g., _SiO2 ) on the semiconductor substrate 102 over a portion of the substrate that creates a channel (or inversion) region 108 during operation of the semiconductor device. A contact layer 120 formed of a metal layer (or alternatively a polysilicon layer) is then formed on the oxide to complete the control terminal 110.

The first terminal region 104 and the second terminal region 106 may be formed by implantation and/or diffusion into the semiconductor substrate 102. Appropriate metal contacts are then formed on the first terminal region 104 and the second terminal region 106 to form the first terminal 112 and the second terminal 114, respectively.

In the context of the present disclosure, the semiconductor substrate 102 may also be referred to as the body of the semiconductor device 100, and the additional terminal 116 may be referred to as the body terminal. The arrangement of the first terminal area 104 and the second terminal area 106 having the opposite conductivity type to the semiconductor substrate 102 (or the body) forms a so-called body diode between the semiconductor substrate 102 and the corresponding first terminal area and the second terminal area. Specifically, a first body diode 122 is created between the first terminal area 104 of the first conductivity type and the semiconductor substrate 102 of the second conductivity type. A second body diode 124 is created between the first terminal area 106 of the first conductivity type and the semiconductor substrate of the second conductivity type. FIG. 1a shows the first body diode 122 and the second body diode 124 in an embodiment in which the semiconductor substrate 102 is p-doped. In this case, the anodes of the first body diode 122 and the second body diode 124 are both formed by the semiconductor substrate 102. Similarly, FIG. 1b shows an embodiment in which the semiconductor substrate 102 is n-doped. Those skilled in the art will understand that the cathodes of the first body diode 122 and the second body diode 124 are therefore formed by the n-type semiconductor substrate 102. The arrangements of Figures 1a and 1b are effectively MOS transistors.

In addition to the first body diode 122 and the second body diode 124, further control terminal diodes 126, 128 may be connected between the control terminal 110 and the first terminal 112, the second terminal 114. The first control terminal diode 126 is connected between the first terminal 112 and the control terminal 110, and the second control terminal diode 128 is connected between the second terminal 114 and the control terminal 110. The first control terminal diode 126 and the second control terminal diode 128 may be integrated on the substrate, or they may be externally connected between the first terminal 112 and the control terminal 110, and the second terminal 114 and the control terminal 110, respectively. By the arrangement of the first body diode 122, the second body diode 124, the first control terminal diode 126, and the second control terminal diode 128, the structure of the device arrangement is therefore referred to as symmetrical. FIG. 1a shows the first control terminal diode 126 and the second control terminal diode 128 in the case where the semiconductor substrate is p-doped. In this case, the cathodes of the first control terminal diode 126 and the second control terminal diode 128 are connected to the control terminal 110. As shown in FIG. 1 b , it will be clear to those skilled in the art that when the semiconductor substrate 102 is n-doped, the anodes of the first control terminal diode 126 and the second control terminal diode 128 are both connected to the control terminal 110 .

FIG. 2 shows an equivalent circuit according to the arrangement of FIG. 1 a, and the same reference numerals correspond to the same features. In FIG. 2 , a semiconductor device 100 for bidirectional operation is connected across two signal lines 202, 204 having different potentials. The first terminal 112 is connected to the first signal line 204 and the second terminal 114 is connected to the second signal line 202. For example, the first signal line 204 can be a ground line, and the second signal line 202 can be a bias voltage line for another circuit (not shown) to be protected. The voltage of the second signal line 202 can be a positive voltage or a negative voltage relative to the first signal line 204. Due to the inherent symmetry of the device 100, the operation of the device is similar regardless of the voltage polarity on the first signal line 202 or the second signal line 204.

The voltage across the signal line 202 and the signal line 204 may be an ESD event or a bias voltage. Assuming that the voltage on the signal line 202 (i.e., the voltage on the second terminal 114) is positive, the second control terminal diode 128 will be forward biased and thus turned on. Therefore, the first control terminal diode 126 will be reverse biased and therefore in blocking mode. Ideally, assuming that there is no voltage drop across the second control terminal diode 128, the voltage on the control terminal 110 will be equal to or substantially equal to the bias voltage on the second terminal 114. However, in practice, the reverse biased first control terminal diode 126 may show a leakage current. This leakage current may flow through the forward biased second control terminal diode 128, causing a voltage drop across the transistor according to the current level. Therefore, in practice, the voltage on the control terminal 110 will be less than the bias voltage by an amount equal to the forward voltage of the second control terminal diode 128. Since the leakage current of the reverse biased first control terminal diode 126 will be small (eg, less than 100 pA), the forward voltage drop of the diode 128 will be in the range of 300 mV to 400 mV.

Furthermore, when the bias voltage is positive, the second body diode 124 will be in blocking mode and thus the first body diode 122 will be forward biased and thus conducting, and in an ideal case, the voltage across the further terminal area 116 will be substantially equal to the ground potential. However, in practice, due to the forward voltage of the forward biased first body diode 122, the voltage across the further terminal area 116 will be higher than the ground potential by an amount equal to the forward voltage of the first body diode 122. As previously mentioned, since the leakage current of the reverse biased second body diode 124 will be small (e.g., less than 100 pA), the forward voltage drop of the diode 122 will be in the range of 300 mV to 400 mV.

In this way, the voltage on control terminal 110 will be higher than the voltage on control terminal 116. When the voltage difference between terminal 110 and terminal 116 exceeds the threshold voltage + _Vth , a channel (or inversion) region 108 is created connecting the two diffusion regions 104 and 106 so that current can flow from terminal 114 to terminal 112.

In the case where the voltage on the signal line 202 (i.e., the voltage on the second terminal 114) is negative compared to the voltage on the first terminal 112 (which, for simplicity, is connected to ground in this example), the second control terminal diode 128 will be reverse biased and thus in blocking mode. As a result, the first control terminal diode 126 will be forward biased and thus conducting. In an ideal situation, i.e., assuming that there is no voltage drop across the first control terminal diode 126, the voltage on the control terminal 110 will be the same as the ground voltage. In practice, however, due to the forward voltage of the forward biased first control terminal diode 126, the voltage on the control terminal 110 will be lower than the ground voltage by an amount equal to the forward voltage of the first control terminal diode 126.

Furthermore, when the bias voltage is negative, the second body diode 122 will be in blocking mode and therefore the first body diode 124 will be forward biased and therefore turned on, and the voltage on the body terminal 116 will ideally be equal to the negative bias voltage, but in practice will be equal to the bias voltage plus the forward voltage of the first body diode 124.

In this case, the voltage at control terminal 110 will be higher than the voltage at control terminal 116. When the voltage difference between control terminal 110 and terminal 116 exceeds a threshold voltage + _Vth , a channel (or inversion) region 108 is created connecting the two diffusion regions 104 and 106 so that current can flow from terminal 112 to terminal 114.

In summary, the operation of the device can be described as follows. When the bias voltage or ESD event is positive:

- as described above, the potential at the control terminal 110 will be the bias voltage minus the forward voltage of the second control terminal diode; and

The potential at the further terminal region 116 will be ground voltage plus the forward voltage of the first body diode 122 .

When the bias voltage or ESD event is negative:

- the potential at the control terminal 110 will be ground minus the forward voltage of the first control terminal diode; and

The potential on the further terminal region 116 will be the bias voltage plus the forward voltage of the second body diode 124 .

In both cases, the potential on the gate terminal 110 will be higher than the potential on the body terminal 116 .

FIG3 shows a graph of the gate-body potential difference V _GB between the control terminal 110 and the body terminal 116 on the vertical axis and the bias voltage V _bias between the first terminal 114 and the second terminal 112 on the horizontal axis. In both the positive and negative cases described above, the relationship between the bias voltage V _bias and the potential difference V _GB between the control terminal 110 (or the gate of the semiconductor device) and the body terminal 116 is positive. In addition, as the bias voltage V _bias increases, the potential difference V _GB increases linearly. As described above, in an ideal case, the potential difference V _GB follows the bias voltage V _bias . However, in practice, the potential difference V _GB will be smaller than the bias voltage V _bias by the forward voltage of the related forward conducting diode. In both cases where the bias voltage V _bias is positive and negative, the absolute potential difference (i.e., the magnitude, not the polarity) between the control terminal 110 and the body terminal 116 is therefore always positive. In both cases, when the potential difference between the line 202 and the line 204 is greater than the threshold voltage of the transistor, the device will switch to the conduction mode.

4 shows a typical current-voltage (IV) characteristic of the semiconductor device 100 according to an embodiment, wherein the vertical axis I _LR corresponds to the current flowing from the line 202 to the line 204 (in other words, from the second terminal 114 to the first terminal 112), and the horizontal axis corresponds to the bias voltage V _bias , i.e., the potential difference between the line 202 and the line 204 (or from the second terminal 114 to the first terminal 112). In the case where the positive bias voltage V _bias is greater than the positive threshold voltage +V _th (the threshold voltage of the MOS transistor), the semiconductor device operates in the positive forward conduction mode region 402. Likewise, in the case where the value of the negative bias voltage V _bias is greater than the threshold voltage V _th , the semiconductor device operates in the negative conduction mode region 404.

Furthermore, in the case where the value of the positive or negative bias voltage V _bias is less than the threshold voltage V _th , the device will be in the blocking mode 406 .

Therefore, according to an embodiment, the semiconductor device 100 may be regarded as a bidirectional MOS diode capable of symmetrical operation.

The threshold voltage or V _th may be selected by appropriate selection of process settings such as, for example, doping levels of the substrate and/or diffusion layers in the bulk below the control terminal 110 .

Applications of the semiconductor device 100 according to embodiments may include on-board, ESD or overload protection, for example, of a printed circuit board (PCB), wherein the semiconductor device 100 is arranged to protect signal lines or contact pads on the PCB from electrical overload.

Alternatively, the semiconductor device 100 may be placed across two signal lines, as shown in FIG. 2 , so as to limit the voltage difference between the line 202 and the line 204 .

Semiconductor device 100 can also be placed between a signal line and a voltage reference line (e.g., a ground line). As shown in FIG2 , line 202 can be a signal line and line 204 can be a ground line. For both positive and negative polarity on line 202, device 100 will limit the voltage difference between the signal line and the ground line.

In applications where low parasitic capacitance is required, such as in USB 2.0 or HDMI serial interfaces, the semiconductor device can incorporate a low capacitance steering diode. In FIG5 , a pair 300 of two anti-parallel diodes 301 and 302 are placed in series with the semiconductor device 100. Transistors 301 and 302 can be chosen to be very small, because then the current will only flow through these diodes in the forward bias direction and the dissipated energy in these diodes will be small. Therefore, the capacitance of the diodes will be small; therefore, the capacitance of the series-connected diode pair 300 and semiconductor device 100 will also be small.

Diodes 301 and 302 may be added externally to semiconductor device 100 , or they may be integrated on the same semiconductor crystal as device 100 ; or may be included in the same package as device 100 .

Another application of the device according to the present embodiment can be in the field of integrated circuits. As shown in Figure 6, the integrated circuit may include two or more power domains Vdd ₁ and Vdd ₂ , which are associated with the core 1 and core 2 of the integrated circuit. The grounding gnd ₁ and gnd ₂ of these domains are often connected by a pair of anti-parallel diodes 300 to provide an ESD current path between core 1 and core 2. There is usually no direct ESD current path between the power supply voltage line Vdd ₁ and Vdd _2. Assuming that the threshold voltage of device 100 is greater than the difference between the two power supply voltages, and during normal operation, the device 100 according to the embodiment will be in a non-conducting mode, then the device 100 according to the embodiment can be placed between power supply lines Vdd ₁ and Vdd _2. However, during an ESD event, the device according to the embodiment will be in a conducting mode, so an additional ESD current path is provided between two different voltage domains.

In the context of the present application, it will be understood by those skilled in the art that the term first conductivity type may refer to a p-type material or an n-type material, and that the second conductivity type will be the opposite type of the first conductivity type. For example, where the first conductivity type is p-type, the second conductivity type will be n-type, and vice versa. Thus, the semiconductor device 100 may be a p-channel (or PMOS) device, or alternatively an n-channel (NMOS) device.

Those skilled in the art will also appreciate that the device 100 according to the embodiment can be combined with other devices. For example, as shown in FIG. 7 , the device 100 is connected in series with another such device, thereby doubling the threshold voltage. The device 100 can also be used in a trigger structure, which is used to trigger another device such as a silicon controlled rectifier (SCR).

Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not just as set out in the claims.

The scope of the present disclosure includes any novel feature or combination of features disclosed therein, whether explicitly or implicitly or in any general manner, whether or not it relates to the claimed invention or mitigates any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from the respective independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.

Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

The term "comprising" does not exclude other elements or steps and the terms "a" or "an" do not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims (10)

1. A semiconductor device arrangement for bidirectional operation, the semiconductor device arrangement comprising: A field effect transistor comprising: a semiconductor substrate body of a first conductivity type; a first terminal region and a second terminal region, each of the first terminal region and the second terminal region being formed of a second conductivity type opposite to the first conductivity type, the first terminal region being separated from the second terminal region by a dividing portion of the semiconductor substrate body; and a first terminal and a second terminal, wherein the first terminal and the second terminal are input terminals; a control terminal, the control terminal being arranged above the dividing portion; a main body terminal, the main body terminal being arranged opposite to the control terminal and being located on the semiconductor substrate main body; a first control diode connected and arranged between the first terminal and the control terminal; and a second control diode connected and arranged between the second terminal and the control terminal; a first body diode symmetrically arranged in the semiconductor substrate body and opposite to the first control diode between the body terminal and the first terminal region; and a second body diode, the second body diode being symmetrically arranged in the semiconductor substrate body and opposite to the second control diode between the body terminal and the second terminal region; The first terminal and the second terminal are connected to the corresponding first signal line and the second signal line. 2. The semiconductor device arrangement of claim 1 , wherein the first control diode has an anode connected to the first terminal and a cathode connected to the control terminal, and the second control diode has an anode connected to the second terminal and a cathode connected to the control terminal. 3. The semiconductor device arrangement of claim 1 , wherein the first control diode has a cathode connected to the first terminal and an anode of the first control diode is connected to the control terminal, and the second control diode has a cathode connected to the second terminal and an anode of the second control diode is connected to the control terminal. 4. An electrostatic discharge protection arrangement comprising the semiconductor device arrangement of claim 1. 5 . An integrated circuit comprising a first domain and a second domain; wherein the first domain is connected to the second domain through a semiconductor device arrangement according to claim 1 . 6. A method of operating a semiconductor device arrangement, comprising: connecting a first terminal of the semiconductor device arrangement to a first signal line carrying a first bias voltage and a second terminal to a second signal line carrying a second bias voltage; and forward biasing a first control diode connected and arranged between the first terminal and a control terminal, and reverse biasing a second control diode connected and arranged between the second terminal and the control terminal; wherein the voltage on the control terminal is equal to the voltage on the first terminal, and The semiconductor device arrangement further comprises a first main body diode symmetrically arranged in the semiconductor substrate body of the semiconductor device arrangement and opposite to the first control diode, a second main body diode symmetrically arranged in the semiconductor substrate body of the semiconductor device arrangement and opposite to the second control diode, and an additional terminal region having an additional terminal, wherein the first main body diode is in a blocking mode and the second main body diode is in a forward mode, so that the voltage of the additional terminal region of the field effect transistor is equal to the voltage on the second terminal. 7 . The method of operating a semiconductor device arrangement according to claim 6 , wherein the voltage on the control terminal is equal to the first bias voltage minus a forward voltage of the first control diode. 8 . The method of operating a semiconductor device arrangement according to claim 6 , wherein the first terminal, the second terminal, and the control terminal are terminals of a field effect transistor. 9 . The method of operating a semiconductor device arrangement according to claim 6 , wherein the voltage at the further terminal area is higher than the voltage at the second terminal by an amount equal to the forward voltage of the second body diode. 10. A method of manufacturing a semiconductor device arrangement for bidirectional operation, the method comprising: forming a field effect transistor comprising a first input terminal, a second input terminal, a control terminal, and a body terminal; arranging a first control diode to be connected between the first input terminal and the control terminal; arranging a second control diode to be connected between the second input terminal and the control terminal; symmetrically disposing a first body diode in a semiconductor substrate body of the semiconductor device and between the body terminal and the first input terminal opposite the first control diode; and arranging a second body diode symmetrically in the semiconductor substrate body and opposite to the second control diode between the body terminal and the second input terminal; The first input terminal and the second input terminal are connected to the corresponding first signal line and the second signal line.