CN110085161A - Display panel and pixel circuit - Google Patents

Abstract

A display panel includes a plurality of pixel circuits, and each pixel circuit includes a first transistor, a writing circuit, a light-emitting unit, a first capacitor and a control circuit. The first terminal of the first transistor is used to receive the first driving signal, and the control terminal is coupled to the first node. The writing circuit is coupled to the first node and the second node, and is used for transmitting the first data signal to the first node and the second data signal to the second node. The first terminal of the light-emitting unit is coupled to the second terminal of the first transistor, and the second terminal is used to receive a second driving signal. The first capacitor is coupled between the first node and the first terminal of the first transistor. The control circuit is used to adjust the second node voltage of the second node according to the lighting control signal. When the voltage of the second node is lower than the preset voltage value, the control circuit outputs the reference voltage to the first node.

Description

Display panel and pixel circuit

technical field

The present disclosure relates to a display panel and a pixel circuit, in particular to a pixel circuit capable of modulating light emitting time.

Background technique

The micro light-emitting diodes produced by the current process technology will produce color shift when different currents flow through them. Therefore, for display panels using micro-LEDs as light-emitting elements, the conduction current of the micro-light-emitting diodes is mostly fixed, and the conduction time of the micro-light-emitting diodes in each frame is modulated to make the human eye feel Screens with different brightness. For the main power signal used to drive the pixel circuit to emit light in the display device, it often needs to provide a large current to light up a plurality of micro light emitting diodes, so that its voltage is reduced due to the load effect. If the circuit responsible for controlling the turn-on time of the micro-LED in the pixel circuit uses the main power signal as the control signal, the pixel circuits at different positions in the display panel will have different voltage drops due to the received main power signal. There are different degrees of time errors when controlling the turn-on and turn-off of the micro light emitting diodes. In addition, thin-film transistors (TFT for short) used in pixel circuits often have characteristic variations due to process factors, that is, thin-film transistors at different positions of the display panel have different characteristics. The non-uniform characteristics of the thin film transistors will also affect the accuracy of the display panel to control the turn-on time of the micro light emitting diodes. Therefore, how to provide a display panel and a pixel circuit capable of accurately controlling the turn-on time of micro-LEDs is a problem to be solved in the industry.

SUMMARY OF THE INVENTION

The present disclosure provides a display panel. The display panel includes a plurality of pixel circuits, wherein each pixel circuit includes a first transistor, a writing circuit, a light emitting unit, a first capacitor and a control circuit. The first transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is used for receiving a first driving signal, and the control terminal of the first transistor is coupled to the first node. The writing circuit is coupled to the first node and the second node, and is used for transmitting the first data signal to the first node, and transmitting the second data signal to the second node. The light emitting unit includes a first terminal and a second terminal, wherein the first terminal of the light emitting unit is coupled to the second terminal of the first transistor, and the second terminal of the light emitting unit is used for receiving a second driving signal. The first capacitor is coupled between the first node and the first terminal of the first transistor. The control circuit is coupled to the first node and the second node, and is used to adjust the second node voltage of the second node according to the light emission control signal, wherein when the second node voltage is lower than a preset voltage value, the control circuit outputs a reference voltage to the first node a node.

The present disclosure provides a display panel. The display panel includes a plurality of pixel circuits, wherein each pixel circuit includes a first transistor, a compensation circuit, a reset circuit, a writing circuit, a control circuit, a first capacitor and a light emitting unit. The first transistor includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the first node. The compensation circuit is coupled to the first terminal and the second terminal of the first transistor, and is coupled to the first node for adjusting the first node voltage of the first node according to the threshold voltage of the first transistor and the first data signal. The reset circuit is used for delivering the reset voltage to the first node. The writing circuit is used for transferring the second data signal to the second node. The control circuit is coupled to the first node and the second node, and is used to adjust the second node voltage of the second node according to the light emission control signal, wherein when the second node voltage is lower than a preset voltage value, the control circuit outputs a reference voltage to the first node a node. The first capacitor is coupled between the first node and the compensation circuit. The light emitting unit includes a first terminal and a second terminal, wherein the first terminal of the light emitting unit is coupled to the compensation circuit, and the second terminal of the light emitting unit is used for receiving the second driving signal.

The present disclosure provides a pixel circuit, and the pixel circuit includes: a first transistor, a light emitting unit, a first capacitor, a second transistor, a second capacitor, a first compensation circuit, a writing circuit and a second compensation circuit. The first transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is used for receiving a first driving signal, and the control terminal of the first transistor is coupled to the first node. The light emitting unit includes a first terminal and a second terminal, wherein the first terminal of the light emitting unit is coupled to the second terminal of the first transistor, and the second terminal of the light emitting unit is used for receiving the second driving signal. The first capacitor is coupled between the first node and the first terminal of the first transistor. The second transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is used for receiving a reference voltage, and the control terminal of the second transistor is coupled to the second node. The second capacitor includes a first terminal and a second terminal, the first terminal of the second capacitor is used to receive the lighting control signal, and the second terminal of the second capacitor is coupled to the second node, wherein the lighting control signal has a ramp pulse waveform . The first compensation circuit is coupled to the first node, the second node and the second terminal of the second transistor, and is used for adjusting the second node voltage of the second node according to the threshold voltage of the second transistor. The writing circuit is used for transmitting the first data signal to the first node, and transmitting the second data signal to the second node. The second compensation circuit is used to transfer the drive current generated by the first transistor to the comparison circuit, wherein when the drive current received by the comparison circuit is not equal to the preset current value, the comparison circuit outputs an adjustment signal to reduce the voltage of the first data signal to The level (level) is set to be negatively related to the magnitude of the drive current.

The above-mentioned display panel and pixel circuit can overcome the problem of color shift of the micro-light-emitting diode as a light-emitting unit.

Description of drawings

In order to make the above-mentioned and other purposes, features, advantages and embodiments disclosed more obvious and understandable, the description of the accompanying drawings in the specification is as follows:

FIG. 1 is a simplified functional block diagram of a display panel according to an embodiment of the disclosure.

FIG. 2 is a functional block diagram of the pixel circuit in FIG. 1 .

FIG. 3 is a simplified waveform diagram of a control signal of a display panel according to an embodiment of the disclosure.

FIG. 4 is a schematic diagram of node voltage waveforms of the pixel circuit in FIG. 2 .

FIG. 5A is a schematic diagram of an equivalent circuit operation of the pixel circuit in FIG. 2 in a first sub-period.

FIG. 5B is a schematic diagram of an equivalent circuit operation of the pixel circuit in FIG. 2 in the second sub-period.

FIG. 6 is a simplified functional block diagram of a pixel circuit according to an embodiment of the disclosure.

FIG. 7 is a simplified functional block diagram of a display panel according to an embodiment of the disclosure.

FIG. 8 is a functional block diagram of the pixel circuit in FIG. 7 .

FIG. 9 is a simplified waveform diagram of a control signal of a display panel according to an embodiment of the disclosure.

FIG. 10 is a schematic diagram of an equivalent circuit operation of the pixel circuit in FIG. 8 in a compensation stage.

FIG. 11 is a simplified functional block diagram of a display panel according to an embodiment of the disclosure.

FIG. 12 is a functional block diagram of the pixel circuit in FIG. 11 .

FIG. 13 is a simplified waveform diagram of a control signal of a display panel according to an embodiment of the disclosure.

FIG. 14 is a simplified functional block diagram of a display panel according to an embodiment of the disclosure.

FIG. 15 is a circuit block diagram of the pixel circuit in FIG. 14 .

FIG. 16 is a simplified waveform diagram of a control signal of a display panel according to an embodiment of the disclosure.

FIG. 17 is a schematic diagram of waveforms when a display panel displays multiple frames of images according to an embodiment of the disclosure.

Description of reference numbers:

100, 700, 1100, 1400: display panel

102: Source driver

104: Gate driver

110, 610, 710, 1110, 1140: pixel circuit

px: pixel matrix

210: write circuit

220: control circuit

T1 ~ T2: first transistor ~ second transistor

C1～C2: first capacitor to second capacitor

N1～N2: first node～second node

D1～D2: first data signal～second data signal

SW1～SW15: the first switch to the fifteenth switch

V1～V2: first node voltage～second node voltage

VDD: the first driving signal

VSS: Second drive signal

Vpwm: lighting control signal

Vx: reference voltage

EU: Luminous Unit

R1～R4: data lines

L1～L5: first voltage level～fifth voltage level

S1[1]～S1[n], S1: the first control signal

S2[1]～S2[n], S2: Second control signal

S3[1]～S3[n], S3: the third control signal

S4[1]～S4[n], S4: the fourth control signal

S5[1]～S5[n], S5: fifth control signal

S6[1]～S6[n], S6: the sixth control signal

S7[1]～S7[n], S7: the seventh control signal

S8[1]～S8[n], S8: Eighth control signal

S9[1]～S9[n], S9: ninth control signal

S10[1]～S10[n], S10: tenth control signal

S11[1]～S11[n], S11: Eleventh control signal

S12[1]～S12[n], S12: Twelfth control signal

720, 1420: comparison circuit

AD: adjust the signal

1210: Compensation circuit

1220: reset circuit

1230: write circuit

1240: control circuit

Vset: reset voltage

1510: first compensation circuit

1520: write circuit

1530: second compensation circuit

Detailed ways

Embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a display panel 100 according to an embodiment of the disclosure. The display panel 100 includes a source driver 102 , a gate driver 104 and a plurality of pixel circuits 110 , wherein the pixel circuits 110 are arranged into a pixel matrix PX having multiple columns. The gate driver 104 is used for correspondingly providing a plurality of first control signals S1[1]˜S1[n] and a plurality of second control signals S2[1]˜S2[n] to the pixel circuits 110 of multiple columns to drive the pixels Matrix PX updates the display.

For example, the gate driver 104 provides the first control signal S1[1] and the second control signal S2[1] to the pixel circuit 110 of the first column, and provides the first control signal S1[2] and the second control signal S2[ 2] to the pixel circuit 110 in the second column, and so on, until the gate driver 104 provides the first control signal S1[n] and the second control signal S2[n] to the pixel circuit 110 in the nth column, where n is positive integer. In order to make the drawing concise and easy to explain, other elements and connections in the display panel 100 are not shown in FIG. 1 .

The references [1] to [n] in the component numbers and signal numbers used in this disclosure and the drawings are only for convenience to refer to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In this disclosure specification and drawings, if a component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to the component group (group) or signal group to which it belongs. Any element or signal not specified in the For example, the object referred to by the signal number S1[1] is the first control signal S1[1], and the object referred to by the signal number S1 is any unspecified first control signal among the first control signals S1[1]~S1[n]. Control signal S1. For another example, the object referred to by the signal number S2[1] is the second control signal S2[1], and the object referred to by the signal number S2 is any unspecified second control signal S2[1]-S2[n]. Two control signals S2.

FIG. 2 is a functional block diagram of the pixel circuit 110 in FIG. 1 . The pixel circuit 110 includes a first transistor T1, a first capacitor C1, a writing circuit 210, a control circuit 220 and a light emitting unit EU. The first transistor T1 includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor T1 is used to receive the first driving signal VDD, and the control terminal is coupled to the first node N1. The first capacitor C1 is coupled between the first node N1 and the first end of the first transistor T1. The light emitting unit EU includes a first terminal and a second terminal, wherein the first terminal of the light emitting unit EU is coupled to the second terminal of the first transistor T1, and the second terminal of the light emitting unit EU is used for receiving the second driving signal VSS.

The writing circuit 210 is coupled to the first node N1 and the second node N2 for transmitting the first data signal D1 to the first node N1 and transmitting the second data signal D2 to the second node N2. Specifically, the writing circuit 210 includes a first switch SW1 and a second switch SW2. The first switch SW1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first switch SW1 is coupled to the first node N1, and the second terminal is used for receiving the first data signal D1. The second switch SW2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second switch SW2 is coupled to the second node N2, and the second terminal is used for receiving the second data signal D2.

In this embodiment, the control terminal of the first switch SW1 is used to receive the first control signal S1, and the control terminal of the second switch SW2 is used to receive the second control signal S2. Both the second terminal of the first switch SW1 and the second terminal of the second switch SW2 are coupled to the same data line R1, so as to respectively receive the first data signal D1 and the second data signal D2 from the source driver 102 through the data line R1 .

In some embodiments, the second end of the first switch SW1 and the second end of the second switch SW2 of the pixel circuit 110 may also be respectively coupled to different data lines, and are respectively connected to the source driver via different data lines. 102 receives the first data signal D1 and the second data signal D2.

The control circuit 220 is coupled to the first node N1 and the second node N2, and is used for adjusting the second node voltage V2 of the second node N2 according to the light emission control signal Vpwm. Specifically, the control circuit 220 includes a second transistor T2 and a second capacitor C2. The second transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 is used to receive the reference voltage Vx, the second terminal is coupled to the first node N1, and the control terminal is coupled to the second node N2. The second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is used for receiving the light emission control signal Vpwm, and the second terminal is coupled to the second node N2.

When the second node voltage V2 is lower than the preset voltage value, the control circuit 220 will output the reference voltage Vx to the first node N1, so as to set the first node voltage V1 of the first node N1 equal to the reference voltage Vx, wherein the reference The voltage Vx is higher than or equal to the voltage level of the first driving signal VDD. In this way, the conduction time of the first transistor T1 can be determined, and the detailed operation of the control circuit 220 will be further explained in the following paragraphs.

In practice, the first switch SW1 , the second switch SW2 , the first transistor T1 and the second transistor T2 can be realized by P-type thin film transistors, or by other suitable types of P-type transistors. The light-emitting unit EU can be realized by organic light-emitting diodes (organic light-emitting diodes) or micro-light-emitting diodes.

FIG. 3 is a simplified waveform diagram of a control signal of the display panel 100 according to an embodiment of the disclosure. The operation of the pixel circuit 110 will be further described below with reference to FIG. 2 and FIG. 3 . In this embodiment, the reference voltage Vx has a fixed voltage level. In the writing stage, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched from the second voltage level L2 to the first voltage level L1, wherein the first voltage level L1 is higher than the first voltage level L1. Two voltage levels L2. In this way, it can ensure that the light emitting unit EU remains in the off state.

In addition, the light emission control signal Vpwm is maintained at the third voltage level L3. The first control signals S1[1]˜S1[n] will switch from a disabled level (for example, a high voltage level) to an enabled level (for example, a low voltage level) in sequence, and the second control signal S2[ 1]～S2[n] will also be switched from disabled level to enabled level in sequence. During the period when two adjacent first control signals S1 are sequentially switched to the enable level, one second control signal S2 is switched to the enable level. Similarly, when two adjacent second control signals S2 are sequentially switched to the enable level, one first control signal S1 is switched to the enable level.

For example, as shown in FIG. 3 , while the first control signal S1 [ 1 ] and the first control signal S1 [ 2 ] are switched to the enable level, the second control signal S2 [ 1 ] is switched to the enable level. During the period when the second control signal S2[1] and the second control signal S2[2] are switched to the enable level, the first control signal S1[2] is switched to the enable level.

In other words, in the writing phase, the first switch SW1 and the second switch SW2 of the pixel circuit 110 are sequentially turned on. Therefore, the first data signal D1 is transmitted to the first node N1 first, and then the second data signal D2 is transmitted to the second node N2. It is worth mentioning that the second data signal D2 sets the second node voltage V2 higher than the reference voltage Vx to turn off the second transistor T2.

In the light-emitting phase, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched from the first voltage level L1 to the second voltage level L2 to turn on the light-emitting unit EU. The light emitting control signal Vpwm gradually decreases from the third voltage level L3, thus having a ramp pulse waveform. Both the first control signals S1[1]˜S1[n] and the second control signals S2[1]˜S2[n] are maintained at the disabled level. Therefore, both the first switch SW1 and the second switch SW2 of the pixel circuit 110 are kept in an off state.

The operation of the pixel circuit 110 in the light-emitting phase will be further described below with reference to FIG. 4 . As shown in FIG. 4 , the light-emitting phase includes a first sub-period and a second sub-period.

In the first sub-period, the equivalent circuit of the pixel circuit 110 is as shown in FIG. 5A . The first transistor T1 generates a driving current Idr as shown in the following "Formula 1" according to the first node voltage V1 to light up the light emitting unit EU:

Wherein, Vth1 represents the threshold voltage of the first transistor T1. k represents the product of the carrier mobility of the first transistor T1 , the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

As the voltage level of the light emission control signal Vpwm gradually decreases, the second node voltage V2 will also gradually decrease due to the capacitive coupling effect of the second capacitor C2. Since the second node voltage V2 at this time is still higher than the preset voltage value shown in the following "Formula 2", the second transistor T2 will remain in the off state:

Vp＝Vx-|Vth2|《Formula 2》

Wherein, Vth2 represents the threshold voltage of the second transistor T2. Vp represents the aforementioned preset voltage value.

Next, in the second sub-period, the equivalent circuit of the pixel circuit 110 is as shown in FIG. 5B . As the voltage level of the lighting control signal Vpwm continues to decrease, the second node voltage V2 will decrease to be less than the preset voltage value shown in <Formula 2>. Therefore, the second transistor T2 is turned on and the reference voltage Vx is transmitted to the first node N1, so that the first node voltage V1 is equal to the reference voltage Vx. In this embodiment, the reference voltage Vx is higher than or equal to the first voltage level L1 of the first driving signal VDD. Therefore, in the second sub-period, the first transistor T1 is switched from the on state to the off state.

It can be seen from the above that the driving current Idri is negatively correlated with the magnitude of the first node voltage V1 set by the first data signal D1. The length of the first sub-period is positively related to the magnitude of the second node voltage V2 set by the second data signal D2. Therefore, by fixing the voltage level of the first data signal D1 and modulating the voltage level of the second data signal D2, the light-emitting time of the pixel circuit 110 can be controlled to generate a fixed driving current Idr.

In other words, the pixel circuit 110 can avoid the problem of color shift in the light emitting unit EU due to the flow of currents of different magnitudes. The pixel circuit 110 can also make the human eyes perceive the display images with different brightness in a multi-frame image in an approximate integration manner through different light-emitting times.

In the above-mentioned embodiments, the first driving signal VDD is a DC signal, and the second driving signal VSS is an AC signal, so as to turn off the light emitting unit EU during the writing phase and turn on the light emitting unit EU during the light emitting phase. However, the present invention is not limited to the above embodiments, and the voltage levels of the first driving signal VDD and the second driving signal VSS can be set according to actual needs.

For example, in some embodiments, the first driving signal VDD is switched from the first voltage level L1 to the second voltage level L2 during the writing phase, and switched from the second voltage level L2 to the first voltage level during the light emitting phase. The voltage level L1, and the second driving signal VSS is maintained at the second voltage level L2.

FIG. 6 is a simplified functional block diagram of a pixel circuit 610 according to an embodiment of the disclosure. The pixel circuit 610 is similar to the pixel circuit 110 , and the pixel circuit 110 of the display panel 100 can be replaced by the pixel circuit 610 .

The difference between the pixel circuit 610 and the pixel circuit 110 is that the control terminals of the first switch SW1 and the second switch SW2 of the pixel circuit 610 are used to receive the first control signal S1 together. In addition, the second end of the first switch SW1 of the pixel circuit 610 is coupled to the data line R1 to receive the first data signal from the data line R1, and the second end of the second switch SW2 is coupled to another data line R2, to receive a second data signal from the data line R2.

In other words, in the writing phase, when the first data signal D1 is transmitted to the first node N1, the second data signal D2 is also transmitted to the second node N2. In this way, the duration of the writing phase can be shortened. The other connection methods, components, implementations and advantages of the aforementioned pixel circuit 110 are all applicable to the pixel circuit 610 , and are not repeated here for the sake of brevity.

FIG. 7 is a simplified functional block diagram of a display panel 700 according to an embodiment of the disclosure. The display panel 700 is similar to the display panel 100, the difference is that the display panel 700 includes a plurality of pixel circuits 710 and comparison circuits 720, and the display panel 700 correspondingly provides a plurality of first control signals S1[1]˜S1[n], a plurality of The second control signals S2 [ 1 ]˜S2 [n] and the plurality of third control signals S3 [ 1 ]˜S3 [n] are sent to the pixel circuits 710 of multiple columns.

The comparison circuit 720 is coupled to the plurality of pixel circuits 710 and is used for adjusting the voltage level of the first data signal D1 to compensate characteristic variations of the pixel circuits 710 at different positions of the display panel 700 . In practice, the comparison circuit 720 can be integrated in the source driver 102 , and can also be realized by a circuit different from the source driver 102 . The detailed operation of the comparison circuit 720 will be further explained in the following paragraphs.

FIG. 8 is a functional block diagram of the pixel circuit 710 in FIG. 7 . The pixel circuit 710 is similar to the aforementioned pixel circuit 110 , the difference is that the pixel circuit 710 further includes a third switch SW3 . The third switch SW3 includes a first terminal, a second terminal and a control terminal. The first terminal of the third switch SW3 is coupled to the comparison circuit 720 , the second terminal is coupled to the second terminal of the first transistor T1 , and the control terminal is used to receive the third control signal S3 .

FIG. 9 is a simplified waveform diagram of a control signal of the display panel 700 according to an embodiment of the disclosure. The operation of the pixel circuit 710 will be further described below with reference to FIG. 8 and FIG. 9 .

In the reset phase, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched from the second voltage level L2 to the first voltage level L1, wherein the first voltage level L1 is higher than The second voltage level L2. The light emission control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is maintained at the fourth voltage level L4. The first control signals S1[1]˜S1[n] are switched to enable levels. Then, after the first control signals S1[1]˜S1[n] are switched to the disabled level, the second control signals S2[1]˜S2[n] are switched to the enabled level. The third control signal S3 is maintained at a disabled level to turn off the third switch SW3.

Therefore, the first switch SW1 is turned on first, so that the first data signal D1 is transmitted to the first node N1 to set the first node voltage V1. Then, after the first switch SW1 is turned off, the second switch SW2 is turned on, so that the second data signal D2 is transmitted to the second node N2 to set the second node voltage V2. It should be noted that the first node voltage V1 is lower than the first voltage level L1 of the first driving signal VDD, so as to turn on the first transistor T1. The second node voltage V2 is higher than the fourth voltage level L4 of the reference voltage Vx, so that the second transistor T2 is turned off.

In the compensation stage, the first driving signal VDD and the second driving signal VSS are maintained at the first voltage level L1. The light emission control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is maintained at the fourth voltage level L4. The first control signal S1 and the second control signal S2 are switched to a disable level to turn off the first switch SW1 and the second switch SW2. The third control signal S3 is switched to enable level to turn on the third switch SW3.

Therefore, the pixel circuit 710 forms an equivalent circuit as shown in FIG. 10 . At this time, the first transistor T1 generates a driving current Idr according to the first node voltage V1. The driving current Idr flows to the comparison circuit 720 through the third switch SW3, and the comparison circuit 720 compares the driving current Idr with a pre-stored preset current value.

It can be known from the aforementioned "Formula 1" that the magnitude of the driving current Idr is negatively correlated with the first node voltage V1 and negatively correlated with the threshold voltage of the first transistor T1. Therefore, when the comparison circuit 720 finds that the driving current Idr is not equal to the preset current value, the comparison circuit 720 will determine that the threshold voltage of the first transistor T1 has changed. At this time, the comparison circuit 720 outputs the adjustment signal AD to the source driver 102 to set the voltage level of the first data signal D1 to be positively related to the magnitude of the driving current Idr to compensate the threshold voltage variation of the first transistor T1 .

In the following write-in phase and light-emitting phase, the third control signal S3 is maintained at a disable level, so that the third transistor T3 is kept in an off state. The rest of the operation modes and advantages of the aforementioned pixel circuit 110 in the write-in phase and the light-emitting phase are applicable to the pixel circuit 710 , and for the sake of brevity, the details are not repeated here.

In some embodiments in which the first switch SW1 and the second switch SW2 of the pixel circuit 710 are respectively coupled to different data lines, the first switch SW1 and the second switch SW2 can be turned on at the same time during the reset phase and/or the write phase. pass to shorten the length of the reset phase and/or the write phase.

From the above, it can be seen that the voltage level of the first voltage signal D1 is adaptively adjusted according to the variation of the threshold voltage of the first transistor T1 . Therefore, even though the first transistors T1 in different regions of the display panel 700 have different characteristics, the first transistors T1 can still generate the same driving current Idr in the light-emitting phase. In other words, the display panel 700 can overcome unstable factors in the manufacturing process and provide high-quality display images.

FIG. 11 is a simplified functional block diagram of a display panel 1100 according to an embodiment of the disclosure. The display panel 1100 includes a source driver 102 , a gate driver 104 and a plurality of pixel circuits 1110 , wherein the pixel circuits 1110 are arranged into a pixel matrix PX having multiple columns. The gate driver 104 is used for correspondingly providing a plurality of fourth control signals S4[1]˜S4[n], a plurality of fifth control signals S5[1]˜S5[n] and a plurality of sixth control signals S6[1 ] to S6[n] to multiple columns of pixel circuits 1110 .

FIG. 12 is a functional block diagram of the pixel circuit 1110 in FIG. 11 . The pixel circuit 1110 includes a first transistor T1 , a light emitting unit EU, a compensation circuit 1210 , a reset circuit 1220 , a writing circuit 1230 and a control circuit 1240 . The first transistor T1 includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor T1 is coupled to the first node N1.

The compensation circuit 1210 is coupled to the first terminal and the second terminal of the first transistor T1, and is coupled to the first node N1. The compensation circuit 1210 is used for adjusting the first node voltage V1 of the first node N1 according to the threshold voltage of the first transistor T1 and the first data signal D1, so as to compensate the variation of the threshold voltage of the first transistor T1. The reset circuit 1220 is used to transmit the reset voltage Vset to the first node N1. The writing circuit 1230 is used for transmitting the second data signal D2 to the second node N2.

The control circuit 1240 is coupled to the first node N1 and the second node N2, and is used for adjusting the second node voltage V2 of the second node N2 according to the light emission control signal Vpwm. When the voltage V2 of the second node is lower than the preset voltage value shown in the aforementioned "Formula 2", the control circuit 1240 outputs the reference voltage Vx to the first node V1 to determine the conduction time of the first transistor T1. The first capacitor C1 is coupled between the first node N1 and the compensation circuit 1210 . The light emitting unit EU includes a first end and a second end. The first terminal of the light emitting unit EU is coupled to the compensation circuit 1210, and the second terminal is used for receiving the second driving signal VSS.

Specifically, the compensation circuit 1210 includes a fourth switch SW4 , a fifth switch SW5 , a sixth switch SW6 and a seventh switch SW7 . The fourth switch SW4 includes a first terminal, a second terminal and a control terminal. The first terminal of the fourth switch SW4 is used for receiving the first data signal D1, the second terminal is coupled to the first terminal of the first transistor T1, and the control terminal is used for receiving the fourth control signal S4. The fifth switch SW5 includes a first terminal, a second terminal and a control terminal. The first terminal of the fifth switch SW5 is coupled to the first node N1, the second terminal is coupled to the second terminal of the first transistor T1, and the control terminal is used for receiving the fourth control signal S4.

The sixth switch SW6 includes a first terminal, a second terminal and a control terminal. The first end of the sixth switch SW6 is used to receive the first driving signal VDD, the second end is coupled to the first end of the first transistor T1, and the control end is used to receive the fifth control signal S5. The seventh switch SW7 includes a first terminal, a second terminal and a control terminal. The first terminal of the seventh switch SW7 is coupled to the second terminal of the first transistor T1, the second terminal is coupled to the first terminal of the light emitting unit EU, and the control terminal is used for receiving the fifth control signal S5.

The reset circuit 1220 includes an eighth switch SW8, wherein the eighth switch SW8 includes a first terminal, a second terminal and a control terminal. The first terminal of the eighth switch SW8 is coupled to the first node N1, the second terminal is used for receiving the reset voltage Vset, and the control terminal is used for receiving the fourth control signal S4 of the previous column in the pixel matrix PX.

For example, in the case that the pixel matrix PX has n columns, take the pixel circuit 1110 in FIG. 12 located in the nth column as an example. The control terminals of the fourth switch SW4 and the fifth switch SW5 will receive the fourth control signal S4[n], while the control terminal of the eighth switch SW8 will receive the fourth control signal S4[n-1 of column n-1 ], where n is a positive integer.

The writing circuit 1230 includes a ninth switch SW9, wherein the ninth switch SW9 includes a first terminal, a second terminal and a control terminal. The first terminal of the ninth switch SW9 is coupled to the second node N2, the second terminal is used for receiving the second data signal D2, and the control terminal is used for receiving the sixth control signal S6. In this embodiment, the first end of the fourth switch SW4 is coupled to the data line R3 to receive the first data signal D1 from the data line R3, and the second end of the ninth switch SW9 is coupled to the data line R4 to automatically receive the first data signal D1 from the data line R3. The data line R4 receives the second data signal D2, but the invention is not limited to this embodiment. In some embodiments, the first terminal of the fourth switch SW4 and the second terminal of the ninth switch SW9 are coupled to the same data line, and the fourth switch SW4 and the ninth switch SW9 can be connected successively from the data line. The first data signal D1 and the second data signal D2 are received.

In practice, the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, and the ninth switch SW9 can be realized by P-type thin film transistors, or other suitable types of P-type thin film transistors. type transistor to achieve.

FIG. 13 is a simplified waveform diagram of a control signal of the display panel 1100 according to an embodiment of the disclosure. In this embodiment, the reference voltage Vx has a fixed voltage level. In the compensation stage, the first driving signal VDD is maintained at the first voltage level L1, the second driving signal VSS is switched from the second voltage level L2 to the first voltage level L1, and the first voltage level L1 is higher than the second voltage level L1. Voltage level L2. The light emission control signal Vpwm is maintained at the third voltage level L3. In addition, the fourth control signals S4[1]˜S4[n] are switched to enable levels in sequence. Both the fifth control signals S5[1]˜S5[n] and the sixth control signals S6[1]˜S6[n] are maintained at the disable level.

Therefore, in the compensation stage, the ninth switch SW9 is kept in an off state. The reset voltage Vset is first transmitted to the first node N1 through the eighth switch SW8 to reset the first node voltage V1 to the reset voltage Vset. Next, after the eighth switch SW8 is switched from the on state to the off state, the first data signal D1 will charge the first node N1 through the fourth switch SW4 and the fifth switch SW5 until the voltage V1 of the first node is equal to or below The voltage value shown in "Formula 3":

V1＝D1-|Vth1|《Formula 3》

Next, in the writing phase, the first driving signal VDD and the second driving signal VSS are maintained at the first voltage level L1. The light emission control signal Vpwm is maintained at the third voltage level L3. In addition, the sixth control signals S6[1]˜S6[n] are switched to enable levels in sequence. Both the fourth control signals S4[1]˜S4[n] and the fifth control signals S5[1]˜S5[n] are maintained at the disable level.

Therefore, in the writing phase, the fourth switch SW4 , the fifth switch SW5 , the sixth switch SW6 , the seventh switch SW7 and the eighth switch SW8 are kept in the off state. The second data signal D2 is transmitted to the second node N2 through the ninth switch SW9 to set the second node voltage V2.

Next, in the light-emitting phase, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched from the first voltage level L1 to the second voltage level L2. The light emission control signal Vpwm gradually decreases from the third voltage level L3, thus having a ramp pulse waveform. In addition, the fourth control signals S4[1]˜S4[n] and the sixth control signals S6[1]˜S6[n] are maintained at the disable level. The fifth control signals S5[1]˜S5[n] are switched to enable levels.

Therefore, the fourth switch SW4 , the fifth switch SW5 , the eighth switch SW8 and the ninth switch SW9 will be in an off state. The sixth switch SW6 and the seventh switch SW7 are turned on. Due to the capacitive coupling effect of the second capacitor C2, the second node voltage V2 gradually decreases along with the light emission control signal Vpwm. The first transistor T1 will generate a driving current Idr as shown in the following "Formula 4":

In this embodiment, the reference voltage Vx is higher than or equal to the first voltage level L1 of the first driving signal VDD. Therefore, the first transistor T1 will continue to generate the driving current Idr until the voltage V2 of the second node drops below the preset voltage value shown in the aforementioned <Formula 2>. When the second node voltage V2 is less than the preset voltage value shown in the aforementioned "Formula 2", the second transistor T2 is turned on, so that the first node voltage V1 is set as the reference voltage Vx, and then the first transistor T1 is switched to off. off state.

From "Formula 4", it can be seen that the magnitude of the driving current Idr in this embodiment will not be affected by the variation of the threshold voltage of the first transistor T1. Therefore, the display panel 1100 can overcome unstable factors in the manufacturing process and provide high-quality display images. Additionally, in some embodiments, the order of the compensation phase and the write phase of FIG. 13 may be reversed.

FIG. 14 is a simplified functional block diagram of a display panel 1400 according to an embodiment of the disclosure. The display panel 1400 includes a source driver 102 , a gate driver 104 , a plurality of pixel circuits 1410 and a comparison circuit 1420 , wherein the pixel circuits 1410 are arranged into a pixel matrix PX with multiple columns. The gate driver 104 is used for correspondingly providing a plurality of seventh control signals S7[1]-S7[n], a plurality of eighth control signals S8[1]-S8[n], a plurality of ninth control signals S9[1 ]～S9[n], multiple tenth control signals S10[1]～S10[n], multiple eleventh control signals S11[1]～S11[n], and multiple twelfth control signals S12[1 ] to S12[n] to multiple columns of pixel circuits 1410 .

FIG. 15 is a circuit block diagram of the pixel circuit 1410 in FIG. 14 . The pixel circuit 1410 includes a first transistor T1 , a light emitting unit EU, a first capacitor C1 , a second transistor T2 , a second capacitor C2 , a first compensation circuit 1510 , a writing circuit 1520 , and a second compensation circuit 1530 .

The comparison circuit 1420 is coupled to the plurality of pixel circuits 1410 and is used for adjusting the voltage level of the first data signal D1 to compensate the threshold voltage variation of the transistors in the pixel circuits 1410 . In practice, the comparison circuit 1420 can be integrated in the source driver 102 , and can also be realized by a circuit different from the source driver 102 . The detailed operation of the comparing circuit 1420 will be further explained in the following paragraphs.

The first transistor T1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor T1 is used for receiving the first driving signal VDD, and the control terminal is coupled to the first node N1. The light emitting unit EU includes a first end and a second end. The first terminal of the light emitting unit EU is coupled to the second terminal of the first transistor T1, and the second terminal of the light emitting unit EU is used for receiving the second driving signal VSS.

The first capacitor C1 is coupled between the first node N1 and the first end of the first transistor T1. The second transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 is used for receiving the reference voltage Vx, and the control terminal is coupled to the second node N2. The second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is used for receiving the light emission control signal Vpwm, and the second terminal is coupled to the second node N2.

The first compensation circuit 1510 is coupled to the first node N1, the second node N2 and the second terminal of the second transistor T2. The first compensation circuit 1510 is used for adjusting the second node voltage V2 of the second node N2 according to the threshold voltage of the second transistor T2 to compensate the variation of the threshold voltage of the second transistor T2.

Specifically, the first compensation circuit 1510 includes a tenth switch SW10 , an eleventh switch SW11 and a twelfth switch SW12 . The tenth switch SW10 includes a first terminal, a second terminal and a control terminal. The first end of the tenth switch SW10 is used to receive the reset voltage Vset, the second end is coupled to the second node N2, and the control end is used to receive the seventh control signal S7. The eleventh switch SW11 includes a first terminal, a second terminal and a control terminal. The first terminal of the eleventh switch SW11 is coupled to the second node N2, the second terminal is coupled to the second terminal of the second transistor T2, and the control terminal is used for receiving the eighth control signal S8. The twelfth switch SW12 includes a first terminal, a second terminal and a control terminal. The first terminal of the twelfth switch SW12 is coupled to the second terminal of the second transistor T2, the second terminal is coupled to the first node N1, and the control terminal is used for receiving the ninth control signal S9.

The writing circuit 1520 is used for transmitting the first data signal D1 to the first node N1, and transmitting the second data signal D2 to the second node N2. Specifically, the writing circuit 1520 includes a third capacitor C3 , a thirteenth switch SW13 and a fourteenth switch SW14 . The third capacitor C3 includes a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the second node N2. The thirteenth switch SW13 includes a first terminal, a second terminal and a control terminal. The first terminal of the thirteenth switch SW13 is coupled to the first node N1, the second terminal is used for receiving the first data signal D1, and the control terminal is used for receiving the tenth control signal S10. The fourteenth switch SW14 includes a first terminal, a second terminal and a control terminal. The first terminal of the fourteenth switch SW14 is coupled to the second terminal of the third capacitor C3, the second terminal is used for receiving the second data signal D2, and the control terminal is used for receiving the eleventh control signal S11.

The second compensation circuit 1530 is used to transmit the driving current Idr generated by the first transistor T1 to the comparison circuit 1420, and includes a fifteenth switch SW15, wherein the fifteenth switch SW15 includes a first terminal, a second terminal and a control terminal. The first terminal of the fifteenth switch SW15 is coupled to the comparison circuit 1420 , the second terminal is coupled to the second terminal of the first transistor T1 , and the control terminal is used to receive the twelfth control signal S12 .

The comparing circuit 1420 is used for comparing the received driving current Idr with a preset current value to adjust the voltage level of the first data signal D1. The operations of the second compensation circuit 1530 and the comparison circuit 1420 will be further described in the following paragraphs. In practice, the tenth switch SW10, the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, and the fifteenth switch SW15 can be realized by P-type thin film transistors, or by other suitable types of P-type transistors.

FIG. 16 is a simplified waveform diagram of a control signal of the display panel 1400 according to an embodiment of the disclosure. In the reset phase, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched from the second voltage level L2 to the first voltage level L1 to turn off the light emitting unit EU, wherein the first The voltage level L1 is higher than the second voltage level L2. The light emission control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is maintained at the fourth voltage level L4. The seventh control signal S7, the tenth control signal S10, and the eleventh control signal S11 have an enable level (for example, a low voltage level), and the eighth control signal S8, the ninth control signal S9, and the twelfth control signal S12 has a disable level (eg, a high voltage level).

Therefore, in the reset phase, the tenth switch SW10, the thirteenth switch SW13, and the fourteenth switch SW14 are in the on state, and the eleventh switch SW11, the twelfth switch SW12, and the fifteenth switch SW15 are in the off state . The first voltage signal D1 is transmitted to the first node N1 through the thirteenth switch SW13 to reset the voltage V1 of the first node. The second voltage signal D2 is transmitted to the second end of the third capacitor C3 through the fourteenth switch SW14 . The reset voltage Vset is delivered to the second node N2 through the tenth switch SW10 to reset the second node voltage V2.

Next, in the compensation phase, the first driving signal VDD and the second driving signal VSS are maintained at the first voltage level L1. The light emitting control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is switched to the fifth voltage level L5, wherein the fifth voltage level L5 is higher than the fourth voltage level L4. The eighth control signal S8 and the eleventh control signal S11 have an enable level, and the seventh control signal S7, the ninth control signal S9, the tenth control signal S10, and the twelfth control signal S12 have a disable level .

Therefore, in the compensation phase, the eleventh switch SW11 and the fourteenth switch SW14 are turned on, and the tenth switch SW10, the twelfth switch SW12, the thirteenth switch SW13, and the fifteenth switch SW15 are turned off. broken. The reference voltage Vx will charge the second node N2 through the eleventh switch SW11 until the second node voltage V2 is equal to the voltage value shown in the following "Formula 5":

V2＝L5-|Vth2|《Formula 5》

Next, in the first writing phase, the first driving signal VDD and the second driving signal VSS are maintained at the first voltage level L1. The light emission control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is maintained at the fifth voltage level L5. The tenth control signals S10[1]˜S10[n] are switched to enable levels in sequence. The seventh control signal S7 , the eighth control signal S8 , the ninth control signal S9 , the eleventh control signal S11 and the twelfth control signal S12 have disable levels.

Therefore, the thirteenth switch SW13 is turned on, and the tenth switch SW10 , the eleventh switch SW11 , the twelfth switch SW12 , the fourteenth switch SW14 and the fifteenth switch SW15 are turned off. The first voltage signal D1 is transmitted to the first node N1 through the thirteenth switch SW13 to set the first node voltage V1.

Next, in the second writing phase, the first driving signal VDD and the second driving signal VSS are maintained at the first voltage level L1. The light emission control signal Vpwm is maintained at the third voltage level L3, and the reference voltage Vx is maintained at the fifth voltage level L5. The eleventh control signals S11[1]˜S11[n] are sequentially switched to enable levels. The seventh control signal S7 , the eighth control signal S8 , the ninth control signal S9 , the tenth control signal S10 and the twelfth control signal S12 have disable levels.

Therefore, the fourteenth switch SW14 is turned on, and the tenth switch SW10 , the eleventh switch SW11 , the twelfth switch SW12 , the thirteenth switch SW13 and the fifteenth switch SW15 are turned off. The second voltage signal D2 will be transmitted to the second terminal of the third capacitor C3 through the thirteenth switch SW13, and the voltage variation of the second terminal of the third capacitor C3 will be transmitted to the second terminal due to the capacitive coupling effect of the third capacitor C3. Node N2, so that the second node voltage V2 has a voltage value as shown in the following "Formula 6":

V2＝L5-|Vth2|+ΔV "Formula 6"

Wherein, ΔV represents the voltage variation of the second terminal of the third capacitor C3 in the second writing phase.

In the light-emitting phase and the second writing phase, the first driving signal VDD is maintained at the first voltage level L1, and the second driving signal VSS is switched to the second voltage level L2 to turn on the light-emitting unit EU. The light emitting control signal Vpwm gradually decreases from the third voltage level L3, and the reference voltage Vx is maintained at the fifth voltage level L5. The ninth control signal S9 has an enable level. The seventh control signal S7 , the eighth control signal S8 , the tenth control signal S10 , the eleventh control signal S11 and the twelfth control signal S12 have disable levels.

Therefore, the tenth switch SW10 , the eleventh switch SW11 , the twelfth switch SW12 , the thirteenth switch SW13 , the fourteenth switch SW14 and the fifteenth switch SW15 are turned off. Due to the capacitive coupling effect of the second capacitor C2, the second node voltage V2 gradually decreases along with the light emission control signal Vpwm. The first transistor T1 generates a driving current Idr according to the first node voltage V1 to light up the light emitting unit EU.

In this embodiment, the fifth voltage level L5 of the reference voltage Vx is higher than or equal to the first voltage level L1 of the first driving signal VDD. Therefore, the first transistor T1 will continue to generate the driving current Idr until the voltage V2 of the second node drops below the preset voltage value shown in the aforementioned <Formula 2>. In this case, the second transistor T2 is turned on, so that the first node voltage V1 is set to the fifth voltage level L5, and then the first transistor T1 is switched to an off state.

FIG. 17 is a schematic diagram of waveforms when the display panel 1400 displays multiple frames of images. During each of the first frame to the nth frame, the display panel 1400 will execute the reset phase, the compensation phase, the first write phase, the second write phase, and the light emitting phase in FIG. 16 . Before the start of each of the first frame to the nth frame, a plurality of tenth control signals S10[1]˜S10[n] will have an enable level, so as to reduce the first node voltage V1 of all pixel circuits 1410 to set to a preset voltage level.

Next, one of the twelfth control signals S12[1]˜S12[n] is switched to an enable level to turn on the fifteenth switch SW15 corresponding to a row of pixel circuits 1410 . The driving current Idr generated by the first transistor T1 flows to the comparison circuit 1420 through the fifteenth switch SW15 , and the comparison circuit 1420 compares the driving current Idr with a preset current value stored in advance. It can be known from the aforementioned "Formula 1" that the magnitude of the driving current Idr is negatively correlated with the first node voltage V1 and negatively correlated with the threshold voltage of the first transistor T1. Therefore, when the comparison circuit 1420 finds that the driving current Idr is not equal to the preset current value, the comparison circuit 1420 will determine that the threshold voltage of the first transistor T1 has changed. At this time, the comparison circuit 1420 outputs the adjustment signal AD to the source driver 102 to set the voltage level of the first data signal D1 to be positively related to the magnitude of the driving current Idr in the first writing phase. In this way, the variation of the threshold voltage of the first transistor T1 can be compensated.

From the above, it can be seen that the voltage level of the first voltage signal D1 of the display panel 1400 is adaptively adjusted according to the variation of the threshold voltage of the first transistor T1 . Therefore, even though the first transistors T1 in different regions of the display panel 1400 have different characteristics, the first transistors T1 can still generate the same driving current Idr.

In addition, the second node voltage V2 of the pixel circuit 1410 is adaptively set according to the threshold voltage of the second transistor T2. Therefore, even if the second transistor T2 in different regions of the display panel 1400 has different characteristics, the second transistor T2 can still be turned on at the expected time point in the light emitting phase. In other words, the display panel 1400 can overcome unstable factors in the manufacturing process and provide high-quality display images.

To sum up, the display panels 100, 700, 1100 and 1400 do not use the first driving signal VDD to control the switching operation of the second transistor T2. Therefore, even if the first driving signal VDD produces a voltage drop due to the need to provide a large current to the plurality of light emitting units EU, each second transistor T2 can still be turned on in time during the light emitting phase. In this way, the display panels 100, 700, 1100 and 1400 can provide high-quality display images.

The switches of the pixel circuits in the above-mentioned embodiments can also be realized by various suitable types of N-type transistors. In this case, the enable level of the control signal corresponding to each switch is a high voltage level, and the disable level is a low voltage level.

Certain terms are used in the description and claims to refer to particular elements. However, those skilled in the art should understand that the same element may be called by different terms. The specification and claims do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. The "comprising" mentioned in the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

The description of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term includes the meanings of plural cases at the same time.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

Claims (17)

1. a kind of display panel includes multiple pixel circuits, wherein each pixel circuit includes:

One the first transistor includes a first end, a second end and a control terminal, and wherein the first end of the first transistor is used In receiving one first driving signal, the control terminal of the first transistor is coupled to a first node；

One write circuit is coupled to the first node and a second node, for by one first data-signal be transferred to this first Node, and one second data-signal is transferred to the second node；

One luminescence unit includes a first end and a second end, and wherein the first end of the luminescence unit is coupled to first crystalline substance The second end of body pipe, the second end of the luminescence unit is for receiving one second driving signal；

One first capacitor is coupled between the first node and the first end of the first transistor；And

One control circuit is coupled to the first node and the second node, for according to a LED control signal adjust this second One second node voltage of node, wherein when the second node voltage is lower than a preset voltage value, control circuit output one Reference voltage is to the first node.

2. display panel as described in claim 1, wherein the LED control signal has ramp pulse waveform.

3. display panel as described in claim 1, wherein the control circuit include:

One second transistor includes a first end, a second end and a control terminal, and wherein the first end of the second transistor is used In receiving the reference voltage, the second end of the second transistor is coupled to the first node, the control of the second transistor End is coupled to the second node；And

One second capacitor includes a first end and a second end, and the first end of second capacitor is for receiving the light emitting control The second end of signal, second capacitor is coupled to the second node.

4. display panel as described in claim 1, which includes one first data line and one second data line, wherein The write circuit includes:

One first switch includes a first end, a second end and a control terminal, and wherein the first end of the first switch is coupled to The first node, the second end of the first switch are used to receive first data-signal from first data line；And

One second switch includes a first end, a second end and a control terminal, and wherein the first end of the second switch is coupled to The second node, the second end of the second switch are used to receive second data-signal from second data line；

Wherein the control terminal of the first switch is for receiving a first control signal, and the control terminal of the second switch is for connecing A second control signal is received, so that the first switch and the second switch are sequentially connected.

5. display panel as described in claim 1, which includes one first data line, wherein the write circuit packet Contain:

One first switch includes a first end, a second end and a control terminal, and wherein the first end of the first switch is coupled to The first node, the second end of the first switch are used to receive first data-signal from first data line；And

One second switch includes a first end, a second end and a control terminal, and wherein the first end of the second switch is coupled to The second node, the second end of the second switch are used to receive second data-signal from first data line；

Wherein the control terminal of the first switch and the control terminal of the second switch are for receiving a first control signal.

6. such as display panel described in any one of claim 1 to 5, wherein in a write phase, first driving signal with should Second driving signal is maintained at a first voltage level, and in a light emitting phase, which is maintained at the first voltage Level, which switches to a second voltage level, and the first voltage level is higher than the second voltage level, Or

In the write phase, first driving signal and second driving signal are maintained at the second voltage level, shine in this Stage, first driving signal switch to the first voltage level, which is maintained at the second voltage level, and And the first voltage level is higher than the second voltage level,

Wherein, which has fixed voltage in the write phase, and has ramp pulse wave in the light emitting phase Shape.

7. wherein the display panel additionally comprises a comparison circuit, the picture such as display panel described in any one of claim 1 to 5 Plain circuit additionally comprises:

One third switch, includes a first end, a second end and a control terminal, the second end of third switch be coupled to this The second end of one transistor, the control terminal of third switch control signal for receiving a third；

Wherein the comparison circuit is coupled to the first end of third switch, for receiving the first crystal by third switch The driving current that pipe generates, when the driving current that the comparison circuit receives is not equal to a pre-set current value, this is more electric Road export an adjustment signal, by the voltage level of first data-signal be set as negative about the driving current it is big It is small.

8. a kind of display panel includes multiple pixel circuits, wherein each pixel circuit includes:

One the first transistor includes a first end, a second end and a control terminal, wherein control terminal coupling of the first transistor It is connected to a first node；

One compensation circuit, is coupled to the first end, the second end of the first transistor, and is coupled to the first node, is used for A first node voltage of the first node is adjusted according to the critical voltage of the first transistor and one first data-signal；

One reset circuit, for a reset voltage to be transferred to the first node；

One write circuit, for one second data-signal to be transferred to a second node；

One control circuit is coupled to the first node and the second node, for according to a LED control signal adjust this second One second node voltage of node, wherein when the second node voltage is lower than a preset voltage value, control circuit output one Reference voltage is to the first node；

One first capacitor is coupled between the first node and the compensation circuit；And

One luminescence unit includes a first end and a second end, and wherein the first end of the luminescence unit is coupled to compensation circuit, The second end of the luminescence unit is for receiving one second driving signal.

9. display panel as claimed in claim 8, wherein the LED control signal has ramp pulse waveform.

10. display panel as claimed in claim 8, wherein the control circuit includes:

One second transistor includes a first end, a second end and a control terminal, and wherein the first end of the second transistor is used In receiving the reference voltage, the second end of the second transistor is coupled to the first node, the control of the second transistor End is coupled to the second node；And

One second capacitor includes a first end and a second end, and the first end of second capacitor is for receiving the light emitting control The second end of signal, second capacitor is coupled to the second node.

11. display panel as claimed in claim 8, wherein the compensation circuit includes:

One the 4th switch includes a first end, a second end and a control terminal, and wherein the first end of the 4th switch is for connecing First data-signal is received, the second end of the 4th switch is coupled to the first end of the first transistor, the 4th switch The control terminal for receive one the 4th control signal；

One the 5th switch includes a first end, a second end and a control terminal, and wherein the first end of the 5th switch is coupled to The first node, the second end of the 5th switch are coupled to the second end of the first transistor, the control of the 5th switch End processed is for receiving the 4th control signal；

One the 6th switch includes a first end, a second end and a control terminal, and wherein the first end of the 6th switch is for connecing One first driving signal is received, the second end of the 6th switch is coupled to the first end of the first transistor, the 6th switch The control terminal for receive one the 5th control signal；And

One the 7th switch includes a first end, a second end and a control terminal, and wherein the first end of the 7th switch is coupled to The second end of the first transistor, the second end of the 7th switch are coupled to the first end of the luminescence unit, and the 7th The control terminal of switch is for receiving the 5th control signal.

12. display panel as claimed in claim 11, multiple pixel circuit is arranged in the matrix shape with multiple row, the picture Plain circuit is located at Nth column, and N is positive integer, and wherein the reset circuit includes:

One the 8th switch includes a first end, a second end and a control terminal, and wherein the first end of the 8th switch is coupled to The first node, the second end of the 8th switch is for receiving the reset voltage, and the control terminal of the 8th switch is for connecing Receive the 4th control signal of N-1 column.

13. display panel as claimed in claim 8, wherein the write circuit includes:

One the 9th switch includes a first end, a second end and a control terminal, and wherein the first end of the 9th switch is coupled to The second node, the second end of the 9th switch are used for receiving second data-signal, the control terminal of the 9th switch Signal is controlled in receiving one the 6th.

14. a kind of pixel circuit, includes:

One the first transistor includes a first end, a second end and a control terminal, and wherein the first end of the first transistor is used In receiving one first driving signal, the control terminal of the first transistor is coupled to a first node；

One luminescence unit includes a first end and a second end, and wherein the first end of the luminescence unit is coupled to first crystalline substance The second end of body pipe, the second end of the luminescence unit is for receiving one second driving signal；

One first capacitor is coupled between the first node and the first end of the first transistor；

One second transistor includes a first end, a second end and a control terminal, and wherein the first end of the second transistor is used In receiving a reference voltage, the control terminal of the second transistor is coupled to a second node；

One second capacitor includes a first end and a second end, and the first end of second capacitor is for receiving a light emitting control The second end of signal, second capacitor is coupled to the second node, and wherein the LED control signal has ramp pulse waveform；

One first compensation circuit is coupled to the second end of the first node, the second node and the second transistor, is used for Critical voltage according to the second transistor adjusts a second node voltage of the second node；

One write circuit for one first data-signal to be transferred to the first node, and one second data-signal is transferred to The second node；And

One second compensation circuit, the driving current for generating the first transistor are transferred to a comparison circuit, wherein when The driving current that the comparison circuit receives is not equal to a pre-set current value, which exports an adjustment signal, will The voltage level of first data-signal is set as the size for the driving current being positively correlated with.

15. pixel circuit as claimed in claim 14, wherein first compensation circuit includes:

The tenth switch includes a first end, a second end and a control terminal, and wherein the first end of the tenth switch is for connecing A reset voltage is received, the second end of the tenth switch is coupled to the second node, and the control terminal of the tenth switch is for connecing Receive one the 7th control signal；

1 the 11st switch, include a first end, a second end and a control terminal, wherein the 11st switch the first end coupling It is connected to the second node, the second end of the 11st switch is coupled to the second end of the second transistor, and the 11st opens The control terminal closed is for receiving one the 8th control signal；And

1 the 12nd switch, include a first end, a second end and a control terminal, wherein the 12nd switch the first end coupling It is connected to the second end of the second transistor, the second end of the 12nd switch is coupled to the first node, and the 12nd opens The control terminal closed is for receiving one the 9th control signal.

16. pixel circuit as claimed in claim 14, wherein the write circuit includes:

One third capacitor includes a first end and a second end, and wherein the first end of the third capacitor is coupled to second section Point；

1 the 13rd switch, include a first end, a second end and a control terminal, wherein the 13rd switch the first end coupling It is connected to the first node, the second end of the 13rd switch is somebody's turn to do for receiving first data-signal, the 13rd switch Control terminal is for receiving 1 the tenth control signal；And

1 the 14th switch, include a first end, a second end and a control terminal, wherein the 14th switch the first end coupling It is connected to the second end of the third capacitor, the second end of the 13rd switch is for receiving second data-signal, and the tenth The control terminal of four switches is for receiving 1 the 11st control signal.

17. pixel circuit as claimed in claim 14, wherein second compensation circuit includes:

1 the 15th switch, include a first end, a second end and a control terminal, wherein the 15th switch the first end coupling It is connected to the comparison circuit, the second end of the 15th switch is coupled to the second end of the first transistor, and the 15th opens The control terminal closed is for receiving 1 the 12nd control signal.