CN110071069A - Show backboard and preparation method thereof - Google Patents

Abstract

The present disclosure provides a display backplane and a manufacturing method thereof. The manufacturing method of the display backplane includes providing a substrate, forming a transparent metal layer on the substrate, forming a black matrix photoresist layer on the transparent metal layer, patterning the black matrix photoresist layer to partially cover the the transparent metal layer, a buffer layer is formed on the substrate, the transparent metal layer and the black matrix photoresist layer, and a transparent oxide semiconductor layer is formed on the buffer layer. The area where the transparent metal layer is covered by the black matrix photoresist layer is defined as the driving thin film transistor area, and the area where the transparent metal layer is not covered by the black matrix photoresist layer is defined as the storage capacitor area. The present disclosure can avoid the internal light reflection of the display backplane and improve the aperture ratio.

Description

Display backplane and method of making the same

【Technical field】

The present disclosure relates to the field of display technology, and in particular, to a display backplane and a manufacturing method thereof.

【Background technique】

At present, the light-shielding metal layer of the display backplane can block part of the incident light, but the internal reflected light still affects the display backplane. In addition, since the electrode of the storage capacitor is made of metal, the pixel light-emitting area and aperture ratio of the display backplane are reduced.

Therefore, there is a need to provide a display backplane and a manufacturing method thereof to solve the problems existing in the prior art.

[Content of the invention]

In order to solve the above technical problems, an object of the present disclosure is to provide a display backplane and a manufacturing method thereof, which can avoid internal light reflection of the display backplane and improve the aperture ratio.

In order to achieve the above object, the present disclosure provides a method for manufacturing a display backplane, including providing a substrate, forming a transparent metal layer on the substrate, forming a black matrix photoresist layer on the transparent metal layer, and patterning the black matrix A photoresist layer to partially cover the transparent metal layer, a buffer layer is formed on the substrate, the transparent metal layer and the black matrix photoresist layer, and a transparent oxide semiconductor layer is formed on the buffer layer. The area where the transparent metal layer is covered by the black matrix photoresist layer is defined as the driving thin film transistor area, and the area where the transparent metal layer is not covered by the black matrix photoresist layer is defined as the storage capacitor area.

In one embodiment of the present disclosure, the transparent metal layer in the storage capacitor region is the lower electrode of the storage capacitor, and the transparent oxide semiconductor layer in the storage capacitor region is the storage capacitor the upper electrode.

In one embodiment of the present disclosure, the transparent metal layer, the buffer layer and the transparent oxide semiconductor layer in the storage capacitor region constitute a storage capacitor.

In one embodiment of the present disclosure, the method further includes sequentially forming a gate insulating layer and a first metal layer on the transparent oxide semiconductor layer.

In one embodiment of the present disclosure, the method further includes forming an interlayer dielectric insulating layer on the buffer layer, the transparent oxide semiconductor layer, the gate insulating layer and the first metal layer and patterning the interlayer dielectric insulating layer to form a plurality of via holes, the via holes passing through the interlayer dielectric insulating layer.

In one embodiment of the present disclosure, the method further includes forming a source electrode and a drain electrode on the transparent oxide semiconductor layer, and the source electrode and the drain electrode are connected to the transparent oxide through corresponding via holes. edge contact of the material semiconductor layer.

In one embodiment of the present disclosure, the method further includes sequentially forming a protective layer, a planarization layer, a transparent electrode layer and a pixel definition layer on the interlayer dielectric insulating layer, the source electrode and the drain electrode. and patterning the protective layer and the flat layer to form a contact hole through which the transparent electrode layer is in contact with the source electrode or the drain electrode.

The present disclosure also provides a display backplane including a substrate, a transparent metal layer, a black matrix photoresist layer, a buffer layer and a transparent oxide semiconductor layer. The transparent metal layer is disposed on the substrate. The black matrix photoresist layer is disposed on the transparent metal layer. The buffer layer is disposed on the substrate, the transparent metal layer and the black matrix photoresist layer. The transparent oxide semiconductor layer is provided on the buffer layer. The black matrix photoresist layer partially covers the transparent metal layer, and the region where the transparent metal layer is covered by the black matrix photoresist layer is defined as the driving thin film transistor region, and is not covered by the black matrix photoresist layer The area where the transparent metal layer is located is defined as the storage capacitor area.

In one embodiment of the present disclosure, the transparent metal layer in the storage capacitor region is the lower electrode of the storage capacitor, and the transparent oxide semiconductor layer in the storage capacitor region is the storage capacitor The upper electrode of the storage capacitor, the transparent metal layer, the buffer layer and the transparent oxide semiconductor layer in the storage capacitor region constitute the storage capacitor.

In one embodiment of the present disclosure, the display backplane further includes a gate insulating layer, a first metal layer, an interlayer dielectric insulating layer, a source electrode and a drain, which are sequentially arranged on the transparent oxide semiconductor layer. electrode, protective layer, flat layer, transparent electrode layer and pixel definition layer, wherein the interlayer dielectric insulating layer includes a plurality of via holes, and the source electrode and the drain electrode communicate with the transparent oxide through the corresponding via holes The protective layer and the flat layer include contact holes, and the transparent electrode layer is in contact with the source electrode or the drain electrode through the contact holes.

Due to the display backplane and the manufacturing method thereof in the embodiments of the present disclosure, the black matrix photoresist layer partially covers the transparent metal layer, and the area where the transparent metal layer covered by the black matrix photoresist layer is defined is defined In order to drive the thin film transistor region, the region where the transparent metal layer is not covered by the black matrix photoresist layer is defined as a storage capacitor region. The black matrix photoresist layer is used as a light-shielding layer, which can avoid the reflection of the internal light of the display backplane and reduce the parasitic capacitive coupling phenomenon caused by the conventional light-shielding metal layer. The upper and lower electrodes of the storage capacitor are made of transparent materials to increase the pixel light-emitting area and aperture ratio of the display backplane.

In order to make the above-mentioned content of the present disclosure more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings:

【Description of drawings】

FIG. 1 shows a flowchart of a method for fabricating a display backplane according to an embodiment of the present disclosure; and

FIG. 2 is a schematic structural diagram of a display backplane according to an embodiment of the present disclosure.

【Detailed ways】

In order to make the above-mentioned and other objects, features, and advantages of the present disclosure more clearly understood, the preferred embodiments of the present disclosure will be exemplified below, and will be described in detail in conjunction with the accompanying drawings. Furthermore, the directional terms mentioned in the present disclosure, such as upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial , radial, uppermost or lowermost, etc., only refer to the directions of the attached drawings. Accordingly, the directional terms used are used to describe and understand the present disclosure, rather than to limit the present disclosure.

In the figures, structurally similar elements are denoted by the same reference numerals.

Referring to FIG. 1 , an embodiment of the present disclosure provides a manufacturing method 100 of a display backplane, which includes the following steps.

Referring to FIG. 1 and FIG. 2 , in step 1, a substrate 110 is provided.

Specifically, the substrate 110 is, for example, a glass substrate. The method of providing the glass substrate further includes cleaning and baking the glass substrate.

Step 2 , forming a transparent metal layer 120 on the substrate 110 .

Specifically, the material of the transparent metal layer 120 includes, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

Step 3 , forming a black matrix (BM) photoresist layer 130 on the transparent metal layer 120 .

Step 4, patterning the black matrix photoresist layer 130 to partially cover the transparent metal layer 120. The area where the transparent metal layer 120 is covered by the black matrix photoresist layer 130 is defined as the driving thin film transistor area 10, and the area where the transparent metal layer 120 is not covered by the black matrix photoresist layer 130 is defined It is the storage capacitor region 20 .

Specifically, after coating the entire black matrix photoresist layer 130, use a black matrix halftone mask to expose the black matrix photoresist layer 130 to define the driving thin film transistor region 10 and all the The storage capacitor region 20 is described. In one embodiment, the black matrix photoresist layer 130 of the driving TFT region 10 is thicker, and the black matrix photoresist layer 130 of the storage capacitor region 20 is thinner. In another embodiment, the driving thin film transistor region 10 has the black matrix photoresist layer 130 , and the storage capacitor region 20 does not have the black matrix photoresist layer 130 .

Specifically, etching the transparent metal layer 120 and performing an ashing process of the black matrix photoresist layer 130 to form the black matrix photoresist layer 130 and the black matrix photoresist layer 130 in the driving thin film transistor region 105 A transparent metal layer 120 is formed, and the transparent metal layer 120 is formed in the storage capacitor region 20 .

Specifically, the transparent metal layer 120 in the storage capacitor region 20 is the lower electrode of the storage capacitor.

Step 5 , forming a buffer layer 140 on the substrate 110 , the transparent metal layer 120 and the black matrix photoresist layer 130 .

Specifically, the material of the buffer layer 140 may be silicon dioxide (SiO 2 ) or other materials.

Step 6 , forming a transparent oxide semiconductor layer 150 on the buffer layer 140 .

Specifically, the material of the transparent oxide semiconductor layer 150 may be indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). The transparent oxide semiconductor layer 150 defines an active region and an upper electrode of the storage capacitor. Specifically, the transparent oxide semiconductor layer 150 in the storage capacitor region 20 is the upper electrode of the storage capacitor. The transparent metal layer 120 , the buffer layer 140 and the transparent oxide semiconductor layer 150 in the storage capacitor region 20 constitute a storage capacitor.

Referring to FIG. 2 , in step 7 , a gate insulating layer 160 and a first metal layer 170 are sequentially formed on the transparent oxide semiconductor layer 150 .

Specifically, the gate insulating layer 160 may be a single-layer SiNx film, a single-layer SiO2 film or a double-layer film. The material of the bilayer film may include at least one of SiNx and SiO2.

Specifically, the material of the first metal layer 170 may include Mo, Al or Cu, and the first metal layer 170 defines the gate of an oxide thin film transistor (TFT). The oxide thin film transistor (TFT) includes a driving thin film transistor and a switching thin film transistor. The driving thin film transistor is located in the driving thin film transistor region 10 . The switching thin film transistor is located in the switching thin film transistor region 30 . In one embodiment, the driving TFT region 10 is located between the storage capacitor region 20 and the switching TFT region 30 . The first metal layer 170 defines the gate of the driving thin film crystal. The first metal layer 170 defines the gate of the switching thin film transistor.

Step 8. Form an interlayer dielectric insulating layer 180 on the buffer layer 140 , the transparent oxide semiconductor layer 150 , the gate insulating layer 160 and the first metal layer 170 and pattern the interlayers The dielectric insulating layer 180 is formed to form a plurality of via holes 182 , the via holes 182 passing through the interlayer dielectric insulating layer 180 .

Step 9. Form a source electrode 192 and a drain electrode 194 on the transparent oxide semiconductor layer 150. The source electrode 192 and the drain electrode 194 are connected to the edge of the transparent oxide semiconductor layer 150 through the corresponding via hole 182. touch.

Step 10. Form a protective layer 210, a flat layer 220, a transparent electrode layer 230 and a pixel definition layer 240 on the interlayer dielectric insulating layer 180, the source electrode 192 and the drain electrode 194 in sequence, and pattern the The protective layer 210 and the flat layer 220 are formed to form a contact hole 212 through which the transparent electrode layer 230 is in contact with the source electrode 192 or the drain electrode 194 .

Specifically, the interlayer dielectric insulating layer 180 may be a single-layer SiNx or a single-layer SiO2. Materials of the source electrode 192 and the drain electrode 194 may include Mo, Al or Cu. The source electrode 192 and the drain electrode 194 define the source electrode and the drain electrode of the driving thin film crystal. The source electrode 192 and the drain electrode 194 define the source electrode and the drain electrode of the switching thin film transistor. The material of the transparent electrode layer 230 may include ITO.

Specifically, the display backplane may be an organic light emitting diode (OLED) backplane. The display backplane may be a liquid crystal display (LCD) backplane.

The display backplane includes a substrate 110 , a transparent metal layer 120 , a black matrix photoresist layer 130 , a buffer layer 140 and a transparent oxide semiconductor layer 150 . The transparent metal layer 120 is disposed on the substrate 110 . The black matrix photoresist layer 130 is disposed on the transparent metal layer 120 . The buffer layer 140 is disposed on the substrate 110 , the transparent metal layer 120 and the black matrix photoresist layer 130 . The transparent oxide semiconductor layer 150 is disposed on the buffer layer 140 . The black matrix photoresist layer 130 partially covers the transparent metal layer 120, and the region where the transparent metal layer 120 is covered by the black matrix photoresist layer 130 is defined as the driving thin film transistor region 10, which is not covered by the black matrix photoresist layer 130. The area where the transparent metal layer 120 is covered by the matrix photoresist layer 130 is defined as the storage capacitor area 20 .

In one embodiment of the present disclosure, the transparent metal layer 120 in the storage capacitor region 20 is the lower electrode of the storage capacitor, and the transparent oxide semiconductor layer 120 in the storage capacitor region 20 is The upper electrode of the storage capacitor, the transparent metal layer 120 , the buffer layer 140 and the transparent oxide semiconductor layer 120 in the storage capacitor region 20 constitute the storage capacitor.

In one embodiment of the present disclosure, the display backplane further includes a gate insulating layer 160, a first metal layer 170, an interlayer dielectric insulating layer 180, The source electrode 192 and the drain electrode 194 , the protective layer 210 , the planarization layer 220 , the transparent electrode layer 230 and the pixel definition layer 240 . The interlayer dielectric insulating layer 180 includes a plurality of via holes 182, the source electrode 192 and the drain electrode 194 are in contact with the edge of the transparent oxide semiconductor layer 120 through the corresponding via holes 182, and the protective layer 210 and the flat layer 220 include contact holes 212 through which the transparent electrode layer 230 is in contact with the source electrode 192 or the drain electrode 194 .

Due to the display backplane and the manufacturing method thereof in the embodiments of the present disclosure, the black matrix photoresist layer partially covers the transparent metal layer, and the area where the transparent metal layer covered by the black matrix photoresist layer is defined is defined In order to drive the thin film transistor region, the region where the transparent metal layer is not covered by the black matrix photoresist layer is defined as a storage capacitor region. The black matrix photoresist layer is used as a light-shielding layer, which can avoid the reflection of the internal light of the display backplane and reduce the parasitic capacitive coupling phenomenon caused by the conventional light-shielding metal layer. The upper and lower electrodes of the storage capacitor are made of transparent materials to increase the pixel light-emitting area and aperture ratio of the display backplane.

While the disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the appended claims. In particular with respect to the various functions performed by the above-described components, the terms used to describe such components are intended to correspond to any component that performs the specified function of the component (eg, which is functionally equivalent) (eg, which is functionally equivalent) (unless otherwise indicated) , even if it is not structurally equivalent to the disclosed structure that performs the functions of the exemplary implementations of the specification shown herein. Furthermore, although a particular feature of this specification has been disclosed with respect to only one of several implementations, such feature may be combined with one or more of the other implementations as may be desired and advantageous for a given or particular application Other feature combinations. Also, to the extent that the terms "including," "having," "containing," or variations thereof, are used in the detailed description or the claims, such terms are intended to include in a manner similar to the term "comprising."

The above are only the preferred embodiments of the present disclosure. It should be pointed out that for those skilled in the art, on the premise of not departing from the principles of the present disclosure, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as the present disclosure. protected range.

Claims (10)

1. a kind of production method for showing backboard characterized by comprising

Substrate is provided；

Transparent metal layer is formed on the substrate；

Black matrix" photoresist layer is formed on the transparent metal layer；

The black matrix" photoresist layer is patterned, partially to cover the transparent metal layer, wherein by the black matrix" photoresist Region where the transparent metal layer of layer covering is defined as driving TFT regions, not by the black matrix" light Region where the transparent metal layer of resistance layer covering is defined as storage capacitors region；

Buffer layer is formed on the substrate, the transparent metal layer and the black matrix" photoresist layer；And

Transparent oxide semiconductor layer is formed on the buffer layer.

2. the production method of display backboard as described in claim 1, which is characterized in that the institute in the storage capacitors region The lower electrode that transparent metal layer is storage capacitors is stated, the transparent oxide semiconductor layer in the storage capacitors region is The top electrode of the storage capacitors.

3. the production method of display backboard as described in claim 1, which is characterized in that the institute in the storage capacitors region It states transparent metal layer, the buffer layer and the transparent oxide semiconductor layer and constitutes storage capacitors.

4. the production method of display backboard as described in claim 1, which is characterized in that further include in the transparent oxide half Gate insulating layer and the first metal layer are sequentially formed in conductor layer.

5. the production method of display backboard as claimed in claim 4, which is characterized in that further include in the buffer layer, described Interlayer dielectric insulation layer and pattern are formed on transparent oxide semiconductor layer, the gate insulating layer and the first metal layer Change the interlayer dielectric insulating layer to form multiple via holes, the via hole runs through the interlayer dielectric insulating layer.

6. the production method of display backboard as claimed in claim 5, which is characterized in that further include in the transparent oxide half Source electrode and drain electrode, the source electrode and the drain electrode are formed in conductor layer passes through corresponding via hole and the transparent Indium The EDGE CONTACT of object semiconductor layer.

7. the production method of display backboard as claimed in claim 6, which is characterized in that further include insulating in the interlayer dielectric Protective layer, flatness layer, transparent electrode layer and pixel defining layer and figure are sequentially formed on layer, the source electrode and the drain electrode To form contact hole, the transparent electrode layer passes through the contact hole and source electricity for protective layer described in case and the flatness layer Pole or drain electrode contact.

8. a kind of display backboard characterized by comprising

Substrate；

Transparent metal layer, setting is on the substrate；

Black matrix" photoresist layer is arranged on the transparent metal layer；

Buffer layer is arranged on the substrate, the transparent metal layer and the black matrix" photoresist layer；And

Transparent oxide semiconductor layer is arranged on the buffer layer；

Wherein black matrix" photoresist layer part covers the transparent metal layer, the institute covered by the black matrix" photoresist layer Region where stating transparent metal layer is defined as driving TFT regions, is not covered by the black matrix" photoresist layer Region where the transparent metal layer is defined as storage capacitors region.

9. display backboard as claimed in claim 8, which is characterized in that the transparent metal in the storage capacitors region Layer is the lower electrode of storage capacitors, and the transparent oxide semiconductor layer in the storage capacitors region is the storage electricity The top electrode of appearance, the transparent metal layer, the buffer layer and the transparent oxide half in the storage capacitors region Conductor layer constitutes the storage capacitors.

10. display backboard as claimed in claim 8, which is characterized in that further include being successively set on the transparent oxide half Gate insulating layer, the first metal layer, interlayer dielectric insulating layer, source electrode and drain electrode, protective layer, flatness layer in conductor layer, Transparent electrode layer and pixel defining layer, wherein the interlayer dielectric insulating layer includes multiple via holes, the source electrode and the leakage Electrode passes through the EDGE CONTACT of corresponding via hole and the transparent oxide semiconductor layer, the protective layer and the flatness layer packet Contact hole is included, the transparent electrode layer is contacted by the contact hole with the source electrode or the drain electrode.