CN110018791B - SSD SOC-based power consumption management control method and system - Google Patents
SSD SOC-based power consumption management control method and system Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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Abstract
The application relates to a power consumption management control method, a system, computer equipment and a storage medium based on an SSD SOC, wherein the system comprises: a controller register for configuring a register inside a controller through a slave bus configuration port; the controller control center is used for obtaining instruction codes from an external SRAM through a main bus to operate and generating low-power consumption processing signals, or generating the low-power consumption processing signals according to the configuration of a slave bus; and the low-power consumption processing module is used for receiving the low-power consumption processing signal sent by the controller control center and performing low-power consumption processing. The invention releases the CPU by adopting the independent power consumption management controller, has high flexibility, small area, low power consumption and high processing speed, and can replace the CPU to carry out low-power consumption processing.
Description
Technical Field
The invention relates to the technical field of solid state disks, in particular to a power consumption management control method and system based on an SSD SOC, a computer device and a storage medium.
Background
At present, in the application of the SSD SOC with low power consumption, different power consumption requirements are applied in different scenarios, and in order to meet the requirements, a speed reduction or a module shutdown is generally adopted, which requires a separate low power consumption design.
In the conventional technology, a CPU is usually adopted to do these things, the CPU cannot be turned off, and in addition, since the CPU is usually used for processing complex tasks, the area is large, the power consumption is high, and the cost is also high.
Disclosure of Invention
In view of the above, it is necessary to provide a power consumption management control method, system, computer device, and storage medium based on the SSD SOC, which can realize low power consumption processing instead of the CPU.
A power consumption management control system based on an SSD SOC is characterized by comprising:
a controller register for configuring a register inside a controller by configuring a port from a bus;
the controller control center is used for obtaining instruction codes from an external SRAM through a main bus to operate and generating low-power consumption processing signals, or generating the low-power consumption processing signals according to the configuration of a slave bus;
and the low-power-consumption processing module is used for receiving the low-power-consumption processing signal sent by the controller control center and performing low-power-consumption processing.
In one embodiment, the low power processing module is further configured to:
receiving a low power consumption signal generated by a slave bus configuration via a controller register;
receiving a low-power consumption signal generated by the operation of a main bus instruction fetching code;
and generating an interrupt to an external CPU according to the low power consumption signal.
In one embodiment, the system further comprises:
a debounce signal module, the debounce signal module configured to receive a low power consumption related signal, the debounce signal passing through debounce logic;
the I2C main module is used for generating an I2C main signal to control an external chip.
In one embodiment, the system further comprises:
a master bus state machine to generate control logic for a master bus.
In one embodiment, the controller register is further configured to:
configuring a register inside the controller through the slave bus configuration port; the configured content comprises low-power signal interrupt control, debounce signal module setting and I2C main module setting;
the slave bus may be accessed through the master bus of the power management controller or may be accessed from the outside.
In one embodiment, the controller control center is further configured to:
receiving a signal generated by the debounce signal module;
an I2C master signal is generated and sent to the I2C master module.
A power consumption management control method based on an SSD SOC is applied to any one of the power consumption management control systems based on the SSD SOC, and the method comprises the following steps:
acquiring a power consumption management control request based on the SSD SOC;
according to the power consumption management control request based on the SSD SOC, a low power consumption processing signal is generated by fetching an instruction code from an external SRAM through a main bus;
and performing low-power consumption processing according to the low-power consumption processing signal through a low-power consumption processing module.
In one embodiment, after the step of obtaining the SSD SOC-based power consumption management control request, the method further includes:
according to the power consumption management control request based on the SSD SOC, a register inside a controller is configured through a slave bus configuration port;
generating a low power consumption processing signal according to the configuration of the slave bus;
and performing low-power consumption processing according to the low-power consumption processing signal through a low-power consumption processing module.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
According to the power consumption management control method, the system, the computer equipment and the storage medium based on the SSD SOC, an independent power consumption management control system is designed to replace a CPU to perform some configuration operations, and low power consumption signals of an SSD main control chip can be received to perform power-off or power-on operations; and the external SRAM (static random access memory) can be used for storing self-defined instruction codes for necessary treatment before power-off or power-on. The power consumption management control system can replace a CPU to perform low power consumption processing, improves the flexibility of power consumption management of the SSD SOC, and is smaller in area, low in power consumption and higher in processing speed.
Drawings
FIG. 1 is a block diagram of a SSD SOC based power management control system in one embodiment;
FIG. 2 is a block diagram of another embodiment of a SSD SOC based power management control system;
FIG. 3 is a block diagram of a power management control system based on SSD SOC in yet another embodiment;
FIG. 4 is a diagram illustrating an overall structure of an SSD SOC power management controller system in one embodiment;
FIG. 5 is a flow chart illustrating a power management control method based on SSD SOC in one embodiment;
FIG. 6 is a flow chart illustrating a power management control method based on SSD SOC in another embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
In the conventional technology, in the application of low power consumption of the SSD SOC, there is a power consumption requirement in different scenarios, and in order to meet the requirement, a speed reduction is generally adopted, or the power supply of the module is turned off (a separate low power consumption design is required). Traditionally, a CPU is adopted to do the things, the CPU cannot be closed, the CPU is used for processing complex tasks, the area is large, and the power consumption is high.
The invention provides a power consumption management control method and a power consumption management control system based on an SSD (solid State disk) SOC (System on chip). By adopting an independent power consumption management controller, a CPU (Central processing Unit) is released, the flexibility is high, the area is small, the power consumption of the system is low, the processing speed is high, and the system can replace the CPU to perform low-power-consumption processing.
In one embodiment, as shown in fig. 1, there is provided a power consumption management control system 100 based on an SSD SOC, the system comprising:
a controller register 101 for configuring a register inside the controller through the slave bus configuration port;
the controller control center 102 is used for obtaining instruction codes from an external SRAM through a main bus to operate and generating a low-power consumption processing signal, or generating the low-power consumption processing signal according to the configuration of a slave bus;
and the low-power consumption processing module 103 is used for receiving the low-power consumption processing signal sent by the controller control center and performing low-power consumption processing.
In one embodiment, the low power processing module 103 is further configured to:
receiving a low power consumption signal generated by a slave bus configuration via a controller register;
receiving a low-power consumption signal generated by the operation of a main bus instruction fetching code;
an interrupt is generated to an external CPU based on the low power consumption signal.
Specifically, referring to fig. 4 in combination, in this embodiment, the controller register slave AHB configures the port, which may be specifically used to configure a register inside the controller. The details of the configuration mainly relate to low power consumption related signals, interrupt control, setting of debounce module and setting of I2C.
The controller controls the control center to fetch instruction codes from the external SRAM through the main bus to operate, and a low-power consumption processing signal is generated; the slave bus configuration may also be received, resulting in a signal for low power consumption processing.
And receiving a signal related to low power consumption, and generating an interrupt to an external CPU. Specifically, a low power consumption related signal generated by the slave bus configuration via the controller register may be received, and a low power consumption related signal generated by the master bus instruction fetch operation may also be received.
In this embodiment, the power consumption management control system may replace a CPU to perform some configuration operations, and may also receive some low power consumption signals of the SSD main control chip for power-down or power-up operations; and the external SRAM (static random access memory) can be used for storing self-defined instruction codes for necessary treatment before power-off or power-on. The embodiment also realizes the release of the CPU by the low-power consumption processing flow. In addition, in the embodiment, an AHB (advanced high performance bus) bus package is adopted, so that parameters can be configured, the integration level is high, and the performance is high.
In one embodiment, as shown in fig. 2, there is provided a power consumption management control system 100 based on an SSD SOC, the system further comprising:
a debounce signal module 104, configured to receive the low power consumption related signal, and pass through debounce logic;
and an I2C master module 105 for generating an I2C master signal to control the external chip.
In one embodiment, as shown in fig. 3, there is provided a power consumption management control system 100 based on an SSD SOC, the system further comprising:
a master bus state machine 106 for generating control logic for the master bus.
In one embodiment, controller register 101 is also used to:
configuring a register inside the controller through the slave bus configuration port; the configured content comprises low-power signal interruption control, debounce signal module setting and I2C main module setting;
the slave bus may be accessed through the master bus of the power management controller or may be accessed from the outside.
In one embodiment, the controller control center 102 is further configured to:
receiving a signal generated by the debounce signal module 104;
generates an I2C master signal and sends the I2C master signal to I2C master module 105.
Specifically, referring to fig. 4, a block diagram of an overall design module and a data flow diagram are shown, and the overall design module mainly includes the following modules:
a controller register: the slave AHB configuration port is used for configuring a register inside the controller; mainly related to signals related to low power consumption, interrupt control, setting of a debounce module and setting of I2C; the slave bus may be accessed through the master bus of the power management controller or may be accessed externally.
The controller controls the control center: receiving a signal generated by a debounce module; generating a main I2C signal; the command code is fetched from an external SRAM through a main bus to run, and a signal processed by low power consumption is generated; the slave bus configuration may also be received, resulting in a signal for low power consumption processing.
The low-power consumption processing module: receiving a signal related to low power consumption, and generating an interrupt to an external CPU; receiving a signal related to low power consumption generated by a slave bus configuration through a controller register; and receiving a low-power consumption related signal generated by the operation of the main bus instruction fetching code.
A debounce signal module: a low power consumption related signal is received through debounce logic.
I2C master: an I2C master signal is generated for controlling an external, e.g. power chip.
A main bus state machine: control logic for generating the main bus AHB.
Wherein, the instruction code structure of controller control center includes two kinds of instruction code structures: a 32Bit instruction +32Bit operand/32 Bit instruction. Supported instructions: no operation/move/read/write/compute instructions: and/or/not/wait instruction/predicate jump instruction, etc.
In one embodiment, as shown in fig. 5, there is provided a power consumption management control method based on SSD SOC, which is applied to the power consumption management control system based on SSD SOC in the above embodiments, and the method includes:
step 502, acquiring a power consumption management control request based on the SSD SOC;
step 504, according to the power consumption management control request based on the SSD SOC, obtaining an instruction code from an external SRAM through a main bus to operate and generating a low power consumption processing signal;
and step 506, performing low power consumption processing by the low power consumption processing module according to the low power consumption processing signal.
In this embodiment, the subsequent may not require CPU-specific details except for initial initialization. Specifically, first, the CPU initializes the SRAM for storing an instruction externally, which mainly relates to a power-on processing flow and a power-off processing flow. Then, waiting for an external power-on/power-off signal or a configuration start signal, the power consumption management controller sends an external SRAM instruction, and starts to process a relevant flow until the processing is completed.
In one embodiment, as shown in fig. 6, a power consumption management control method based on the SSD SOC is provided, and after the step of obtaining the power consumption management control request based on the SSD SOC, the method further includes:
step 602, configuring a register inside a controller through a slave bus configuration port according to a power consumption management control request based on the SSD SOC;
step 604, generating a low power consumption processing signal according to the configuration of the slave bus;
and 606, performing low power consumption processing according to the low power consumption processing signal through the low power consumption processing module.
In this embodiment, no external instruction SRAM is required, but the CPU is relied upon. Specifically, first, the CPU receives an interrupt generated by a low power consumption signal. And then, judging according to the received interrupt signal, configuring relevant PMU settings, and starting a power-on/power-off process.
For specific limitations of the power consumption management control method based on the SSD SOC, see the above limitations on the power consumption management control system based on the SSD SOC, which are not described herein again.
It should be understood that although the various steps in the flowcharts of fig. 5-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 5-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 7. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a power consumption management control method based on the SSD SOC.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (7)
1. A power consumption management control method based on an SSD SOC is applied to a power consumption management control system based on the SSD SOC, and is characterized by comprising the following steps:
acquiring a power consumption management control request based on the SSD SOC;
according to the SSD SOC-based power consumption management control request, a low power consumption processing signal is generated by the operation of fetching an instruction code from an external SRAM through a main bus;
performing low-power consumption processing according to the low-power consumption processing signal through a low-power consumption processing module;
after the step of obtaining the power consumption management control request based on the SSD SOC, the method further comprises the following steps:
according to the power consumption management control request based on the SSD SOC, a register inside a controller is configured through a slave bus configuration port;
generating a low power consumption processing signal according to the configuration of the slave bus;
performing low-power consumption processing according to the low-power consumption processing signal through a low-power consumption processing module;
the SSD SOC-based power consumption management control system comprises:
a controller register for configuring a register inside a controller by configuring a port from a bus;
the controller control center is used for obtaining instruction codes from an external SRAM through a main bus to operate and generating low-power consumption processing signals, or generating the low-power consumption processing signals according to the configuration of a slave bus;
the low-power consumption processing module is used for receiving a low-power consumption processing signal sent by the controller control center and performing low-power consumption processing;
the low power consumption processing module is further configured to: receiving a low power consumption signal generated by a slave bus configuration via a controller register; receiving a low-power consumption signal generated by the operation of a main bus instruction fetching code; and generating an interrupt to an external CPU according to the low power consumption signal.
2. The SSD SOC based power consumption management control method of claim 1, wherein the SSD SOC based power consumption management control system further comprises:
a debounce signal module, the debounce signal module configured to receive a low power consumption related signal, the debounce signal passing through debounce logic;
the I2C main module is used for generating an I2C main signal to control an external chip.
3. The SSD SOC based power consumption management control method of claim 2, wherein the system further comprises:
a master bus state machine to generate control logic for a master bus.
4. The SSD SOC-based power management control method of claim 3, wherein the controller register is further configured to:
configuring a register inside the controller through the slave bus configuration port; the configured content comprises low-power signal interruption control, debounce signal module setting and I2C main module setting;
the slave bus may be accessed through the master bus of the power management controller or may be accessed from the outside.
5. The SSD SOC-based power management control method of claim 4, wherein the controller control center is further configured to:
receiving a signal generated by the debounce signal module;
an I2C master signal is generated and sent to the I2C master module.
6. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1-5 are implemented when the computer program is executed by the processor.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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| CN110401939B (en) * | 2019-09-04 | 2023-03-24 | 大唐半导体科技有限公司 | Low-power consumption bluetooth controller link layer device |
| CN111077975B (en) * | 2019-12-17 | 2021-07-13 | 深圳忆联信息系统有限公司 | Method and device for reducing Power State3 Power consumption of SSD, computer equipment and storage medium |
| CN113325998B (en) * | 2020-02-29 | 2022-09-06 | 杭州海康存储科技有限公司 | Read-write speed control method and device |
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