CN110008155B - Electronic device and operation method thereof - Google Patents

Abstract

An electronic device is provided. The electronic device includes a first integrated circuit and a second integrated circuit. The direction pin of the first integrated circuit outputs a direction control signal to the direction pin of the second integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit obtains the control right. When the first integrated circuit obtains the control right, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit. When the direction control signal is in the second logic state, the second integrated circuit obtains the control right. When the second IC obtains the control right, the frequency pin of the second IC outputs the second frequency signal to the frequency pin of the first IC.

Description

Electronic device and method of operation thereof

field of invention

The invention relates to an electronic device and an operating method thereof.

Background technique

When cooperating between two integrated circuits, in addition to data transmission pins, additional control pins are required to transmit specific control signals. Generally speaking, the greater the number of pins, the higher the manufacturing cost of the integrated circuit. In addition, in the process of cooperative operation between two integrated circuits, one of the integrated circuits acts as a "master" (master control terminal), while the other integrated circuit acts as a "slave (slave)" role (controlled end). In the known technology, master and slave are fixed. For example, in the master-slave architecture, integrated circuit A acts as a "master" role (master), and integrated circuit B acts as a "slave (slave)" role (controlled end). The frequency signal required for synchronous operation is fixedly provided by the integrated circuit A, and the integrated circuit B receives the frequency signal of the integrated circuit A for coordinated operation. IC B cannot change from slave to master.

Contents of the invention

The invention provides an electronic device and its operation method, which can dynamically switch the control right to one of the first integrated circuit and the second integrated circuit according to the operation requirement.

An embodiment of the invention provides an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The first integrated circuit has at least a direction pin and a frequency pin, wherein the direction pin of the first integrated circuit outputs a direction control signal. The second integrated circuit has at least a direction pin and a frequency pin. The direction pin of the second integrated circuit is coupled to the direction pin of the first integrated circuit to receive the direction control signal. The clock pin of the second integrated circuit is coupled to the clock pin of the first integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit takes control. When the first integrated circuit takes control, the frequency pin of the first integrated circuit outputs the first frequency signal to the frequency pin of the second integrated circuit. When the direction control signal is in the second logic state, the second integrated circuit takes control. When the second integrated circuit takes control, the frequency pin of the second integrated circuit outputs a second frequency signal to the frequency pin of the first integrated circuit.

An embodiment of the invention provides an operating method of an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The operation method includes: outputting a direction control signal from the direction pin of the first integrated circuit to the direction pin of the second integrated circuit; when the direction control signal is in the first logic state, the first integrated circuit obtains the control right; When the first integrated circuit obtains the control right, the frequency pin of the first integrated circuit outputs the first frequency signal to the frequency pin of the second integrated circuit; when the direction control signal is in the second logic state, the second integrated circuit obtains control and when the second integrated circuit obtains the control right, the frequency pin of the second integrated circuit outputs a second frequency signal to the frequency pin of the first integrated circuit.

Based on the above, the electronic device and its operating method according to the embodiments of the present invention can dynamically switch the control right to one of the first integrated circuit and the second integrated circuit through the direction control signal. When the first integrated circuit takes control, the first integrated circuit can output the first frequency signal to the second integrated circuit. When the second integrated circuit takes control, the second integrated circuit can output the second frequency signal to the first integrated circuit.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a circuit block of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of an operating method of an electronic device according to an embodiment of the invention.

FIG. 3 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to an embodiment of the present invention.

FIG. 4 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention.

FIG. 6 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention.

Detailed ways

As used throughout the present specification, including the claims, the term "coupled (or connected)" may refer to any means of connection, direct or indirect. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. In addition, wherever possible, components/members/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

FIG. 1 is a schematic diagram of a circuit block of an electronic device 100 according to an embodiment of the present invention. The electronic device 100 includes a first integrated circuit 110 and a second integrated circuit 120 . The first integrated circuit 110 has at least a direction pin DR, a frequency pin CK, a first data pin D1 and a second data pin D2. The second integrated circuit 120 has at least a direction pin DR, a frequency pin CK, a first data pin D1 and a second data pin D2. According to design requirements, the first integrated circuit 110 may also be configured with other pins, and the second integrated circuit 120 may also be configured with other pins.

The direction pin DR of the first integrated circuit 110 outputs a direction control signal DIR. The direction pin DR of the second integrated circuit 120 is coupled to the direction pin DR of the first integrated circuit 110 to receive the direction control signal DIR. The clock pin CK of the second integrated circuit 120 is coupled to the clock pin CK of the first integrated circuit 110 . The first data pin D1 of the second integrated circuit 120 is coupled to the first data pin D1 of the first integrated circuit 110 . The second data pin D2 of the second integrated circuit 120 is coupled to the second data pin D2 of the first integrated circuit 110 .

FIG. 2 is a schematic flowchart of an operating method of an electronic device according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2. In step S210 , the direction pin DR of the first integrated circuit 110 outputs a direction control signal DIR to the direction pin DR of the second integrated circuit 120 . Step S220 determines the logic state of the direction control signal DIR. When the determination result of step S220 indicates that the direction control signal DIR is in the first logic state, step S230 will be performed. When the determination result of step S220 indicates that the direction control signal DIR is in the second logic state, step S250 will be performed.

The first logic state and the second logic state can be determined according to design requirements. For example, in one embodiment, the first logic state may be a logic state "1" (such as a high logic level), and the second logic state may be a logic state "0" (such as a low logic level bits). In another embodiment, the first logic state may be a logic state "0" and the second logic state may be a logic state "1".

The initial state of the direction control signal DIR can be determined according to design requirements. For example, in an embodiment, the initial state of the direction control signal DIR may be the second logic state. In another embodiment, the initial state of the direction control signal DIR may be a first logic state.

When the direction control signal DIR is at the first logic state, the first integrated circuit 110 takes control in step S230. When the first integrated circuit 110 takes control, the clock pin CK of the first integrated circuit 110 outputs the clock signal SCL to the clock pin CK of the second integrated circuit 120 in step S240 . When the direction control signal DIR is at the second logic state, the second integrated circuit 120 takes control in step S250 . When the second integrated circuit 120 takes control, the clock pin CK of the second integrated circuit 120 outputs the clock signal SCL to the clock pin CK of the first integrated circuit 110 in step S260 .

Therefore, in this embodiment, the control right can be dynamically switched to one of the first integrated circuit 110 and the second integrated circuit 120 through the direction control signal DIR. For example, in the master-slave architecture, the first integrated circuit 110 that obtains the control can act as a "master (master)" role (master control end), while the second integrated circuit 120 acts as a "slave (slave)" role ( controlled end). When the first integrated circuit 110 takes control, the first integrated circuit 110 can output the frequency signal SCL to the second integrated circuit 120 . After the control right is dynamically switched from the first integrated circuit 110 to the second integrated circuit 120, the second integrated circuit 120 that has obtained the control right can be changed to the "master" role (master control terminal), while the first integrated circuit 110 is Change to the role of "servant" (accused end). When the second integrated circuit 120 takes control, the second integrated circuit 120 can output the second frequency signal SCL to the first integrated circuit 110 . Based on the frequency signal SCL, the first integrated circuit 110 and the second integrated circuit 120 can perform cooperative operations.

When the first integrated circuit 110 takes control, the first data pin D1 of the first integrated circuit 110 acts as the data output pin of the first integrated circuit 110, and the first data pin D1 of the second integrated circuit 120 acts as the second A data input pin of the integrated circuit 120 . Therefore, the first integrated circuit 110 that obtains the control right can output the main data signal MOSI to the second integrated circuit 120 . When the first integrated circuit 110 takes control, the second data pin D2 of the first integrated circuit 110 acts as the data input pin of the first integrated circuit 110, and the second data pin D2 of the second integrated circuit 120 acts as the second A data output pin of the integrated circuit 120 . Therefore, based on the control of the first integrated circuit 110 , the second integrated circuit 120 can output the slave data signal MISO to the first integrated circuit 110 .

When the second integrated circuit 120 takes control, the first data pin D1 of the second integrated circuit 120 acts as the data output pin of the second integrated circuit 120, and the first data pin D1 of the first integrated circuit 110 acts as the first A data input pin of the integrated circuit 110 . Therefore, the second integrated circuit 120 that obtains the control right can output the main data signal MOSI to the first integrated circuit 110 . When the second integrated circuit 120 takes control, the second data pin D2 of the second integrated circuit 120 acts as a data input pin of the second integrated circuit 120, and the second data pin D2 of the first integrated circuit 110 acts as the first A data output pin of the integrated circuit 110 . Therefore, based on the control of the second integrated circuit 120 , the first integrated circuit 110 can output the slave data signal MISO to the second integrated circuit 120 .

In this embodiment, “the signal of the first data pin D1 transitions from the fourth logic state to the fifth logic state when the signal of the clock pin CK is in the third logic state” is defined as a start signal. The start signal indicates the beginning of a data transfer period. “When the signal of the clock pin CK is at the third logic state, the signal of the first data pin D1 transitions from the fifth logic state to the fourth logic state” is defined as an end signal. The end signal indicates the end of the data transmission period. The third logic state, the fourth logic state and the fifth logic state can be set according to design requirements. For example, in this embodiment, the third logic state may be a logic state "1" (such as a high logic level), the fourth logic state may be a logic state "1", and the fifth logic state may be a logic state "1". The logic state may be a logic state "0" (eg, a low logic level). In another embodiment, the third logic state may be a logic state "0", the fourth logic state may be a logic state "0", and the fifth logic state may be a logic state "1".

FIG. 3 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to an embodiment of the present invention. Please refer to Figure 1 and Figure 3. In the embodiment shown in FIG. 3, "when the frequency signal SCL of the frequency pin CK is in logic state 1 (for example, a high logic level), the main data signal MOSI of the first data pin D1 transitions from logic state 1 to Logic state 0 (such as low logic level)" is defined as a start signal STA, and "when the frequency signal SCL is logic state 1, the main data signal MOSI transitions from logic state 0 to logic state 1" is defined as An end signal STP. The start signal STA indicates the start of a data transmission period, and the end signal STP indicates the end of a data transmission period.

In the embodiment shown in FIG. 3 , the initial state of the direction control signal DIR is assumed to be a logic state “0” (eg, a low logic level). When the direction control signal DIR is at the logic state “0”, the second integrated circuit 120 takes control. When the second integrated circuit 120 takes control (that is, when the direction control signal DIR is logic state "0"), the second integrated circuit 120 can output the frequency signal SCL to the first integrated circuit 110, and the second integrated circuit 120 can The start signal STA is output to the first integrated circuit 110 to start a data transmission period DP1. During the data transmission period DP1, the pulse width (the duration of the high logic level) or the valley width (the duration of the low logic level) of the frequency signal SCL is smaller than the threshold width, wherein the threshold width can be adjusted according to design requirements. Decide. During the data transmission period DP1 , the second integrated circuit 120 may output the master data signal MOSI to the first integrated circuit 110 , and the first integrated circuit 110 may output the slave data signal MISO to the second integrated circuit 120 . During the data transmission period DP1, the main data signal MOSI can transition when the clock signal SCL is at a low logic level, and the main data signal MOSI does not transition when the clock signal SCL is at a high logic level. The operation of the slave data signal MISO can be analogized with reference to the related description of the master data signal MOSI. The second integrated circuit 120 may output an end signal STP to the first integrated circuit 110 to end the data transmission period DP1.

The first integrated circuit 110 can pull up the direction control signal DIR to a logic state 1 (for example, a high logic level), so as to take back control from the second integrated circuit 120 . When the first integrated circuit 110 takes control (that is, when the direction control signal DIR is logic state "1"), the first integrated circuit 110 can output the frequency signal SCL to the second integrated circuit 120, and the first integrated circuit 110 can The start signal STA is output to the second integrated circuit 120 to start a data transmission period DP2. During the data transmission period DP2 , the first integrated circuit 110 may output the master data signal MOSI to the second integrated circuit 120 , and the second integrated circuit 120 may output the slave data signal MISO to the first integrated circuit 110 . The operation of the clock signal SCL, the main data signal MOSI and the slave data signal MISO in the data transmission period DP2 can be analogized with reference to the related description of the data transmission period DP1. The first integrated circuit 110 may output an end signal STP to the second integrated circuit 120 to end the data transmission period DP2.

It is assumed here that the pulse width (or valley width) of the clock signal SCL during the data transmission period (eg, the data transmission period DP1 or the data transmission period DP2 shown in FIG. 3 ) is smaller than a threshold width. The threshold width may be determined according to design requirements. In the embodiment shown in FIG. 1 , “when the first integrated circuit 110 takes control, the pulse width (or valley width) of the frequency signal SCL is greater than the threshold width” is defined as a reset signal. The first integrated circuit 110 can reset the second integrated circuit 120 through the reset signal. Therefore, the first integrated circuit 110 (the second integrated circuit 120 ) can save an extra reset pin.

FIG. 4 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention. Please refer to Figure 1 and Figure 4. In the embodiment shown in FIG. 4, "when the first integrated circuit 110 takes control (that is, when the direction control signal DIR is logic state "1"), the frequency signal SCL and/or the main data signal MOSI are pulled down and last Exceeding the threshold width (for example, exceeding 1 millisecond)" is defined as a reset signal RST. The first integrated circuit 110 can reset the second integrated circuit 120 through the reset signal RST.

FIG. 5 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention. Please refer to Figure 1 and Figure 5. In the embodiment shown in FIG. 5 , "the pulse width PW of the direction control signal DIR falls within a width range" is defined as an interrupt signal INT. The width range may be determined according to design requirements. For example, the width may range from 1 microsecond to 10 microseconds. The first integrated circuit 110 can notify the second integrated circuit of an interrupt request through the interrupt signal INT. Therefore, the first integrated circuit 110 (the second integrated circuit 120 ) can save an extra interrupt pin.

FIG. 6 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention. Please refer to Figure 1 and Figure 6. Here it is assumed that the first integrated circuit 110 has an interrupt flag (or an interrupt register). In the embodiment shown in FIG. 6, when the second integrated circuit 120 obtains the control right from the first integrated circuit 110 (that is, after the direction control signal DIR is changed from a logic state "1" to a logic state "0"), The second integrated circuit 120 first requests to read the interrupt flag (or interrupt register) of the first integrated circuit 110 through the main data signal MOSI. Based on the requirement/control of the second integrated circuit 120 , the first integrated circuit 110 may send back the content of the interrupt flag (or the interrupt register) to the second integrated circuit 120 through the slave data signal MISO. According to the content of the interrupt flag (or the interrupt register), the second integrated circuit 120 can know whether the first integrated circuit has issued an interrupt request. Therefore, the first integrated circuit 110 (the second integrated circuit 120 ) can save an extra interrupt pin.

It should be noted that, in different application scenarios, the relevant functions of the first integrated circuit 110 and/or the second integrated circuit 120 can use general programming languages (programming languages, such as C or C++), hardware description languages (hardware description) languages, such as Verilog HDL or VHDL) or other suitable programming languages to be implemented as software, firmware or hardware. The programming language that can perform the relevant functions can be arranged as any known computer-accessible media, such as magnetic tapes, semiconductors memory, magnetic disks or optical disks (compact disks, such as CD-ROM or DVD-ROM), or the programming language can be transmitted through the Internet (Internet), wired communication (wired communication), wireless communication (wireless communication) or other communication media. The programming language can be stored in an accessible medium of the computer, so that the processor of the computer can access/execute the programming codes of the software (or firmware). For hardware implementation, one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable logic gates Various logic blocks, modules and circuits in an array (Field Programmable Gate Array, FPGA) and/or other processing units may be used to implement or execute the functions described in the embodiments herein. In addition, the apparatus and method of the present invention can be realized by a combination of hardware and software.

To sum up, the electronic device 100 and its operating method in the above embodiments can be dynamically switched to one of the first integrated circuit 110 and the second integrated circuit 120 through the direction control signal DIR. When the first integrated circuit 110 takes control, the first integrated circuit 110 can output the clock signal SCL to the second integrated circuit 120 , and the first integrated circuit 110 can output the main data signal MOSI to the second integrated circuit 120 . Based on the control of the first integrated circuit 110 which has taken control, the second integrated circuit 120 may output the slave data signal MISO to the first integrated circuit 110 . When the second integrated circuit 120 takes control, the second integrated circuit 120 can output the clock signal SCL to the first integrated circuit 110 , and the second integrated circuit 120 can output the main data signal MOSI to the first integrated circuit 110 . Based on the control of the second integrated circuit 120 which takes control, the first integrated circuit 110 may output the slave data signal MISO to the second integrated circuit 120 .

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (14)

1. An electronic device, comprising:

a first integrated circuit having at least a direction pin and a frequency pin, wherein the direction pin of the first integrated circuit outputs a direction control signal; and

a second integrated circuit having at least a direction pin and a frequency pin, wherein the direction pin of the second integrated circuit is coupled to the direction pin of the first integrated circuit to receive the direction control signal, the frequency pin of the second integrated circuit is coupled to the frequency pin of the first integrated circuit,

wherein the first integrated circuit gains control when the direction control signal is in a first logic state, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit when the first integrated circuit gains the control, the second integrated circuit gains the control when the direction control signal is in a second logic state, and the frequency pin of the second integrated circuit outputs a second frequency signal to the frequency pin of the first integrated circuit when the second integrated circuit gains the control.

2. The electronic device of claim 1, wherein the initial state of the direction control signal is the second logic state.

3. The electronic device of claim 1, wherein the first integrated circuit further has a first data pin and a second data pin, the second integrated circuit further has a first data pin and a second data pin, the first data pin of the second integrated circuit is coupled to the first data pin of the first integrated circuit, the second data pin of the second integrated circuit is coupled to the second data pin of the first integrated circuit;

wherein when the first integrated circuit obtains the control right, the first data pin of the first integrated circuit is used as a data output pin of the first integrated circuit, the first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, the second data pin of the first integrated circuit is used as a data input pin of the first integrated circuit, and the second data pin of the second integrated circuit is used as a data output pin of the second integrated circuit; and

when the second integrated circuit obtains the control right, the first data pin of the second integrated circuit is used as the data output pin of the second integrated circuit, the first data pin of the first integrated circuit is used as the data input pin of the first integrated circuit, the second data pin of the second integrated circuit is used as the data input pin of the second integrated circuit, and the second data pin of the first integrated circuit is used as the data output pin of the first integrated circuit.

4. The electronic device according to claim 3, wherein "the transition of the signals of the plurality of first data pins from a fourth logic state to a fifth logic state when the signals of the frequency pins of the first and second integrated circuits are in the third logic state" is defined as a start signal indicating the start of a data transfer period, "the transition of the signals of the plurality of first data pins from the fifth logic state to the fourth logic state when the signals of the frequency pins of the first and second integrated circuits are in the third logic state" is defined as an end signal indicating the end of the data transfer period.

5. The electronic device of claim 1, wherein a pulse width of the first clock signal during data transmission is less than a threshold width, and a reset signal is defined as the pulse width of the first clock signal being greater than the threshold width when the first integrated circuit obtains the control right, and the first integrated circuit resets the second integrated circuit through the reset signal.

6. The electronic apparatus according to claim 1, wherein "a pulse width of the direction control signal falls within a width range" is defined as an interrupt signal by which the first integrated circuit notifies the second integrated circuit of an interrupt request.

7. The electronic device as claimed in claim 1, wherein the first IC has an interrupt flag, and when the second IC obtains the control right from the first IC, the second IC reads the interrupt flag of the first IC to know whether the first IC has an interrupt request.

8. A method of operation of an electronic device, wherein the electronic device includes a first integrated circuit and a second integrated circuit, the method of operation comprising:

outputting a direction control signal to a direction pin of the second integrated circuit by the direction pin of the first integrated circuit;

when the direction control signal is in a first logic state, the first integrated circuit obtains control power;

when the first integrated circuit obtains the control right, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit;

when the direction control signal is in a second logic state, the second integrated circuit obtains the control right; and

when the second IC obtains the control right, the frequency pin of the second IC outputs a second frequency signal to the frequency pin of the first IC.

9. The method of operation of claim 8, wherein the initial state of the direction control signal is the second logic state.

10. The method of claim 8, wherein a first data pin of the second integrated circuit is coupled to a first data pin of the first integrated circuit, and a second data pin of the second integrated circuit is coupled to a second data pin of the first integrated circuit;

when the first integrated circuit obtains the control right, a first data pin of the first integrated circuit is used as a data output pin of the first integrated circuit, a first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, a second data pin of the first integrated circuit is used as a data input pin of the first integrated circuit, and a second data pin of the second integrated circuit is used as a data output pin of the second integrated circuit; and

when the second integrated circuit obtains the control right, the first data pin of the second integrated circuit is used as the data output pin of the second integrated circuit, the first data pin of the first integrated circuit is used as the data input pin of the first integrated circuit, the second data pin of the second integrated circuit is used as the data input pin of the second integrated circuit, and the second data pin of the first integrated circuit is used as the data output pin of the first integrated circuit.

11. The method of operation of claim 10, further comprising:

defining "signals of the plurality of first data pins transition from a fourth logic state to a fifth logic state when signals of the frequency pins of the first and second integrated circuits are in a third logic state" as a start signal, wherein the start signal represents a start of a data transfer period; and

defining "the signals of the plurality of first data pins transition from the fifth logic state to the fourth logic state when the signals of the frequency pins of the first and second integrated circuits are the third logic state" as an end signal, wherein the end signal indicates an end of the data transfer period.

12. The method of operation of claim 8, wherein a pulse width of the first frequency signal during data transmission is less than a threshold width, the method of operation further comprising:

defining the pulse width of the first clock signal greater than the threshold width when the first integrated circuit obtains the control right as a reset signal, wherein the first integrated circuit resets the second integrated circuit through the reset signal.

13. The method of operation of claim 8, further comprising:

defining "the pulse width of the direction control signal falls within a width range" as an interrupt signal, wherein the first integrated circuit informs the second integrated circuit of an interrupt requirement through the interrupt signal.

14. The method of operation of claim 8, wherein the first integrated circuit has an interrupt flag, the method of operation further comprising:

when the second IC obtains the control right from the first IC, the second IC reads the interrupt flag of the first IC to know whether the first IC has proposed an interrupt request.

Images