CN101135921A - Multi-clock switching device and switching method thereof - Google Patents

Abstract

A multi-clock switching device and a switching method thereof can effectively prevent glitches from occurring on an output clock signal, the device comprises: the control unit generates a clock stop signal according to the slave control ready signal, the effective register address and the clock selection register address; a clock selection signal unit outputting a clock selection signal as a clock selection register signal according to the clock selection delay signal; a multiplexer for selecting one of the plurality of clock signals according to the clock selection register signal to generate a pre-output clock signal; a latch unit coupled to the multiplexer and the clock selection signal unit, for generating an output clock signal according to the clock stop delay signal and the pre-output clock signal; the sampling delay unit is used for sampling the clock stop signal to generate a clock stop delay signal and setting a low clock stop delay signal after a first preset time; the sampling clock stop signal generates a clock selection delay signal and is followed by a low clock selection delay signal at a second predetermined time.

Description

Multi-clock switching device and switching method thereof

technical field

The present invention relates to a multi-clock switching device and method, more specifically, a multi-clock switching device and a switching method thereof which prevent glitches during switching.

Background technique

A plurality of clock signals with different frequencies generally exist in current computer systems, and these clock signals with different frequencies are usually provided by a clock chip on a motherboard. In order to reduce power consumption, or to provide clock signals with different frequencies when plug-and-play (Plug-and-Play) peripherals are changed, special clock signal switching is required.

FIG. 1 is a schematic diagram of a conventional multi-clock switching device. The traditional multi-clock switching device is described here as a switching device for three clock signals. The switching of the clock signals CLK1, CLK2 and CLK3 is realized through a multiplexer (MUX) 10 and a clock selection signal CLK_SEL[1:0]. .

Referring now to FIG. 2, when the clock selection signal CLK_SEL[1:0] is 01, the multiplexer 10 selects the clock signal CLK1, that is, the output clock signal CLK_OUT is the clock signal CLK1; when the system wants to switch the output clock signal CLK_OUT, at time t changes the value of the clock selection signal CLK_SEL[1:0], as shown in Figure 2, the clock selection signal CLK_SEL[1:0] becomes 11 after time t, then the multiplexer 10 should select the clock signal CLK3, that is, output The clock signal CLK_OUT is the clock signal CLK3. But the actual situation is that when the multiplexer 10 switches the output, the clock signals CLK1 and CLK3 are at different levels, so a glitch 201 as shown in FIG. 2 will appear. The occurrence of glitches may cause misoperations such as synchronous failure and data loss in circuits using the output clock signal as a reference clock signal, thereby affecting the normal operation of the entire system.

In the prior art, different circuits and methods are used to prevent glitches during multi-clock switching. Usually, some preprocessing is performed on the clock selection signal before the multiplexer. For example, through preprocessing, the clock switching can occur when the clock signals CLK1 and CLK3 are both low. In this case, the clock switching occurs and the output clock signal CLK_OUT There will be no glitches. However, these preprocessing circuits are usually implemented by some sequential circuits, and there is a time delay in the sequential circuits, and under non-ideal conditions, the output clock signal also has glitches.

Contents of the invention

In order to more effectively prevent burrs from appearing on the output clock signal during clock switching, the invention provides a multi-clock switching device and a switching method thereof. The multi-clock switching device includes: a control unit, which generates a clock stop signal according to a slave ready signal, an effective register address and a clock selection register address; a clock selection signal unit, which generates a clock according to a clock selection delay signal The selection signal output is a clock selection register signal; a multiplexer, which selects one of the multiple clock signals according to the clock selection register signal, and generates a pre-output clock signal; and a latch unit, coupled to the multiplexer The device and the clock selection signal unit generate an output clock signal according to a clock stop delay signal and the pre-output clock signal; the multi-clock switching device also includes a sampling delay unit, which samples the clock stop signal to generate the clock stop Delaying the signal, and setting the clock stop delay signal low after a first predetermined time; sampling the clock stop signal to generate the clock selection delay signal, and setting the clock selection delay signal low after a second predetermined time.

The multi-clock switching method provided by the present invention includes: generating a clock stop signal according to a slave ready signal, an effective register address and a clock selection register address; sampling the clock stop signal to generate a clock stop delay signal, and Set the clock stop delay signal low after a predetermined time; sample the clock stop signal to generate a clock selection delay signal, and set the clock selection delay signal low after a second predetermined time; select a clock according to the clock selection delay signal The signal is output and maintained as a clock selection register signal; one of the plurality of clock signals is selected according to the clock selection register signal to generate a pre-output clock signal; and an output is generated according to the clock stop delay signal and the pre-output clock signal clock signal.

The multi-clock switching device and the switching method thereof in the present invention utilize the timing sequence of signals on the system bus to effectively detect the timing of clock switching, thereby effectively preventing glitch signals from appearing on the output clock signal.

Description of drawings

FIG. 1 is a schematic diagram of a conventional multi-clock switching device.

FIG. 2 is a signal timing diagram of traditional multi-clock switching.

FIG. 3 is a schematic diagram of an embodiment of a multi-clock switching device of the present invention.

FIG. 4 is a signal timing diagram of multi-clock switching in the present invention.

FIG. 5 is a flow chart of the steps of the multi-clock switching method of the present invention.

Detailed ways

The computer architecture based on the system bus has become the modern mainstream computer architecture. In the computer structure based on the system bus, the communication between the central processing unit and other devices will go through the bus. The clock switching request is usually issued by the operating system, and the clock selection signal is usually sent to the device or circuit that needs the output clock through the bus, so when the clock switching action occurs can be detected on the bus. Based on this, the present invention provides a multi-clock switching device and method to more effectively prevent the occurrence of burrs on the output clock signal.

In order to make the purpose, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail in conjunction with accompanying drawings 3 to 5 .

FIG. 3 is a schematic diagram of an embodiment of a multi-clock switching device of the present invention. The multi-clock switching device 300 includes a bus interface module 310 , a control unit 320 , a sampling delay unit 330 , a clock selection unit 340 , a multiplexer 350 and a latch unit 360 . The bus interface module 310 is hung on a system bus. Here, taking the commonly used system bus PCI bus as an example, the bus interface module 310 receives the effective register address Addr[7:0] and the clock selection signal CLK_SEL[1: from the PCI bus. 0], CLK_SEL[1:0] may be a request from a driver of a certain circuit in the operating system to switch the clock. People in the existing PCI bus technology know that when the equipment hanging on the PCI bus is addressed as the target equipment for data transmission on the bus, it will send a response signal to respond to the bus timing, so when the bus interface module 310 is addressed And when it is ready to receive the data on the bus CLK_SEL[1:0], it sends out a slave control ready signal TRDY# to respond. The control unit 320 generates a clock stop signal CLK_STOP according to the slave ready signal TRDY#, the valid register address Addr[7:0] and the clock selection register address Add CLK_SEL_NF[7:0]. The sampling delay unit 330 generates the clock stop delay signal CLK_STOP1 by sampling the clock stop signal CLK_STOP, and sets the clock stop delay signal CLK_STOP1 low after a first predetermined time; sets the clock stop delay signal CLK_STOP1 low after a second predetermined time to generate Clock selection delay signal CLK_DELAY. The clock selection signal unit 340 delays and outputs the clock selection signal CLK_SEL[1:0] as the clock selection register signal CLK_SEL_NF[1:0] according to the clock selection delay signal CLK_DELAY. The multiplexer 350 selects one of the multiple clock signals CLK1 , CLK2 , and CLK3 according to the clock selection register signal CLK_SEL_NF[1:0], and outputs it as the pre-output clock signal CLK_G. The latch unit 360 generates an output clock signal CLK_OUT according to the clock stop delay signal CLK_STOP1 and the pre-output clock signal CLK_G. The clock switching of the multi-clock switching device 300 occurs when the clock selection register signal CLK_SEL_NF[1:0] is updated, and a glitch may appear on the output CLK_G at this moment, but due to the control of the clock stop delay signal CLK_STOP1, the output clock signal CLK_OUT It is built low long enough before and after the clock switch, so it can ensure that the glitch signal that may appear can be filtered out. The specific structure of the multi-clock switching device 300 will be described in detail below, and how to ensure the timing will be described.

The control unit 320 includes a comparison logic 321, an OR logic gate 322 and an inverter 323, wherein the comparison logic 321 can be a multi-bit value comparator, starting from the highest bit, comparing the effective register address Addr[7:0] bit by bit Whether it is equal to each bit of the clock selection register address Add_CLK_SEL_NF[7:0], if they are all equal, then set its output low; or logic gate 322 is output again according to the output of the comparison logic 321 and the slave control ready signal TRDY The clock stop signal CLK_STOP is output via the inverter 323 .

The sampling delay unit 330 uses the bus clock CLK_BUS of the PCI bus as a reference clock signal. It includes an inverter 331 , an OR logic gate 332 , an AND logic gate 333 , a flip-flop 334 , a flip-flop 335 , a flip-flop 336 , an inverter 337 , an AND logic gate 338 , an inverter 339 , and an AND logic gate 3310 . The clock stop signal CLK_STOP is coupled to the flip-flop 334 through the OR logic gate 332 and the AND logic gate 333, the flip-flop 334 outputs the clock stop delay signal CLK_STOP1 under the control of the bus clock CLK_BUS, and the flip-flop 335 is coupled to the output terminal of the flip-flop 334 , under the control of the bus clock CLK_BUS, output the second clock stop delay signal CLK_STOP2, the flip-flop 336 is coupled to the output end of the flip-flop 335, and output the third clock stop delay signal CLK_STOP3 under the control of the bus clock CLK_BUS; AND logic gate 338 According to the output signal of the third clock stop delay signal CLK_STOP3 after the inverter 337 and the second clock stop delay signal CLK_STOP2, the clock stop feedback signal CLK_STOP_BACK is generated; the clock stop feedback signal CLK_STOP_BACK is output to the AND logic gate 333 through the inverter 331, The other input end of the OR logic gate 332 is coupled to the clock stop delay signal CLK_STOP1 . Therefore, the output of the AND logic gate 333 can maintain a high potential until the inversion signal of the clock stop feedback signal CLK_STOP_BACK pulls it low. This part of the circuit implements sampling the high transition edge of the clock stop signal CLK_STOP to generate the clock stop delay signal CLK_STOP1, and keeps the high time of CLKS_TOP1 for a first predetermined time (two bus clock cycles in this embodiment). The AND logic gate 3310 generates the clock selection delay signal CLK_DELAY according to the output signal of the second clock stop delay signal CLK_STOP2 through the inverter 339 and the clock stop delay signal CLK_STOP1, and its high time is maintained for a second predetermined time (this embodiment is one bus clock cycle).

In another embodiment of the present invention, the sampling delay unit 330 may add a flip-flop between the flip-flop 334 and the flip-flop 335 to realize that the first predetermined time is longer than two bus clock cycles. In another embodiment of the present invention, the clock stop delay signal CLK_STOP1 may be used instead of CLK_DELAY as the enable signal of the clock selection signal module 341 . The sampling delay unit 330 realizes the high transition edge of the sampling clock stop signal CLK_STOP to generate the clock stop delay signal CLK_STOP1, and keeps the high time of CLK_STOP1 for a first predetermined time (at least two bus clock cycles), according to this It is obvious to those skilled in the art that other improvements are made to the sampling delay unit 330 in the embodiment of the invention to realize these functions.

The clock selection signal unit 340 includes a clock selection signal module 341 and a clock selection signal register 342 . The clock selection signal module 341 is coupled to the bus interface module 310 and the sampling delay unit 330. According to the bus clock CLK_BUS, when the clock selection delay signal CLK_DELAY is set high, the clock selection signal CLK_SEL[1: 0] to output the clock selection register signal CLK_SEL_NF[1:0], and keep outputting the clock selection register signal CLK_SEL_NF[1:0] afterwards. The clock selection signal register 342 is coupled to the clock selection signal module 341 and stores the clock selection register signal CLK_SEL_NF[1:0]. The address of the clock selection signal register 342 is the clock selection register address Add_CLK_SEL_NF[7:0].

Table 1 is a logical function table of the clock selection signal module 341 .

Table 1

input signal output signal CLK_BUS CLK_DELAY CLK_SEL[1:0] CLK_SEL_NF[1:0] ↑ 1 d1 d0 d1 d0 ↑ 0 X X d1 d0

The clock selection signal module 341 uses the bus clock signal CLK_BUS as a clock signal, and triggers an action on its rising edge: when the clock selection delay signal CLK_DELAY is at a high potential, the clock selection register signal CLK_SEL_NF[1:0] is equal to the clock selection signal CLK_SEL[1: 0]; when the clock selection delay signal CLK_DELAY is low, the value of the clock selection register signal CLK_SEL_NF[1:0] remains unchanged.

The latch unit 360 includes an inverter 361 , an inverter 362 , a latch 363 and an AND logic gate 364 . The input terminal of the inverter 361 is coupled to the clock stop delay signal CLK_STOP1 , and the output terminal thereof is coupled to the data input terminal of the latch 363 . The input terminal of the inverter 362 is coupled to the pre-output clock signal CLK_G, and the output terminal thereof is coupled to the enable terminal of the latch 363 . Those skilled in the art know that the output is enabled when the enable terminal of the latch is at a high potential, therefore, when the pre-output clock signal CLK_G is set low, the latch 363 is enabled to output the clock gating signal CLK_EN, when the When the pre-output clock signal CLK_G is set high, keep the clock gating signal CLK_EN unchanged. The AND logic gate 364 generates the output clock signal CLK_OUT according to the clock gating signal CLK_EN and the pre-output clock signal CLK_G. This ensures that the transition of the clock gating signal CLK_EN must occur when the pre-output clock signal CLK_G is set low.

FIG. 4 is a timing diagram of multi-clock switching in the present invention. In the figure, slave ready signal TRDY#, clock stop signal CLK_STOP, clock stop delay signal CLK_STOP1, second clock stop delay signal CLK_STOP2, third clock stop delay signal CLK_STOP3, clock stop feedback signal CLK_STOP_BACK, clock selection delay signal CLK_DELAY, clock selection The registered signal CLK_SEL_NF[1:0] and the clock gating signal CLK_EN are synchronized with the bus clock signal CLK_BUS, that is, the actions of these signals are performed on the rising edge of the bus clock signal CLK_BUS; and the clock signals CLK1_CLK2 and CLK3 to be switched are synchronized with the bus clock signal The signal CLK_BUS can be fully asynchronous.

On the data address line AD of the PCI bus, the effective register address Addr[7:0] first appears, and after the transmission is completed, the clock selection signal CLK_SEL[1:0] appears, and the figure shows that the slave control ready signal TRDY# is controlled by the bus interface module 310 is set low for one cycle of the bus clock, during which the bus interface module 310 receives the clock selection signal CLK_SEL[1:0] from the bus. When the control unit 320 confirms that the effective register address Addr[7:0] is equal to the clock selection register address Add_CLK_SEL_NF[7:0], the clock stop signal CLK_STOP is set high while the slave ready signal TRDY# is set low. The rising edge of the clock stop delay signal CLK_STOP1 is generated by the sampling clock stop signal CLK_STOP, and the rising edge of the second clock stop delay signal CLK_STOP2 is generated by the sampling clock stop delay signal CLK_STOP1, and the rising edge of the third clock stop delay signal CLK_STOP3 is Sampling is generated by the second clock stop delay signal CLK_STOP2. The clock stop feedback signal CLK_STOPBACK is generated by the inversion of the third clock stop delay signal CLK_STOP3 and the second clock stop delay signal CLK_STOP2 through an AND operation. After inversion, it controls the clock stop delay signal CLK_STOP1 to be low, so that the clock stop delay signal CLK_STOP1 Set high two bus clock cycles and then set low, those skilled in the art know that the clock stop delay signal CLK_STOP1 can be set high for any number of bus clock cycles by increasing the number of flip-flops. . The clock selection delay signal CLK_DELAY is generated by an AND operation with the clock stop delay signal CLK_STOP1 after the inversion of the second clock stop delay signal CLK_STOP2 , so the second predetermined time for setting it high is one bus cycle. When it is detected that the clock selection delay signal CLK_DELAY is high, the clock selection register signal CLK_SEL_NF[1:0] is updated according to the clock selection signal CLK_SEL[1:0], and a clock switching action occurs at this time, that is, at time t ₂ in the figure, The pre-output clock signal CLK_G is switched from the clock signal CLK1 to CLK3, and a glitch signal 401 appears on the pre-output clock signal CLK_G. The clock gating signal CLK_EN is generated by the latch 363 according to the clock stop delay signal CLK_STOP1 and the pre-output clock signal CLK_G, and it only jumps when the pre-output clock signal CLK_G is set low; the clock gating signal CLK_EN and the pre-output clock signal CLK_G performs an AND operation to generate an output clock signal CLK_OUT, and the output clock signal CLK_OUT is set low between time _t1 and time _t3 , thereby filtering out the glitch signal 401 .

FIG. 5 is a flow chart of the steps of the multi-clock switching method of the present invention. First step S501 "judging whether the slave ready signal TRDY# is set low, and the effective register address Addr[7:0] is equal to the clock selection register address Add_CLK_SEL_NF[7:0]", if yes, it indicates that a clock switching request has occurred on the bus, Then step S502 of “setting the clock stop signal CLK_STOP high” is executed. Then perform step S503 "sample the clock stop signal CLK_STOP to generate a clock stop delay signal CLK_STOP1, and set the clock stop delay signal CLK_STOP1 low after a first predetermined time; it samples the clock stop signal CLK_STOP to generate a clock selection delay signal CLK_DELAY, and Set the clock selection delay signal CLK_DELAY low after a second predetermined time. Referring to FIG. 4, it can be known that the "sampling clock stop signal CLK_STOP" refers to the rising edge of the sampling clock stop signal CLK_STOP according to the bus clock signal CLK_BUS. Clock stop delay signal CLK_STOP1 and clock selection delay signal CLK_DELAY, "setting the clock stop delay signal low after a first predetermined time" means that after two bus clock cycles as shown in Figure 4, set low clock stop delay signal CLK_STOP1 ; "setting the clock selection delay signal low after a second predetermined time" refers to setting the clock selection delay signal CLK_DELAY low after a bus clock cycle as shown in FIG. 4 . Then execute step S504 "output the clock selection signal CLK_SEL[1:0] according to the clock selection delay signal CLK_DELAY and keep it as the clock selection registration signal CLK_SEL_NF[1:0]" means that according to the bus clock CLK_BUS, when the clock selection delay signal CLK_DELAY is set When high, the clock selection signal CLK_SEL[1:0] from the system bus is output as the clock selection registration signal CLK_SEL_NF[1:0], and then the clock selection registration signal CLK_SEL_NF[1:0] is kept output. Then execute step S505 "select one of the multiple clock signals according to the clock selection register signal CLK_SEL_NF[1:0] to generate the pre-output clock signal CLK_G", that is, clock switching is performed while the clock selection register signal is updated, and the generated There may be glitches on the pre-output clock signal CLK_G. Then execute step S506 "according to the clock stop delay signal CLK_STOP1 and the pre-output clock signal CLK_G, generate the output clock signal CLK_OUT", referring to Figure 4, that is, when the pre-output clock signal CLK_G is set low, the clock stop delay signal CLK_STOP1 The inverse signal of the clock gating signal CLK_EN is generated; when the pre-output clock signal CLK_G is set high, the clock gating signal CLK_EN remains unchanged. And when the clock gating signal CLK_EN is set low, the pre-output clock signal CLK_G is set low, and the output is the output clock signal CLK_OUT.

Based on the above description, the multi-clock switching device and method disclosed in the present invention overcomes the problem of glitches in clock switching in the prior art. The present invention utilizes the timing of signals on the system bus to effectively detect the timing of clock switching. When a clock switching request is detected on the bus, it delays for a second predetermined time, and then updates the data in the clock selection signal register. The action of clock switching, and the output clock signal is set low within a first predetermined time before and after the clock switching time, thereby effectively preventing the glitch signal on the output clock signal.

The embodiment shows three clock signals CLK1, CLK2, and CLK3. In fact, those skilled in the art know that the multi-clock switching device and method disclosed in the present invention can be applied to the switching of N clock signals (N≥2 ). The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and improvements on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of the present application.

A brief description of the symbols in the drawings is as follows:

300: clock switching device

310: bus interface module

320: control unit

321: Comparison logic

322: OR logic gate

323: Inverter

330: Sampling delay unit

331: Inverter

332: OR logic gate

333: AND logic gate

334: Trigger

335: Trigger

336: Trigger

337: Inverter

338: AND logic gate

339: Inverter

3310: AND logic gate

340: clock selection unit

341: Clock selection signal module

342: Clock selection signal register

350: multiplexer

360: Latch unit

361: Inverter

362: Inverter

363: Latches

364: AND logic gate

Claims (13)

1. A multi-clock switching device, characterized in that, comprising: A control unit generates a clock stop signal according to a slave control ready signal, an effective register address and a clock selection register address; a clock selection signal unit, outputting a clock selection signal as a clock selection registration signal according to a clock selection delay signal; a multiplexer, which selects one of a plurality of clock signals according to the clock selection register signal to generate a pre-output clock signal; and A latch unit, coupled to the multiplexer and the clock selection signal unit, generates an output clock signal according to a clock stop delay signal and the pre-output clock signal. 2. The multi-clock switching device according to claim 1, wherein the slave control ready signal comes from a bus interface module, and when the bus interface module is addressed and ready to receive data, the slave control signal is set low ready signal and receive this clock select signal on the bus. 3. The multi-clock switching device according to claim 2, further comprising a sampling delay unit, which samples the clock stop signal to generate the clock stop delay signal, and sets the clock low after a first predetermined time. A clock stop delay signal; it samples the clock stop signal to generate the clock selection delay signal, and sets the clock selection delay signal low after a second predetermined time. 4. The multi-clock switching device according to claim 3, wherein the first predetermined time is at least two bus clock cycles, and the second predetermined time is one bus clock cycle. 5. The multi-clock switching device according to claim 4, wherein the control unit sets the clock stop signal high when the slave ready signal is low and the valid register address is equal to the clock selection register address. 6. The multi-clock switching device according to claim 5, wherein the clock selection signal unit comprises: A clock selection signal module, coupled to the bus interface module and the sampling delay unit, when the clock selection delay signal is set high, the clock selection signal is output and kept as the clock selection registration signal; and A clock selection signal register is coupled to the clock selection signal module, its address is the address of the clock selection register, and stores the clock selection register signal. 7. The multi-clock switching device according to claim 6, wherein the latch unit further comprises: an inverter, the input end of which is coupled to the clock stop delay signal; A latch, the data input end of which is coupled to the output end of the inverter, when the pre-output clock signal is set low, the latch is enabled to output a clock gating signal, when the pre-output clock signal is set When high, keep this clock gating signal unchanged; and An AND logic gate generates an output clock signal according to the clock gating signal and the pre-output clock signal. 8. A multi-clock switching method is characterized in that, comprising the steps of: generating a clock stop signal according to a slave ready signal, a valid register address and a clock selection register address; Sampling the clock stop signal to generate a clock stop delay signal, and setting the clock stop delay signal low after a first predetermined time; sampling the clock stop signal to generate a clock selection delay signal, and setting low after a second predetermined time The clock select delay signal; Outputting a clock selection signal according to the clock selection delay signal and keeping it as a clock selection registration signal; Selecting one of a plurality of clock signals according to the clock selection register signal to generate a pre-output clock signal; and An output clock signal is generated based on the clock stop delay signal and the pre-output clock signal. 9. The multi-clock switching method according to claim 8, wherein the valid register address and the clock selection signal are received from the same system bus. 10. The multi-clock switching method according to claim 9, wherein the step of generating the clock stop delay signal and the clock selection delay signal and the step of outputting and maintaining the clock selection registration signal are all carried out according to a bus clock signal operate. 11. The multi-clock switching method according to claim 10, wherein the first predetermined time is at least two bus clock cycles, and the second predetermined time is one bus clock cycle. 12 . The multi-clock switching method according to claim 11 , wherein when the slave ready signal is set low and the valid register address is equal to the clock selection register address, the clock stop signal is set high. 13 . 13. The multi-clock switching method according to claim 12, wherein the step of outputting the output clock signal further comprises: When the pre-output clock signal is set low, a clock gating signal is generated according to the inversion signal of the clock stop delay signal; When the pre-output clock signal is set high, keep the clock gating signal unchanged; and When the clock gating signal is set low, the pre-output clock signal is set low.

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