CN110008075A - A kind of chip adjustment method and device - Google Patents

Abstract

This paper discloses an embodiment of the present invention and provides a chip debugging method and device, including: after entering the DEBUG mode, receiving an address signal of a serially input register; reading the value of the corresponding register according to the register address signal ; Serially output the value of the register. The present application can debug all the key signals and registers inside the chip with as little cost as possible.

Description

A chip debugging method and device

technical field

The invention relates to the technical field of chip design, in particular to a chip debugging method and device.

Background technique

In the related art, the DEBUG technology of the chip's internal signal is mainly to debug the data of the CPU and its affiliated modules, such as joint test work group (JTAG, Joint Test Action Group) debugging, TRACE debugging, by passing the CPU instructions or data through. The specially defined interface is directly or stored and then exported, so as to achieve the purpose of DEBUG, but when the crash occurs, this method has certain limitations, and it cannot read the key signals and key registers in the chip, and the value of the key signal can be It is helpful for debugging personnel to judge the cause of the crash.

Therefore, how to read key signal values and register values in the chip for viewing by debuggers during the DEBUG process when the machine crashes is a technical problem to be solved urgently.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the embodiments of the present invention provide a chip debugging method and device, which can debug all key signals and registers inside the chip with as little cost as possible.

The embodiment of the present invention provides the following technical solutions:

A chip debugging method, comprising:

After entering DEBUG mode, receive the address signal of the serially input register;

According to the register address signal, read the value of the corresponding register;

The value of the register is serially output.

The reading the value of the corresponding register according to the register address signal includes: decoding the register address signal, determining the module to which the corresponding register belongs, and reading the value of the register from the module to which the register belongs.

Wherein, the method further includes: performing a parallel-to-serial operation after reading the value of the register.

The value of the register is serially output through the predefined DEBUG_ADDR pin.

Wherein, the method also includes one of the following:

Set the DEBUG_EN pin high to enter the DEBUG mode;

After the value of the register is serially output, the DEBUG_EN pin is set low to exit the DEBUG mode.

A chip debugging device, comprising:

The decoding module is used to receive the address signal of the serially input register after entering the DEBUG mode, and read the value of the corresponding register according to the register address signal;

The output module is used for serially outputting the value of the register.

It also includes: a conversion module; the decoding module is specifically configured to receive a serially input register address signal, decode the register address signal, determine the module to which the corresponding register belongs, and convert the module to the module to which the register belongs. The module sends a read operation instruction; the conversion module is configured to receive the read operation instruction from the decoding module, read the value of the corresponding register, and perform a parallel-to-serial operation on the value of the register.

Wherein, the output module includes at least: a predefined DEBUG_ADDR pin.

Among them, it also includes: DEBUG_EN pin, which is used to indicate that DEBUG mode has been entered when it is set to high.

A chip that includes:

The memory that stores the chip debugging program;

The processor is configured to execute the chip debugging program to perform the operations of the above-mentioned chip debugging method.

A computer-readable storage medium stores a chip debugging program on the computer-readable storage medium, and when the chip debugging program is executed by a processor, implements the steps of the above-mentioned chip debugging method.

The embodiment of the present invention can realize the purpose of DEBUG whole chip through simple logic and fewer pins, that is, the purpose of debugging all key signals and registers inside the chip can be realized at the least cost, and meanwhile, the purpose of saving pins is also achieved. The effect is to speed up the debugging progress.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention.

FIG. 1 is a schematic flowchart of a chip debugging method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a chip debugging device according to an embodiment of the present invention;

3 is a schematic diagram of an exemplary structure of a chip in an embodiment of the present invention;

4 is a functional schematic diagram of a decoding module in the chip shown in FIG. 3;

Fig. 5 is the functional schematic diagram of the conversion module in the chip shown in Fig. 3;

FIG. 6 is an exemplary implementation flowchart of a chip debugging method according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

In the current chip design, DEBUG is a very important part of the design, which is related to the debugging progress of the chip, which in turn affects the progress of the product launch. If the execution method of DEBUG is unreasonable, the cost of human time and time will be immeasurable. Similar technical solutions in related technologies are more limited. In related technologies, the debugging of the chip is to use the DEBUG function that comes with the CPU, from JTAG to TRACE, but these solutions require highly complex and large-area modules, and also require chip design engineers and Debugging engineers have a long time to learn, understand and apply, and when the chip crashes, the scope of debugging is extremely limited, and JTAG debugging does not even work. Therefore, regardless of the cost of chip area, the labor cost of subsequent debugging is very high.

In view of the above technical problems of the related art, the present application provides the following technical solutions. The technical solution of the present application can achieve the purpose of DEBUG full-chip registers and key signals through simple logic and fewer pins.

The implementation manner of the technical solution of the present application will be described in detail below.

Example 1

As shown in FIG. 1, a chip debugging method is provided, which is characterized in that:

Step 101, after entering the DEBUG mode, receive the address signal of the serially input register;

Step 102, according to the register address signal, read the value of the corresponding register;

Step 103: Serially output the value of the register, so that the observation device (eg, an oscilloscope) receives the value of the register and displays it (eg, displays the value of the register through a waveform), so that the debugger can observe .

Here, the register is a pre-debugged register, and the register address signal refers to the address signal of the pre-debugged register.

In this embodiment, two dedicated debug pins are used, and simple logic is added to the content of the chip, which is connected to all IP modules of the AMBA bus interface. The register value can be read out through the connection module, and at the same time converted into serial data and output to the pin, which can be observed by the oscilloscope. In this way, when the chip crashes and the CPU cannot be accessed, the method of this embodiment can still quickly access internal registers, capture the value of key signals, and quickly locate faults, thereby achieving the purpose of DEBUG full-chip registers and key signals. It can be seen from this that this embodiment can realize the purpose of DEBUG full-chip through simple logic and fewer pins, that is, the purpose of debugging all key signals and registers inside the chip can be realized at the least possible cost, and at the same time, the purpose of saving The effect of the pins speeds up the debugging progress.

In this embodiment, reading the value of the corresponding register according to the register address signal may include: decoding the register address signal, determining the module to which the corresponding register belongs, and reading the value of the corresponding register from the module to which the register belongs. the value of the register.

In this embodiment, the method may further include: performing a parallel-to-serial operation after reading the value of the register.

In this embodiment, the value of the register is serially output through the predefined DEBUG_ADDR pin.

In this embodiment, one or both of the following may also be included: 1) set the DEBUG_EN pin to high to enter the DEBUG mode; 2) after serially outputting the value of the register, connect the DEBUG_EN pin to the high pin low to exit the DEBUG mode.

Embodiment 2

A chip debugging device, as shown in Figure 2, may include:

The decoding module 21 is used to receive the address signal of the serially input register after entering the DEBUG mode, and read the value of the corresponding register according to the register address signal;

The output module 22 is used for serially outputting the value of the register.

In this embodiment, the above-mentioned chip debugging device may further include: a conversion module 23; the decoding module 21 can be specifically configured to receive a serially input register address signal, decode the register address signal, determine the module to which the corresponding register belongs, and Send a read operation instruction to the conversion module in the module to which the register belongs; the conversion module 23 can be used to receive the read operation instruction from the decoding module, read the value of the corresponding register and compare the value of the register. String operation.

In this embodiment, the output module 22 may at least include: a predefined DEBUG_ADDR pin. In other words, the value of the register is serially output through the pre-defined DEBUG_ADDR pin.

In this embodiment, the above apparatus may further include: a DEBUG_EN pin, which is used to indicate that the DEBUG mode has been entered when it is set to high. In addition, the DEBUG_EN pin can be used to indicate that DEBUG mode has been exited when asserted low.

For other technical details in this embodiment, refer to Embodiment 1.

Embodiment 3

A chip that includes:

The memory that stores the chip debugging program;

A processor configured to execute the chip debugging program to perform the operations of the chip debugging method of the first embodiment.

For other technical details in this embodiment, refer to Embodiment 1.

Embodiment 4

A computer-readable storage medium stores a chip debugging program on the computer-readable storage medium, and when the chip debugging program is executed by a processor, implements the steps of the chip debugging method in the first embodiment.

For other technical details in this embodiment, refer to Embodiment 1.

Exemplary implementations of the above embodiments will be described in detail below. It should be noted that the following examples can be arbitrarily combined. Moreover, in practical applications, the above embodiments may also have other implementation manners, and each process, execution process, etc. in the following examples may also be adjusted according to the needs of practical applications.

Example 1

As shown in FIG. 3 , it is a schematic diagram of an exemplary structure of a chip. As shown in FIG. 3 , the chip is provided with a decoding module and a conversion module connected with the original modules (module 1, . . . , module n) in the chip one by one. Among them, as shown in Figure 4, the decoding module is responsible for address decoding, serial address input, module selection, and data serial output. As shown in Figure 5, each conversion module is responsible for converting the serial address signal of the module it is connected to. For AMBA bus read interface, AMBA bus read data to serial data signal. The conversion module also includes a control sub-module, which is responsible for the timing control of the conversion module. Specifically, the control sub-module is used to control the conversion module to perform corresponding operations according to the following sequence: operate the read address, then acquire the data, and then output it to the pin.

As shown in FIG. 6 , it is an exemplary implementation flow of chip debugging.

As shown in Figure 6, an exemplary execution flow of chip debugging may include:

Step 601, set the DEBUG_EN pin to high, indicating that the chip is in DEBUG mode, and the internal conversion module will automatically disconnect the pre-debugged IP module from the original AMBA bus, so that the module is directly connected to the conversion module;

Step 602, from the DEBUG_ADDR pin to the serially input 32-bit register address signal in the chip;

Step 603: The decoding module decodes the serially input 32-bit register address signal, determines which module's register to access according to the register address, and selects the conversion module connected to the module to perform the read operation.

In this application, the key signal is allocated to the register, so that the signal value of the key signal can be directly accessed and read through the register address.

Step 604, the conversion module will read out the value of the corresponding register and perform the parallel-to-serial operation, and return the corresponding serial data signal to the decoding module;

In step 605, the decoding module receives the serial data signal returned by the above-mentioned register, and serially outputs the corresponding data, that is, the value of the register to the pin, and the debugger can observe the value of the register through the oscilloscope. Taking into account the observability, the decoding module can output the value of the register by jumping through a certain format of coding to prevent the observation inconvenience caused by continuous 0 or continuous 1, and can also repeat the output multiple times.

Those of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware (such as a processor) through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk Wait. Optionally, all or part of the steps in the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above-mentioned embodiments can be implemented in the form of hardware, for example, an integrated circuit to implement its corresponding function, or it can be implemented in the form of a software function module, for example, a program stored in a memory is executed by a processor. / directive to implement its corresponding function. The present application is not limited to any particular form of combination of hardware and software.

The above shows and describes the basic principles and main features of the present application and the advantages of the present application. The present application is not limited by the above-mentioned embodiments. The above-mentioned embodiments and descriptions only describe the principles of the present application. Without departing from the spirit and scope of the present application, the present application will also have various changes and improvements. These changes and improvements are within the scope of the claimed application.

Claims (11)

1. a kind of chip adjustment method characterized by comprising

After entering DEBUG mode, the address signal of the register of serial input is received；

According to the register address signal, the value of corresponding registers is read；

By the value Serial output of the register.

2. reading is corresponding the method according to claim 1, wherein described according to the register address signal The value of register, comprising:

The register address signal is decoded, determines module belonging to corresponding registers, and to module belonging to the register Read the value of the register.

3. method according to claim 1 or 2, which is characterized in that the method also includes:

After the value for reading the register, executes and turn string operation.

4. the method according to claim 1, wherein

By DEBUG_ADDR pin predetermined by the value Serial output of the register.

5. the method according to claim 1, wherein the method also includes one of following:

DEBUG_EN pin is set to height, to enter the DEBUG mode；

After the value Serial output of the register, the DEBUG_EN pin is set to it is low, to exit the DEBUG mould Formula.

6. a kind of chip debugging apparatus, comprising:

Decoder module, for the address signal of the register of serial input being received, according to described after entering DEBUG mode Register address signal reads the value of corresponding registers；

Output module, for by the value Serial output of the register.

7. chip debugging apparatus according to claim 6, which is characterized in that further include: conversion module；

The decoder module decodes the register address signal specifically for the register address signal of reception serial input, Determine module belonging to corresponding registers, and the conversion module into module belonging to the register sends read operation instruction；

The conversion module reads the value of corresponding registers and incites somebody to action for receiving the read operation instruction from the decoder module The value of the register carries out and turns string operation.

8. chip debugging apparatus according to claim 6, which is characterized in that

The output module, includes at least: DEBUG_ADDR pin predetermined.

9. chip debugging module according to claim 6, which is characterized in that further include:

DEBUG_EN pin has entered DEBUG mode for indicating when being set to high.

10. a kind of chip, comprising:

It is stored with the memory of chip debugging routine；

Processor is configured to execute the chip debugging routine to execute the chip debugging side as described in any one of claim 1 to 5 The operation of method.

11. a kind of computer readable storage medium, which is characterized in that be stored with chip tune on the computer readable storage medium Program is tried, the chip debugging side as described in any one of claims 1 to 5 is realized when the chip debugging routine is executed by processor The step of method.