CN109981517B - QPSK neural network demodulator based on FPGA and control method thereof - Google Patents

Abstract

The invention relates to an FPGA-based QPSK neural network demodulator, comprising: a clock and reset module, which is used for sending a clock signal and a reset signal; an AD sampling module, which is used for sampling the to-be-demodulated signal to obtain sampling data; an input buffer module, It is used to receive and buffer the sampled data, and perform clock domain conversion on the sampled data; the phase mutation detection module is used to detect the relative phase change in the sampled data after clock domain conversion, and output the phase mutation information; the constellation rotation and data inversion module , which is used to receive and process phase mutation information to form baseband data; the synchronous output module is used to synchronously judge baseband data, and generate and output demodulated data. The demodulator proposed by the invention has low parameter complexity and high structural stability, can improve the demodulator's adaptability to special environments through targeted training, and uses a time delay network to perform one-dimensional convolution operations, thereby reducing computational costs. complexity, and improve the efficiency of hardware resource use.

Description

A QPSK neural network demodulator based on FPGA and its control method

technical field

The invention belongs to the technical field of digital communication, in particular to an FPGA-based QPSK neural network demodulator and a control method thereof.

Background technique

The modulation and demodulation link is a crucial process in the digital communication system. The so-called modulation is the process of loading the baseband signal onto the higher frequency electromagnetic wave signal in order to facilitate the transmission of the signal, and the demodulation is the reverse process of the modulation. , is the process of moving the signal from higher frequencies to lower frequencies. Generally speaking, the input signal of the demodulator will introduce many non-ideal factors in the process of transmission and reception, including environmental noise, multipath effect, electromagnetic interference of receiving equipment, etc. The existence of these factors puts forward higher requirements on the performance of the demodulator. It can be said that the performance of the demodulator largely affects the performance of the entire communication system.

As a typical feedforward multi-layer neural network, convolutional neural network can automatically extract complex features from a large amount of data and perform autonomous learning, and does not require high input images, and does not require complicated pre-processing of input images. . Because of the specific network structure of the convolutional neural network, its recognition ability is not easily affected by graphic distortion or simple geometric transformation in the image, and it also has a good recognition effect on the recognition objects with some subtle changes. Among them, the one-dimensional convolutional neural network is particularly suitable for processing discrete time series due to the structural characteristics of its one-dimensional input. The high-speed AD sampling data of the modulated signal is just such a set of sequences. If it is input into a one-dimensional convolutional neural network, the information carried in the modulated signal can be analyzed by detecting some of the features. This method has its unique advantages compared with the traditional demodulation method. First, a stable network structure can be constructed through experiments, making it insensitive to the parameter disturbance of the input signal and improving its robustness. Secondly, since the ability of one-dimensional convolutional neural networks to identify information is obtained through training, when dealing with special channel environments, the adaptability of one-dimensional convolutional neural networks can be improved by designing a large number of characteristic training data. It can better adapt to special conditions such as frequency offset.

With the advancement of microelectronics manufacturing process and integrated circuit design, the hardware implementation schemes of convolutional neural networks are becoming more and more diverse. Among them, Field Programmable Gate Array (FPGA) is stable, reliable, resource-rich and can The advantages of repetitive programming, low power consumption, and high speed make it the best choice for hardware implementation of convolutional neural networks. In recent years, the development of high-level synthesis tools based on FPGA has greatly reduced the development difficulty of FPGA design and made it easier and faster to implement complex algorithms on FPGA.

In traditional demodulators, two methods of coherent demodulation and non-coherent demodulation are generally used. Among them, coherent demodulation has been more widely used due to its good anti-noise performance. Coherent demodulation is mainly aimed at the demodulation of linearly modulated signals, and its realization method is to recover a coherent carrier that is strictly synchronized with the modulated carrier at the receiving end, and then conduct frequency mixing and judgment. The quality of the coherent carrier is directly related to the performance of the demodulator. In this method, there are a large number of configurable parameters, including filter parameters, numerically controlled oscillator parameters, phase detection parameters, loop parameters, etc., each parameter may affect the demodulation performance, which causes the demodulator The robustness is poor, and can not be upgraded and improved in a targeted manner for a special environment, such as frequency offset.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides an FPGA-based QPSK neural network demodulator and a control method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides an FPGA-based QPSK neural network demodulator, including:

Clock and reset module, used to send clock signal and reset signal;

AD sampling module, used for sampling the demodulated signal to obtain sampling data;

an input buffer module for receiving and buffering the sampled data, and performing clock domain conversion on the sampled data;

a phase mutation detection module, configured to detect the relative phase change in the sampled data after clock domain conversion, and output phase mutation information;

a constellation rotation and data inversion module for receiving and processing the phase mutation information to form baseband data;

The synchronous output module is used for synchronously judging the baseband data, and generating and outputting demodulated data.

In an embodiment of the present invention, the method further includes: a PCIe interaction module, configured to input network parameters to the FPGA.

In an embodiment of the present invention, it further includes: a parameter storage module, configured to receive, store and forward the network parameters.

In an embodiment of the present invention, the phase mutation detection module includes: a plurality of one-dimensional convolutional neural networks implemented in an FPGA.

In an embodiment of the present invention, the one-dimensional convolutional neural network includes: an input layer, a convolutional layer, a hidden layer and an output layer, and auxiliary input buffer, output buffer and control module.

Another embodiment of the present invention provides a control method of an FPGA-based QPSK neural network demodulator, including:

Send clock signal and reset signal;

Obtain sampling data by sampling the demodulated signal;

receiving and buffering the sampled data, and performing clock domain conversion on the sampled data;

Detecting the relative phase change in the sampled data after clock domain conversion, and outputting phase mutation information;

receiving and processing the phase mutation information to form baseband data;

The baseband data is judged synchronously, and demodulated data is generated and output.

In an embodiment of the present invention, before sending the clock signal and the reset signal, the method further includes: storing the network parameters in the parameter storage module.

In an embodiment of the present invention, before sampling the to-be-demodulated signal to obtain sampled data, the method further includes: inputting network parameters into the FPGA.

Compared with the prior art, the beneficial effects of the present invention:

1. The demodulator proposed by the present invention takes the relative phase sudden change in the QPSK modulated signal as a feature, and uses the phase sudden change detection module implemented in the FPGA to perform feature detection on it, and respectively detects three kinds of relative phases in the QPSK modulated signal. Change, use the constellation rotation and data inversion module implemented in the FPGA to output the demodulated data waveform according to the type and timing of the phase sudden change, and then complete the demodulation.

2. The demodulator proposed by the present invention has low parameter complexity and high structural stability, and can improve the adaptability of the demodulator to special environments through targeted training, and uses a time delay network to perform one-dimensional convolution operations to reduce It reduces the computational complexity and improves the utilization efficiency of hardware resources.

Description of drawings

1 is a schematic structural diagram of an FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

2 is a schematic waveform diagram of a signal to be demodulated in an FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

3 is a schematic diagram of a working process of an FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

4 is a schematic structural diagram of a one-dimensional convolutional neural network in another FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

5 is a schematic diagram of one-dimensional Same convolution operation in yet another FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

6 is a schematic structural diagram of a time delay network in another FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention;

FIG. 7 is a schematic flowchart of another control method of an FPGA-based QPSK neural network demodulator provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of an FPGA-based QPSK neural network demodulator according to an embodiment of the present invention.

An embodiment of the present invention provides an FPGA-based QPSK neural network demodulator, including:

Clock and reset module, used to send clock signal and reset signal;

AD sampling module, used for sampling the demodulated signal to obtain sampling data;

The input buffer module is used to receive and buffer the sampled data, and perform clock domain conversion on the sampled data;

The phase mutation detection module is used to detect the relative phase change in the sampled data after clock domain conversion, and output the phase mutation information;

Constellation rotation and data inversion module for receiving and processing phase mutation information to form baseband data;

The synchronous output module is used for synchronously judging baseband data, and generating and outputting demodulated data.

Specifically, the clock and reset module sends two signals, a clock signal and a reset signal. The clock signal always exists when the system is working, and the reset signal exists only when the reset signal is sent. The input buffer module is located at the front end of the demodulator, and is used to complete the function of input buffer sample data. The front stage of the demodulator is the AD sampling module. When the two perform data transmission, the input buffer module completes the data reception according to the sampling synchronization clock given by the AD sampling module, and this sampling synchronization clock is different from the clock in the FPGA. It is stable and cannot be used directly by the subsequent stage. Therefore, here, a FIFO is set in the input buffer module for the cross-clock domain processing of the signal line, the output data width is equal to the input signal width, and the clock on the FPGA is used as the synchronous output clock of the data.

The clock of the demodulator is generated by the external crystal oscillator after being phase-locked by the internal PLL of the FPGA, and is provided to each module through the global clock network to ensure that the delay of the clock reaching each module is the same.

The clock and reset module is also used to generate a reset signal for demodulator operation. The reset signal includes two stages. The first stage is clock reset, that is, after the demodulator is powered on, the PLL starts to work from reset; the second stage reset is program reset. After the PLL enters the locked state, all modules enter the working state from the reset state. This structure can effectively avoid the logic disorder caused by the unstable clock at the initial stage of power-on.

In particular, the specific embodiment of the present invention further includes: a PCIe interaction module, configured to input network parameters to the FPGA.

The PCIe interaction module is used to complete the information interaction between the general-purpose computer and the FPGA. It mainly inputs the trained network parameters into the FPGA, and outputs the demodulated data to the computer for further analysis and processing.

In particular, in a specific embodiment of the present invention, it further includes: a parameter storage module, configured to receive, store and forward the network parameters.

The parameter storage module mainly uses the BRAM resources in the FPGA to form a block storage array to store network parameters. Before the FPGA is reset, the host computer stores the network parameters in the parameter storage module. Parameters are only used and not modified in the FPGA. After the module is powered on, it reads in network parameters through the PCIe interface, and provides it to the phase mutation detection module when needed.

In particular, in the specific embodiment of the present invention, the phase mutation detection module includes: a plurality of one-dimensional convolutional neural networks implemented in FPGA.

Specifically, the phase mutation detection module is the core of the demodulator, including: three one-dimensional convolutional neural networks implemented in FPGA to detect π/2, -π/2 and π in the QPSK signal to be demodulated respectively. Type three relative phase changes, and output phase mutation information.

Specifically, referring to FIG. 2 and FIG. 3 , the waveform of the signal to be demodulated is shown in FIG. 2 , and it is easy to know that the relative phase change in the QPSK signal includes three types: π/2 type, -π/2 type and π type. The working process of the demodulator is shown in Figure 3. After the demodulator is powered on, the clock and reset modules give the clock signal and the reset signal in turn, and then AD samples the demodulated signal to form a discrete time sequence. Input to the input buffer block for data buffering and clock domain conversion. Subsequently, the clock domain converted data is input into the phase mutation detection module in the form of a sliding window, and the parameter storage module provides the corresponding network parameters, and the constellation rotation and data inversion modules initialize the IQ data lines; in the phase mutation detection , the phase mutation detection module calculates according to the pre-trained network parameters, and the output rule of the calculation result is: if the phase mutation detection module detects a certain phase mutation in the current input, it outputs 1, otherwise it outputs 0. The output of the phase mutation detection module is a discrete sequence with the same rate as the AD sampling rate, and its shape appears as a pulse when a certain phase mutation occurs; the constellation rotation and data inversion module performs pulse detection on the output sequence of the phase mutation detection module. , the constellation diagram is flipped according to the type of phase mutation. The constellation position corresponding to the previous symbol is the starting point, and it is rotated according to the type of phase change. When a π/2 type phase mutation occurs, it is rotated 90° clockwise. When - The π/2-type phase mutation is rotated 90° counterclockwise. When the π-type phase mutation occurs, it is rotated 180°. The result of the rotation is the constellation position corresponding to the current symbol. According to the constellation position corresponding to the current symbol, the IQ two-way data Then, the IQ two-way data waveform is obtained by flipping the line; then, the synchronous output module samples the IQ two-way data waveform according to the code rate, and outputs the final demodulated data.

In particular, in a specific embodiment of the present invention, a one-dimensional convolutional neural network includes: an input layer, a convolutional layer, a hidden layer and an output layer, as well as auxiliary input buffering, output buffering and control modules.

Specifically, referring to FIG. 4 , the one-dimensional convolutional neural network implemented in the FPGA in the phase mutation detection module includes: an input layer, a convolutional layer, a hidden layer, an output layer, and an auxiliary input buffer, output buffer and control module. . In the input layer, the registers are cascaded to form a sliding window. The convolutional layer includes two physically independent one-dimensional convolution kernels with the same structure. The main constituent elements in the hidden layer and the output layer are neurons. The neuron model is similar, only the number of synapses is different, and the activation function of the neuron adopts the sigmoid function. The input and output buffers are used to buffer the input data and perform clock domain conversion, and the control module is used to control valid signals, and coordinate the parameter storage module to give corresponding parameters in a timely manner.

Specifically, referring to FIG. 5 and FIG. 6 , the convolution layer in the one-dimensional convolutional neural network implemented in the FPGA needs to complete the one-dimensional same convolution operation. The same convolution means that the length of the output vector is equal to the input vector, assuming that the input The length of the vector is σ=M+1, and the length of the convolution kernel is M+1. According to the convolution theory, to obtain an output vector with a length of M+1, the input vector needs to be expanded with a length of M. Generally, 0 is used. For expansion, the expanded input vector with a length of 2M+1 performs a convolution operation with a convolution kernel with a length of M+1, and the result is shown in Figure 5. The convolution operation includes a total of (M+1) 2 multiplication operations, some of which are cases where the multiplier is 0, and the calculation result of this part of the data in the wire frame in Figure 5 has been previously or will be In the subsequent operations, by adding some multiplication results to the time delay network composed of different delay queues, a large number of repeated calculations can be avoided. The structure of the time delay network is shown in Figure 6. In the figure [x ₁ x ₂ ... x _M+1 ] is the current input vector, [w ₁ w ₂ ... w _M+1 ] is the current convolution kernel output by the parameter storage module, D is the delay unit, The result of the convolution operation corresponding to the current input is [y ₁ y ₂ ... y _M+1 ]. Under the control of the FPGA clock, the data can be accurately clocked and delayed with a small resource occupation. With the results on the delay line, on average, each input vector only needs to perform M+1 multiplications to obtain the convolution result.

As shown in Figure 7, the present invention provides a control method of an FPGA-based QPSK neural network demodulator on the basis of the above-mentioned embodiment, including:

Send clock signal and reset signal;

Obtain sampling data by sampling the demodulated signal;

Receive and buffer sampled data, and perform clock domain conversion on the sampled data;

Detect the relative phase change in the sampled data after clock domain conversion, and output phase mutation information;

Receive and process phase mutation information to form baseband data;

Synchronously judge baseband data, generate and output demodulated data.

In particular, in the specific embodiment of the present invention, before sending the clock signal and the reset signal, the method further includes: storing the network parameters in the parameter storage module.

In particular, in the specific embodiment of the present invention, before sampling the to-be-demodulated signal to obtain sampled data, the method further includes: inputting network parameters into the FPGA.

The demodulator proposed by the present invention takes the relative phase sudden change in the QPSK modulation signal as a feature, and uses the phase sudden change detection module implemented in FPGA to perform feature detection on it, and respectively detects three kinds of relative phase changes in the QPSK modulation signal, The constellation rotation and data inversion module implemented in FPGA is used to output the demodulated data waveform according to the type and timing of the phase mutation, and then complete the demodulation. The demodulator proposed by the invention has low parameter complexity and high structural stability, can improve the demodulator's adaptability to special environments through targeted training, and uses a time delay network to perform one-dimensional convolution operations, thereby reducing computational costs. complexity, and improve the efficiency of hardware resource use.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (7)

1. An FPGA-based QPSK neural network demodulator, comprising:

the clock and reset module is used for sending a clock signal and a reset signal;

the AD sampling module is used for sampling a signal to be demodulated to acquire sampling data;

the input buffer module is used for receiving and buffering the sampling data and performing clock domain conversion on the sampling data;

the phase mutation detection module is used for detecting the relative phase change in the sampling data after clock domain conversion and outputting phase mutation information; the phase mutation detection module comprises three one-dimensional convolutional neural networks which are realized in an FPGA (field programmable gate array), the three one-dimensional convolutional neural networks are used for respectively detecting three relative phase changes of pi/2 type, pi/2 type and pi type in a QPSK (quadrature phase shift keying) signal to be demodulated and outputting phase mutation information, and the phase mutation information is a discrete sequence with the same rate as the sampling rate of the AD sampling module and has the shape of a pulse when the phase mutation occurs;

the constellation rotation and data inversion module is used for carrying out pulse detection on the output sequence, rotating a constellation diagram according to the type of phase mutation in the pulse detection to obtain a constellation position corresponding to a current code element, and inverting the IQ two-way data line according to the constellation position corresponding to the current code element to obtain an IQ two-way data waveform;

and the synchronous output module is used for sampling the IQ two-path data waveform according to the code rate, and generating and outputting demodulation data.

2. The demodulator of claim 1, further comprising: and the PCIe interaction module is used for inputting the network parameters into the FPGA.

3. The demodulator of claim 2, further comprising: and the parameter storage module is used for receiving, storing and forwarding the network parameters.

4. The demodulator according to claim 1, wherein the one-dimensional convolutional neural network comprises: an input layer, a convolutional layer, an implicit layer and an output layer, and auxiliary input buffer, output buffer and control module.

5. A control method of a QPSK neural network demodulator based on FPGA is characterized by comprising the following steps:

sending a clock signal and a reset signal;

sampling a signal to be demodulated to obtain sampling data;

receiving and buffering the sampling data, and performing clock domain conversion on the sampling data;

detecting three relative phase changes of pi/2 type, -pi/2 type and pi type in the sampling data after clock domain conversion, and outputting phase mutation information, wherein the phase mutation information is a discrete sequence with the same rate as the sampling rate of the AD sampling module, and has the shape of a pulse when the phase mutation occurs;

performing pulse detection on the output sequence, rotating a constellation diagram according to the type of phase mutation in the pulse detection to obtain a constellation position corresponding to a current code element, and turning the IQ two-way data line according to the constellation position corresponding to the current code element to obtain an IQ two-way data waveform;

and sampling the IQ two-path data waveform according to the code rate, and generating and outputting demodulation data.

6. The method of claim 5, further comprising, prior to sending the clock signal and the reset signal: and storing the network parameters to a parameter storage module.

7. The method of claim 5, prior to acquiring sample data for the signal samples to be demodulated, further comprising: the network parameters are input to the FPGA.

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