CN101969319A - Universal digital dual modulation-demodulation technology in wireless communication - Google Patents
Universal digital dual modulation-demodulation technology in wireless communication Download PDFInfo
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- CN101969319A CN101969319A CN2010102562823A CN201010256282A CN101969319A CN 101969319 A CN101969319 A CN 101969319A CN 2010102562823 A CN2010102562823 A CN 2010102562823A CN 201010256282 A CN201010256282 A CN 201010256282A CN 101969319 A CN101969319 A CN 101969319A
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Abstract
The invention provides a universal digital dual modulation-demodulation technology in wireless communication. The technology comprises a scheme that: a data signal and a voice signal are subjected to spectrum spreading by different PN sequences by a communication signal transmission end, are subjected to code division, and are modulated and demodulated by a modulator and a demodulator respectively; the output data modulated by the modulator is combined with a voice medium frequency signal; the demodulator directly samples the medium frequency signal to realize synchronization of demodulation and clock tracking; and the recovered base band data are input into a master control device. The technology can meet the requirement on high real time and high transmission, and quick synchronous communication application, and has the advantages of simple structure and reliable work.
Description
(1) technical field:
The present invention relates to radio communication modulation-demodulation technique, improve by technological adaptability based on software and radio technique, but the application scenario of extensive use different communication.
(2) background technology
In the existing communication technology, analog communication and digital communication are arranged.At digital communicating field, general data and speech all are to be transmitted by distinct device, i.e. data transmission set and voice transfer equipment; Perhaps adopt the different channels transmission.The advantage of this mode is to realize on engineering simply, but the while has also brought the equipment cost height, frequency efficiency is low, the signal multiplexing degree is low, and the transfer of data real-time is not strong, the shortcoming that efficiency of transmission is low.
In the star-like communication system to multiple spot, require wireless communication system can realize data in real time high efficiency of transmission (finishing the transmission and the receiving course of a given data in certain communication cycle) on one point, the data transmission error rate is not less than 10
-6, be not more than 0.6s lock in time.
(3) summary of the invention
The objective of the invention is provides a kind of general digital formula double modulation demodulation scheme for solving high real-time, high transmission rates and quick synchronous application requirements, and this scheme is:
At the communication signal emitting end data-signal and voice signal being implemented sign indicating number behind different PN sequence spread spectrums divides, carry out modulation and demodulation by a modulator and demodulator respectively again, data of exporting after the modulators modulate and voice intermediate-freuqncy signal are closed the road, demodulator is directly sampled in intermediate-freuqncy signal, realize separating be in harmonious proportion clock tracing synchronously, recover to import master control set behind the base band data.
Described modulator-demodulator comprises complex programmable logic device (CPLD), Field Programmable Gate Array FPGA, the course of work of modulator-demodulator comprises modulation and demodulation two large programs, wherein modulated process comprises that data shunt, phase mapping and state decoding, level produce, export I, Q two-way digital modulation signals, become modulated-analog signal by DA conversion and filtering; Demodulating process comprise if signal sampling, AD conversion, numeral coupling, time-delay demodulation separate difference, low-pass filtering, judgement realize separating be in harmonious proportion clock tracing synchronously, recover base band data, by described complex programmable logic device (CPLD) finish data along separate routes, the function of phase mapping and state decoding, by Field Programmable Gate Array FPGA realize except that above-mentioned data along separate routes, phase mapping and state decoding is, AD is transformed to after the ADC and DA is transformed to DAC repertoire before.
The invention has the beneficial effects as follows:
Can satisfy high real-time, high transmission rates and synchronous communications applications requirement fast, and have simple in structure, the advantage of reliable operation.
(4) description of drawings
Fig. 1 is a general digital formula double modulation demodulation techniques structured flowchart of the present invention;
Fig. 2 is a general digital formula double modulation demodulation techniques modulating part theory diagram of the present invention;
Fig. 3 is a general digital formula double modulation demodulation techniques despread-and-demodulation part theory diagram of the present invention;
Fig. 4 is the theory diagram of differential coding decoding in the general digital formula double modulation demodulation techniques of the present invention;
Fig. 5 is the figure as a result after differential coding decoding time-delay shown in Figure 4 is multiplied each other;
(5) embodiment
Describe concrete structure of the present invention and working condition in detail below in conjunction with pattern.
As shown in Figure 1, general digital formula double modulation demodulation techniques of the present invention are at the communication signal emitting end data-signal and voice signal to be implemented sign indicating number behind different PN sequence spread spectrums to divide, carry out modulation and demodulation by a modulator and demodulator respectively again, data of exporting after the modulators modulate and voice intermediate-freuqncy signal are closed the road, demodulator is directly sampled in intermediate-freuqncy signal, realize separating be in harmonious proportion clock tracing synchronously, recover to import master control set behind the base band data.
Described modulator-demodulator comprises complex programmable logic device (CPLD), Field Programmable Gate Array FPGA, the course of work of modulator-demodulator comprises modulation and demodulation two large programs, as shown in Figure 2, the dotted line top is a modulating part, the below is despreading and demodulation part, wherein modulated process comprises that data shunt, phase mapping and state decoding, level produce, export I, Q two-way digital modulation signals, become modulated-analog signal by DA conversion and filtering; Demodulating process comprises if signal sampling, AD conversion, numeral coupling, postpone demodulation separate difference, low-pass filtering, judgement realize separating be in harmonious proportion clock tracing synchronously, recover base band data, by described complex programmable logic device (CPLD) finish data along separate routes, the function of phase mapping and state decoding, by Field Programmable Gate Array FPGA realize except that above-mentioned data along separate routes, phase mapping and state decoding is, AD is transformed to after the ADC and DA is transformed to DAC repertoire before.
The modulation principle of voice signal and data-signal is consistent, just adopts different PN sequences respectively.
In communication, separate timing and need extract carrier wave with phase-locked loop usually, in this process, can produce the carrier phase ambiguities problem.For addressing this problem, adopt the differential modulation mode, only need that information code current is carried out differential coding and modulate again and get final product, represent ' 1 ' with the variation of front and back code element, invariant representation ' 0 ', I/Q two-way differential coding, differential coding are decoded schematic diagram as shown in Figure 3.
Wherein 3 (A) are differential coding figure, and 3 (B) are decoding figure, and its principle is: input and output are respectively 0,1 binary number, when with 1, after-1 expression 1,0, XOR among the figure becomes multiplying, during system preliminary examination, all carry out zero clearing, so what adopt is that initial reference level is 0 mode,-1 represented 1 after two numbers multiplied each other
And 1 represent 0, the result after time-delay is multiplied each other as shown in Figure 4, originating data is 11100, since second bit, negative peak represents 1, posivtive spike represents 0.
The present invention reconciles conditioning technology by the correlation peak on I or Q road is adjudicated, can obtain bit synchronization information, for improving reliability, to the absolute value summation of I, Q two paths of signals, carry out threshold judgement, equally can obtain bit synchronization information, whenever rule out a peak value, to the clock signal counting, between two peaks, uniformly-spaced produce two positive pulse signals, can obtain synchronizing signal.
Main innovation of the present invention is to adopt duplex MODEM to realize simultaneous data and speech transmission, directly on intermediate-freuqncy signal, sample, digital matched filtering, delay demodulation separate difference, the synchronous of mediation clock tracing separated in realization, recover base band data, and do not adopt the synchronization acquistion of carrier extract, tracking and long code.
Described Field Programmable Gate Array FPGA can select the high-end product of 2,000,000 in Xilinx company for use, selecting this device mainly is to consider from capacity and speed, because matched filter will consume a large amount of resources, and the clock frequency of NCO is higher, reaches 160～240MHz.Complex programmable logic device (CPLD) CPLD can select the XC9572XL of Xilinx company for use.Realize the modulation-demo-demodulation method that the present invention proposes by programming, utilize prior art to make corresponding hardware then, form digital duplex MODEM of the present invention, realize the double modulation demodulating process.
Claims (3)
1. general digital formula double modulation demodulation techniques in the radio communication, it is characterized in that: the scheme of these double modulation demodulation techniques is: at the communication signal emitting end data-signal and voice signal are implemented sign indicating number behind different PN sequence spread spectrums and divide, carry out modulation and demodulation by a modulator and demodulator respectively again, data of exporting after the modulators modulate and voice intermediate-freuqncy signal are closed the road, demodulator is directly sampled in intermediate-freuqncy signal, realize separating be in harmonious proportion clock tracing synchronously, recover to import master control set behind the base band data.
2. general digital formula double modulation demodulation techniques as claimed in claim 1, it is characterized in that: described modulator-demodulator comprises complex programmable logic device (CPLD), Field Programmable Gate Array FPGA, the course of work of modulator-demodulator comprises modulation and demodulation two large programs, wherein modulated process comprises that data shunt, phase mapping and state decoding, level produce, export I, Q two-way digital modulation signals, become modulated-analog signal by DA conversion and filtering; Demodulating process comprises if signal sampling, AD conversion, numeral coupling, postpone demodulation separate difference, your pass filter, judgement realize separating be in harmonious proportion clock tracing synchronously, recover base band data, by described complex programmable logic device (CPLD) finish data along separate routes, the function of phase mapping and state decoding, by Field Programmable Gate Array FPGA realize except that above-mentioned data along separate routes, phase mapping and state decoding is, AD is transformed to after the ADC and DA is transformed to DAC repertoire before.
3. general digital formula double modulation demodulation techniques as claimed in claim 1 is characterized in that: described on-site programmable gate array FPGA is selected 2,000,000 products of Xilinx company for use, and CPLD selects the XC9572XL type product of Xilinx company for use.
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Cited By (16)
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| CN102075472A (en) * | 2011-02-16 | 2011-05-25 | 四川九洲电器集团有限责任公司 | Method for spreading intermediate frequency of OQPSK and despreading and demodulating spread intermediate frequency |
| CN103117771A (en) * | 2013-01-23 | 2013-05-22 | 杭州电子科技大学 | Method for combining uplink of CDMA 2000 digital repeater |
| CN107925435A (en) * | 2015-09-21 | 2018-04-17 | 罗克福安全有限公司 | Systems for Transmitting Sampled Signals Through Imperfect Electromagnetic Pathways |
| CN109981517A (en) * | 2019-01-22 | 2019-07-05 | 西安电子科技大学 | A kind of QPSK neural network demodulation device and its control method based on FPGA |
| US11463125B2 (en) | 2017-03-20 | 2022-10-04 | Hyphy Usa Inc. | Transporting sampled signals over multiple electromagnetic pathways |
| CN116229696A (en) * | 2022-12-30 | 2023-06-06 | 北京遥感设备研究所 | Control command high-speed transmission method and device, storage medium and electronic equipment |
| US11716114B2 (en) | 2020-11-25 | 2023-08-01 | Hyphy Usa Inc. | Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
| US11769468B2 (en) | 2022-01-19 | 2023-09-26 | Hyphy Usa Inc. | Spread-spectrum video transport integration with timing controller |
| US11842671B2 (en) | 2022-03-07 | 2023-12-12 | Hyphy Usa Inc. | Spread-spectrum video transport source driver integration with display panel |
| US11997415B2 (en) | 2021-08-17 | 2024-05-28 | Hyphy Usa Inc. | Sampled analog storage system |
| US12039951B2 (en) | 2021-09-03 | 2024-07-16 | Hyphy Usa Inc. | Spread-spectrum video transport integration with display drivers |
| US12148354B2 (en) | 2021-09-17 | 2024-11-19 | Hyphy Usa Inc. | Spread-spectrum video transport integration with virtual reality headset |
| US12176933B2 (en) | 2021-08-12 | 2024-12-24 | Hyphy Usa Inc. | Distributing staged sampled signals and conveying over electromagnetic pathways |
| US12335086B2 (en) | 2021-07-12 | 2025-06-17 | Hyphy Usa Inc. | Spread-spectrum video transport with quadrature amplitude modulation |
| US12513035B2 (en) | 2022-08-16 | 2025-12-30 | Hyphy Usa Inc. | Spread-spectrum video transport with orthogonal frequency division multiplexing and OFDM video transport |
| US12531007B2 (en) | 2023-02-21 | 2026-01-20 | Hyphy Usa Inc. | Analog video transport to a display panel and source driver integration with display panel |
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| CN102075472A (en) * | 2011-02-16 | 2011-05-25 | 四川九洲电器集团有限责任公司 | Method for spreading intermediate frequency of OQPSK and despreading and demodulating spread intermediate frequency |
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| CN103117771A (en) * | 2013-01-23 | 2013-05-22 | 杭州电子科技大学 | Method for combining uplink of CDMA 2000 digital repeater |
| CN103117771B (en) * | 2013-01-23 | 2015-03-25 | 杭州电子科技大学 | Method for combining uplink of CDMA 2000 digital repeater |
| US11838047B2 (en) | 2015-09-21 | 2023-12-05 | Hyphy Usa Inc. | System for transporting sampled signals over imperfect electromagnetic pathways |
| US12506510B2 (en) | 2015-09-21 | 2025-12-23 | Hyphy Usa Inc. | Analog video transport over imperfect electromagnetic pathways |
| CN107925435A (en) * | 2015-09-21 | 2018-04-17 | 罗克福安全有限公司 | Systems for Transmitting Sampled Signals Through Imperfect Electromagnetic Pathways |
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| US11025292B2 (en) | 2015-09-21 | 2021-06-01 | Hyphy Usa Inc. | System for transporting sampled signals over imperfect electromagnetic pathways |
| US11394422B2 (en) | 2015-09-21 | 2022-07-19 | Hyphy Usa Inc. | System for transporting sampled signals over imperfect electromagnetic pathways |
| US12368467B2 (en) | 2017-03-20 | 2025-07-22 | Hyphy Usa Inc. | Transporting sampled analog signals over multiple electromagnetic pathways |
| US11894869B2 (en) | 2017-03-20 | 2024-02-06 | Hyphy Usa Inc. | Transporting sampled signals over multiple electromagnetic pathways |
| US11463125B2 (en) | 2017-03-20 | 2022-10-04 | Hyphy Usa Inc. | Transporting sampled signals over multiple electromagnetic pathways |
| CN109981517A (en) * | 2019-01-22 | 2019-07-05 | 西安电子科技大学 | A kind of QPSK neural network demodulation device and its control method based on FPGA |
| CN109981517B (en) * | 2019-01-22 | 2020-06-19 | 西安电子科技大学 | QPSK neural network demodulator based on FPGA and control method thereof |
| US11716114B2 (en) | 2020-11-25 | 2023-08-01 | Hyphy Usa Inc. | Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
| US12047112B2 (en) | 2020-11-25 | 2024-07-23 | Hyphy Usa, Inc. | Decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
| US12335086B2 (en) | 2021-07-12 | 2025-06-17 | Hyphy Usa Inc. | Spread-spectrum video transport with quadrature amplitude modulation |
| US12294394B2 (en) | 2021-08-12 | 2025-05-06 | Hyphy Usa Inc. | Distributing staged sampled signals and conveying analog samples over electromagnetic pathways |
| US12176933B2 (en) | 2021-08-12 | 2024-12-24 | Hyphy Usa Inc. | Distributing staged sampled signals and conveying over electromagnetic pathways |
| US11997415B2 (en) | 2021-08-17 | 2024-05-28 | Hyphy Usa Inc. | Sampled analog storage system |
| US12039951B2 (en) | 2021-09-03 | 2024-07-16 | Hyphy Usa Inc. | Spread-spectrum video transport integration with display drivers |
| US12112718B2 (en) | 2021-09-03 | 2024-10-08 | Hyphy Usa Inc. | Analog video transport integration with display drivers |
| US12148354B2 (en) | 2021-09-17 | 2024-11-19 | Hyphy Usa Inc. | Spread-spectrum video transport integration with virtual reality headset |
| US11948536B2 (en) | 2022-01-19 | 2024-04-02 | Hyphy Usa Inc. | Analog video transport integration with timing controller |
| US11769468B2 (en) | 2022-01-19 | 2023-09-26 | Hyphy Usa Inc. | Spread-spectrum video transport integration with timing controller |
| US11842671B2 (en) | 2022-03-07 | 2023-12-12 | Hyphy Usa Inc. | Spread-spectrum video transport source driver integration with display panel |
| US12513035B2 (en) | 2022-08-16 | 2025-12-30 | Hyphy Usa Inc. | Spread-spectrum video transport with orthogonal frequency division multiplexing and OFDM video transport |
| CN116229696A (en) * | 2022-12-30 | 2023-06-06 | 北京遥感设备研究所 | Control command high-speed transmission method and device, storage medium and electronic equipment |
| US12531007B2 (en) | 2023-02-21 | 2026-01-20 | Hyphy Usa Inc. | Analog video transport to a display panel and source driver integration with display panel |
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