CN109962707A - A kind of CMOS combinational logic circuit - Google Patents
A kind of CMOS combinational logic circuit Download PDFInfo
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- CN109962707A CN109962707A CN201910305397.8A CN201910305397A CN109962707A CN 109962707 A CN109962707 A CN 109962707A CN 201910305397 A CN201910305397 A CN 201910305397A CN 109962707 A CN109962707 A CN 109962707A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The present invention provides a kind of CMOS combinational logic circuits, to the combinational logic arithmetic element circuit in standard cell lib that when adder circuit designs, alternative techniques factory is provided.The CMOS combinational logic circuit includes PMOS network and NMOS network, and PMOS network and NMOS network respectively include three transistors.It is realized by less transistorLogical operation function, reduces area, reduces power consumption, while shortening path, reduces transmission delay.
Description
Technical field
The present invention relates to a kind of circuit unit structure, in particular to a kind of standard cell lib provided to alternative techniques factory
In combinational logic arithmetic element circuit Small-sized C MOS combinational logic arithmetic element circuit.
Background technique
When designing the core chips in large-scale high performance computing service device, in current design cycle, from front end RTL (electricity
Resistor transistor logic circuit) it is designed into the realization of rear end, it is all based on the standard cell lib of technique factory offer, although designing in this way
Period is short, but can resource it is limited (only technique factory provide standard cell lib), lack flexibility.Work as high-performance calculation
When server is to power consumption and very sensitive speed, it is difficult to meet the performance requirement of server using such tool processing mode, because
The combinational logic fortune that this designer needs some low-power consumption or the logic unit that can be raised speed to come in alternate standard cell library
Element circuit is calculated, to reduce power consumption and improve speed.
In the chip design of high performance computing service device, pass through the comprehensive circuit meshwork list structure of analysis RTL code, discovery
There is a logical operation in critical path in adder structure, as shown in Figure 1, when being RTL design in 32 adder structures
The logic circuit structure of logical operation in critical path, using 3 basic logic gates: NAND gate, NOT gate wrap in total with door
12 transistors are contained, input signal A and B first carry out that logical AND is non-, then carry out logical AND with the reverse phase of input signal C again
The calculation function of operation, realization isThe transmission time of this structure has two-level logic gate delay.If can design
One logic unit can substitute this unit: not increasing area, while reducing power consumption and transmission time again, improve adder
Speed realizes that the performance of server improves.This is significantly.
Summary of the invention
The present invention provides a kind of circuit unit structure, is realizingWhile calculation function, area is smaller, function
Consume smaller, speed faster, the speed for realizing adder improves.
The present invention provides a kind of CMOS combinational logic circuit, including PMOS network and NMOS network, the PMOS networks
In include:
The first transistor is PMOS tube, and the grid G of the first transistor is connect with the first input signal, and described first is brilliant
The source S of body pipe is connect with supply voltage, the drain D of the first transistor and drain D, the third transistor of second transistor
Source S connection；
Second transistor is PMOS tube, and the grid G of the second transistor is connect with the second input signal, and described second is brilliant
The source S of body pipe is connect with supply voltage, the drain D of the second transistor and drain D, the third transistor of the first transistor
Source S connection；
Third transistor is PMOS tube, and the grid G of the third transistor is connect with third input signal, and the third is brilliant
The source S of body pipe and the drain D of the first transistor, the drain D of second transistor connect, the drain D of the third transistor with
The drain D of 4th transistor, the drain D of the 5th transistor, output signal connection；
Include: in the NMOS network
4th transistor is NMOS tube, and the grid G of the 4th transistor is connect with third input signal, and the described 4th is brilliant
The drain D and the drain D of third transistor of body pipe, the drain D of the 5th transistor, output signal connection, the 4th transistor
Source S connect with ground signalling；
5th transistor is NMOS tube, and the grid G of the 5th transistor is connect with the first input signal, and the described 5th is brilliant
The drain D and the drain D of third transistor of body pipe, the drain D of the 4th transistor, output signal connection, the 5th transistor
Source S connect with the drain D of the 6th transistor；
6th transistor is NMOS tube, and the grid G of the 6th transistor is connect with the second input signal, and the described 6th is brilliant
The drain D of body pipe is connect with the source S of the 5th transistor, and the source S of the 6th transistor is connect with ground signalling.
The supply voltage is high level voltage, and the ground signalling is low level voltage.
When the first input signal, the second input signal, third input signal are low level, output signal is high level；
First input signal, third input signal are low level, and when the second input signal is high level, output signal is high level；The
One input signal, the second input signal are low level, and when third input signal is high level, output signal is low level；First
Input signal is low level, and when third input signal, the second input signal are high level, output signal is low level；First is defeated
Entering signal is high level, and when the second input signal, third input signal are low level, output signal is high level；First input
Signal, the second input signal are high level, and when third input signal is low level, output signal is low level；First input letter
Number, third input signal be high level, the second input signal be low level when, output signal is low level；First input signal,
When second input signal, third input signal are high level, output signal is low level.
The CMOS combinational logic circuit is in the circuit design of adder.
Circuit unit structure provided by the invention has only used the half of 12 transistors in Fig. 1 structure, passes through less crystalline substance
Body pipe realizes same function operation, reduces area, reduces power consumption, while shortening path, reduces transmission delay.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 isLogic circuit structure；
Fig. 2 is circuit unit structure of the invention；
Fig. 3 is the input/output relation table of comparisons of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.
As shown in Figure 1, being realized the present invention provides a kind of circuit unit structureLogical operation function.
In PMOS network, the first transistor, second transistor and third transistor are all PMOS tube.The first transistor P0's
Grid G is connect with the first input signal A, and source S is connect with supply voltage VDD, the drain D of drain D and second transistor P1, the
The source S of three transistor P2 connects；The grid G of second transistor P1 is connect with the second input signal B, source S and supply voltage
VDD connection, drain D are connect with the source S of the drain D of the first transistor P0, third transistor P2；The grid of third transistor P2
G is connect with third input signal C, and source S is connect with the drain D of the drain D of the first transistor P0, second transistor P1, drain D
It is connect with the drain D of the 4th transistor N0, the drain D of the 5th transistor N1, output signal Y.When third input signal C is low electricity
Usually, third transistor P2 is connected, and the value of output signal Y depends on the first input signal A and the second input signal B, as long as the
As soon as one of them is low level to input signal A and the second input signal B, have in the first transistor P0 and second transistor P1 to
Few meeting conducting, output signal Y are connected to supply voltage VDD, realize output signal Y high level.As the first input signal A
It is simultaneously high level with the second input signal B, the first transistor P0 and second transistor P1 are turned off simultaneously, the 5th transistor N1
It being simultaneously turned on the 6th transistor N2, output signal Y is connected to ground signalling GND, and output signal Y is low level, that is,
It realizesMiddle C=0,Function.
In NMOS network, the 4th transistor, the 5th transistor and the 6th transistor are all NMOS tube.4th transistor N0's
Grid G is connect with third input signal C, the drain D of drain D and third transistor P2, the drain D of the 5th transistor N1, output
Signal Y connection, source S are connect with ground signalling GND；The grid G of 5th transistor N1 is connect with the first input signal A, drain D
It is connect with the drain D of third transistor P2, the drain D of the 4th transistor N0, output signal Y, source S is with the 6th transistor N2's
Drain D connection；The grid G of 6th transistor N2 is connect with the second input signal B, and the source S of drain D and the 5th transistor N1 connect
It connects, source S is connect with ground signalling GND.NMOS tube N1 and N2 series connection, it is then in parallel with N0 again.When third input signal C is height
When level, the 4th transistor N0 pipe conducting, output signal Y is connected to ground signalling GND, and the first input signal A and second is defeated
Enter signal B does not all influence to be high and low, and output signal Y is low level, that is, is realizedMiddle C=1Function.
Contrast relationship such as Fig. 3 institute of first input signal A, the second input signal B, third input signal C and output signal Y
Show.When the first input signal A, the second input signal B, third input signal C are low level, output signal Y is high level；The
One input signal A, third input signal C are low level, and when the second input signal B is high level, output signal Y is high level；
First input signal A, the second input signal B are low level, and when third input signal C is high level, output signal Y is low electricity
It is flat；First input signal A is low level, and when third input signal C, the second input signal B are high level, output signal Y is low
Level；First input signal A is high level, and when the second input signal B, third input signal C are low level, output signal Y is
High level；First input signal A, the second input signal B are high level, when third input signal C is low level, output signal Y
For low level；First input signal A, third input signal C are high level, when the second input signal B is low level, output signal
Y is low level；When first input signal A, the second input signal B, third input signal C are high level, output signal Y is low electricity
It is flat.
Circuit unit structure provided by the invention has only used the half of 12 transistors in Fig. 1 structure, passes through less crystalline substance
Body pipe realizes same function operation, reduces area, reduces power consumption, while shortening path, reduces transmission delay.
It is described in detail in addition, being provided for the embodiments of the invention CMOS combinational logic circuit structure above, this
Apply that a specific example illustrates the principle and implementation of the invention in text, the explanation of above example is only intended to
It facilitates the understanding of the method and its core concept of the invention；At the same time, for those skilled in the art, think of according to the present invention
Think, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as pair
Limitation of the invention.
Claims (4)
1. a kind of CMOS combinational logic circuit, including PMOS network and NMOS network, it is characterised in that:
Include: in the PMOS network
The first transistor is PMOS tube, and the grid G of the first transistor is connect with the first input signal, the first transistor
Source S connect with supply voltage, the source of the drain D of the drain D of the first transistor and second transistor, third transistor
Pole S connection；
Second transistor is PMOS tube, and the grid G of the second transistor is connect with the second input signal, the second transistor
Source S connect with supply voltage, the source of the drain D of the drain D of the second transistor and the first transistor, third transistor
Pole S connection；
Third transistor is PMOS tube, and the grid G of the third transistor is connect with third input signal, the third transistor
Source S and the drain D of the first transistor, the drain D of second transistor connect, the drain D of the third transistor and the 4th
The drain D of transistor, the drain D of the 5th transistor, output signal connection；
Include: in the NMOS network
4th transistor is NMOS tube, and the grid G of the 4th transistor is connect with third input signal, the 4th transistor
Drain D and the drain D of third transistor, the drain D of the 5th transistor, output signal connect, the source of the 4th transistor
Pole S is connect with ground signalling；
5th transistor is NMOS tube, and the grid G of the 5th transistor is connect with the first input signal, the 5th transistor
Drain D and the drain D of third transistor, the drain D of the 4th transistor, output signal connect, the source of the 5th transistor
Pole S is connect with the drain D of the 6th transistor；
6th transistor is NMOS tube, and the grid G of the 6th transistor is connect with the second input signal, the 6th transistor
Drain D connect with the source S of the 5th transistor, the source S of the 6th transistor is connect with ground signalling.
2. CMOS combinational logic circuit as described in claim 1, it is characterised in that: the supply voltage is high level voltage,
The ground signalling is low level voltage.
3. CMOS combinational logic circuit as described in claim 1, it is characterised in that: when the first input signal, the second input letter
Number, third input signal be low level when, output signal is high level；First input signal, third input signal are low level,
When second input signal is high level, output signal is high level；First input signal, the second input signal are low level, the
When three input signals are high level, output signal is low level；First input signal is low level, third input signal, second
When input signal is high level, output signal is low level；First input signal is high level, and the second input signal, third are defeated
Enter signal be low level when, output signal is high level；First input signal, the second input signal are high level, third input
When signal is low level, output signal is low level；First input signal, third input signal are high level, the second input letter
Number be low level when, output signal is low level；First input signal, the second input signal, third input signal are high level
When, output signal is low level.
4. CMOS combinational logic circuit as claimed any one in claims 1 to 3, it is characterised in that: the CMOS combination is patrolled
Circuit is collected in the circuit design of adder.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114793114A (en) * | 2021-01-26 | 2022-07-26 | 深圳比特微电子科技有限公司 | Composite logic gate circuit and mining machine equipment |
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| CN114793114A (en) * | 2021-01-26 | 2022-07-26 | 深圳比特微电子科技有限公司 | Composite logic gate circuit and mining machine equipment |
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