CN109888064A - The growing method of LED epitaxial slice - Google Patents
The growing method of LED epitaxial slice Download PDFInfo
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- CN109888064A CN109888064A CN201910069091.7A CN201910069091A CN109888064A CN 109888064 A CN109888064 A CN 109888064A CN 201910069091 A CN201910069091 A CN 201910069091A CN 109888064 A CN109888064 A CN 109888064A
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Abstract
The invention discloses a kind of growing methods of LED epitaxial slice, belong to technical field of semiconductors.The growing method includes: to provide a substrate；Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer on substrate；P type semiconductor layer includes the multiple sublayers stacked gradually, and the sublayer of first stacking is grown in the following way: opening magnesium source and nitrogen source, forms gallium vacancy on the surface of active layer；Indium source and gallium source are opened, magnesium is activated；Indium source is closed, forms sublayer on the surface of active layer；Other sublayers are grown in the following way: being closed gallium source, formed gallium vacancy on the surface of established sublayer；Gallium source is opened, forms sublayer on the surface of established sublayer；The thickness of multiple sublayers is gradually increased along the stacking direction of multiple sublayers, and the growth temperature of the doping concentration of magnesium and multiple sublayers gradually rises along the stacking direction of multiple sublayers in multiple sublayers.The present invention can effectively increase the number of cavities of p type semiconductor layer offer.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of growing method of LED epitaxial slice.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is that one kind can be converted to electric energy
The semiconductor diode of luminous energy.New Solid lighting source as one kind efficiently, environmentally friendly, green, LED is by extensive rapidly
It applies in fields such as traffic lights, automobile interior exterior lamp, landscape light in city, cell phone back light sources on ground.The core component of LED is core
Piece, the luminous efficiency for improving chip is the target constantly pursued in LED application process.
Chip includes epitaxial wafer and the electrode that extension on piece is arranged in.Existing LED epitaxial wafer includes substrate, buffer layer, N
Type semiconductor layer, active layer and p type semiconductor layer, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer stack gradually
On substrate.Substrate is for providing the surface of epitaxial growth, and buffer layer for providing the nuclearing centre of epitaxial growth, partly lead by N-type
Body layer is for providing the electronics of recombination luminescence, and p type semiconductor layer is for providing the hole of recombination luminescence, and active layer is for carrying out electricity
The recombination luminescence of son and hole.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The activation efficiency that the magnesium doping in hole is provided in p type semiconductor layer is very low, leads to the number of cavities for injecting active layer
It is significantly limited in active layer much smaller than the electron amount of injection active layer in addition the rate travel of electronics is much larger than hole
The recombination luminescence of electrons and holes influences the luminous efficiency of LED.Although theoretically in p type semiconductor layer magnesium doping concentration and P
The number of cavities that p type semiconductor layer provides when the growth temperature of type semiconductor layer is higher is more, but actually there are self-complementary for magnesium
Repay effect, in p type semiconductor layer the doping concentration of magnesium too it is high can not also achieve one's goal generate more hole, while p type semiconductor layer
Growth temperature it is too high active layer can be damaged, the luminous efficiency of LED can not be improved number of cavities increase.
Summary of the invention
The embodiment of the invention provides a kind of growing methods of LED epitaxial slice, are able to solve prior art hole
Negligible amounts, the problem of influencing LED luminous efficiency.The technical solution is as follows:
The embodiment of the invention provides a kind of growing method of LED epitaxial slice, the growing method includes:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate；
Wherein, the p type semiconductor layer includes the multiple sublayers stacked gradually, and the sublayer of first stacking is using such as
Under type growth:
Magnesium source and nitrogen source are opened, forms gallium vacancy on the surface of the active layer；
Indium source and gallium source are opened, magnesium is activated；
Indium source is closed, forms the sublayer on the surface of the active layer；
Other sublayers in addition to the sublayer being laminated in the multiple sublayer except first are given birth in the following way
It is long:
Gallium source is closed, forms gallium vacancy on the surface of the established sublayer；
Gallium source is opened, forms the sublayer on the surface of the established sublayer；
The thickness of the multiple sublayer is gradually increased along the stacking direction of the multiple sublayer, magnesium in the multiple sublayer
Doping concentration gradually rises along the stacking direction of the multiple sublayer, and the growth temperature of the multiple sublayer is along the multiple sublayer
Stacking direction gradually rise.
Optionally, the elevation amplitude of the growth temperature of the multiple sublayer and the doping concentration of magnesium in the multiple sublayer
It is directly proportional to increase multiple.
Further, in the two neighboring sublayer, the growth temperature of the sublayer being laminated afterwards is than described in being first laminated
The growth temperature of sublayer is 5 DEG C high~and 30 DEG C.
Further, in the two neighboring sublayer, the doping concentration of magnesium is first laminated in the sublayer that is laminated afterwards
1.5 times of the doping concentration of magnesium in the sublayer~5 times.
Optionally, the raising for increasing the doping concentration of magnesium in multiple and the multiple sublayer of the thickness of the multiple sublayer
Multiple is identical.
Further, in the two neighboring sublayer, the sublayer that is laminated afterwards with a thickness of the sublayer being first laminated
1.5 times~4 times of thickness.
Optionally, the when a length of 5s~20s in gallium vacancy is formed.
Optionally, the quantity of the multiple sublayer is 3~8.
Optionally, the active layer includes the multiple periodic structures stacked gradually, and each periodic structure includes successively
The Quantum Well and quantum of stacking are built, and the material of the Quantum Well uses the gallium nitride of doped indium, and the material that the quantum is built uses
Undoped gallium nitride.
Further, the doping concentration of indium is indium in the Quantum Well in the gallium indium nitride layer formed when activating to magnesium
Doping concentration 1/20~1/10.
Technical solution provided in an embodiment of the present invention has the benefit that
By the way that the growth of p type semiconductor layer is divided into multistage, the magnesium source of a period of time is all passed through before every section of growth in advance
And nitrogen source, gallium vacancy is formed in the growing surface of sublayer, magnesium atom can be promoted to mix in subsequent growth, thus in p-type half
When the doping concentration of magnesium and the growth temperature of p type semiconductor layer increase in conductor layer, the self-compensation mechanism of magnesium is avoided partly to lead p-type
Limitation caused by number of cavities increases in body layer.In such a situa-tion, then gradually rise magnesium in multiple sublayers doping it is dense
The growth temperature of degree and multiple sublayers, the growth temperature of sublayer is higher, and the activation efficiency of magnesium is higher, therefore the growth temperature of sublayer
It cooperates with the doping concentration of magnesium in sublayer, the integrally provided number of cavities of p type semiconductor layer can be effectively increased；P simultaneously
The growth temperature of sublayer in type semiconductor layer close to active layer is lower, can avoid destruction of the high temperature to active layer as far as possible.
And cooperate the thickness change of multiple sublayers and the doping concentration and growth temperature of magnesium, close to the growth of the sublayer of active layer
Temperature is lower, and crystal quality is poor, and defect concentration is big, uses lesser thickness at this time, is conducive to fill and lead up defect, to reduce p-type
The defect concentration of semiconductor layer entirety；With the growth temperature of sublayer and wherein, the doping concentration of magnesium is gradually risen simultaneously, accordingly
Increase the thickness of sublayer, it is ensured that enough magnesium nitrogen ratios further increase the integrally provided number of cavities of p type semiconductor layer.
In addition, first opening indium source before first sublayer is grown, being activated to magnesium, can change at p type semiconductor layer formation initial stage
Become the form of covalent bond in compound, promotes magnesium atom that gallium atom and nitrogen-atoms is replaced to form covalent bond to generate hole, herein
On the basis of, the magnesium atom in p type semiconductor layer being subsequently formed can also be formed easily altogether instead of gallium atom and nitrogen-atoms
Valence link and generate hole, on the whole increase p type semiconductor layer provide number of cavities.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of growing method of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of the source MO open and-shut mode in p type semiconductor layer growth course provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of growing methods of LED epitaxial slice.Fig. 1 mentions for the embodiment of the present invention
A kind of flow chart of the growing method of the LED epitaxial slice supplied.Referring to Fig. 1, which includes:
Step 101: a substrate is provided.
Optionally, which may include:
Controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure be 200torr~500torr (preferably
350torr), 5 minutes~6 minutes (preferably 5.5 minutes) annealings are carried out to substrate in hydrogen atmosphere.
The surface for cleaning substrate through the above steps avoids being conducive to the life for improving epitaxial wafer in impurity incorporation epitaxial wafer
Long quality.
Optionally, the material of substrate can use sapphire (main material is aluminum oxide), if crystal orientation is [0001]
Sapphire.
Step 102: grown buffer layer on substrate.
Optionally, the material of buffer layer can use undoped gallium nitride or aluminium nitride.Further, buffer layer
Thickness can be 15nm~30nm, preferably 25nm.
Illustratively, which may include:
Controlled at 530 DEG C~560 DEG C (preferably 545 DEG C), pressure be 200torr~500torr (preferably
350torr), grown buffer layer on substrate.
Optionally, after step 102, which can also include:
Undoped gallium nitride layer is grown, on the buffer layer to alleviate lattice mismatch generation between substrate material and gallium nitride
Stress and defect provide crystal quality preferable growing surface for epitaxial wafer main structure.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy first in patterned substrate, because
This is also referred to as low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again, will form multiple mutually independent three
Island structure is tieed up, referred to as three-dimensional nucleating layer；Then it is carried out between each three-dimensional island structure on all three-dimensional island structures
The cross growth of gallium nitride forms two-dimension plane structure, referred to as two-dimentional retrieving layer；The finally high growth temperature one on two-dimensional growth layer
The thicker gallium nitride of layer, referred to as intrinsic gallium nitride layer.By three-dimensional nucleating layer, two-dimentional retrieving layer and intrinsic gallium nitride in the present embodiment
Layer is referred to as undoped gallium nitride layer.
Further, the thickness of undoped gallium nitride layer can be 2 μm~3.5 μm, preferably 2.75 μm.
Illustratively, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure be 200torr~600torr (preferably
400torr), undoped gallium nitride layer is grown on the buffer layer.
Step 103: growing n type semiconductor layer on the buffer layer.
Optionally, the material of n type semiconductor layer can use the gallium nitride of n-type doping (such as silicon or germanium).Further,
The thickness of n type semiconductor layer can be 2 μm~3 μm, preferably 2.5 μm.The doping concentration of N type dopant in n type semiconductor layer
It can be 1018/cm3~1020/cm3, preferably 1019/cm3。
Illustratively, which may include:
Controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure be 200torr~300torr (preferably
250torr), n type semiconductor layer is grown on the buffer layer.
It should be noted that n type semiconductor layer, which is grown in, not to be mixed if growth has undoped gallium nitride layer on buffer layer
On miscellaneous gallium nitride layer.
Optionally, after step 103, which can also include:
The growth stress releasing layer on n type semiconductor layer, with lattice mismatch between release liners material and epitaxial material
The stress of generation avoids stress from extending in active layer the recombination luminescence for influencing electrons and holes.
Step 104: active layer is grown on n type semiconductor layer.
In the present embodiment, active layer may include the multiple periodic structures stacked gradually, each periodic structure include according to
The Quantum Well and quantum of secondary stacking are built, and the material of Quantum Well uses the gallium nitride (InGaN) of doped indium, and the material that quantum is built uses
Undoped gallium nitride (GaN).What is finally grown in active layer is undoped gallium nitride layer, is conducive to form gallium sky on surface
Position, avoids the adverse effect of the self-compensation mechanism of magnesium.
Further, the thickness of Quantum Well can be 2nm~3nm, preferably 2.5nm；The thickness that quantum is built can be 8nm
~11nm, preferably 9.5nm；The quantity of Quantum Well is identical as the quantity that quantum is built, and the quantity that quantum is built can be 11~13
It is a, preferably 12；The thickness of active layer can be 130nm~160nm, preferably 145nm.
Illustratively, which may include:
Controlled at 760 DEG C~780 DEG C (preferably 770 DEG C), pressure 200torr, grown quantum trap；
Controlled at 860 DEG C~890 DEG C (preferably 875 DEG C), pressure 200torr, grown quantum is built.
It should be noted that Quantum Well and quantum are built according to above-mentioned condition alternating growth, active layer can be formed.If N
Growth has stress release layer in type semiconductor layer, then active layer is grown on stress release layer.
Optionally, after step 104, which can also include:
Electronic barrier layer is grown on active layer, carries out non-spoke with hole into p type semiconductor layer to avoid electron transition
It penetrates compound, reduces the luminous efficiency of LED.
Further, the material of electronic barrier layer can be using the aluminium gallium nitride alloy (AlGaN) of p-type doping, such as AlyGa1-yN,
0.15 < y < 0.25；The thickness of electronic barrier layer can be 30nm~50nm, preferably 40nm.
Illustratively, electronic barrier layer is grown on active layer, may include:
Controlled at 930 DEG C~970 DEG C (preferably 950 DEG C), pressure 100torr grows electronics on active layer
Barrier layer.
Optionally, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer causes in active layer to avoid the higher growth temperature of electronic barrier layer
Phosphide atom is precipitated, and influences the luminous efficiency of light emitting diode.
Further, the material of low temperature P-type layer can be the gallium nitride of p-type doping；The thickness of low temperature P-type layer can be
10nm~50nm, preferably 30nm；The doping concentration of P-type dopant can be 10 in low temperature P-type layer18/cm3~1020/cm3, excellent
It is selected as 1019/cm3。
Illustratively, the growing low temperature P-type layer on active layer may include:
Controlled at 600 DEG C~850 DEG C (preferably 750 DEG C), pressure be 100torr~600torr (preferably
300torr), the growing low temperature P-type layer on active layer.
Step 105: the growing P-type semiconductor layer on active layer, p type semiconductor layer include the multiple sublayers stacked gradually.
In the present embodiment, the sublayer of first stacking is grown in the following way:
Magnesium source and nitrogen source are opened, forms gallium vacancy on the surface of active layer；
Indium source and gallium source are opened, magnesium is activated；
Indium source is closed, forms sublayer on the surface of active layer.
Other sublayers in addition to the sublayer being laminated in multiple sublayers except first are grown in the following way:
Gallium source is closed, forms gallium vacancy on the surface of established sublayer；
Indium source is opened, forms sublayer on the surface of established sublayer.
The thickness of multiple sublayers is gradually increased along the stacking direction of multiple sublayers, and the doping concentration of magnesium is along more in multiple sublayers
The stacking direction of a sublayer gradually rises, and the growth temperature of multiple sublayers gradually rises along the stacking direction of multiple sublayers.
Fig. 2 is the schematic diagram of the source MO open and-shut mode in p type semiconductor layer growth course provided in an embodiment of the present invention.Such as figure
Shown in 2, in one sublayer of growth regulation, magnesium source and nitrogen source are first opened, indium source and gallium source are in close state at this time；Indium is opened again
Source and gallium source, magnesium source and nitrogen source are also at opening state at this time；Indium source is finally closed, gallium source, nitrogen source and magnesium source are in and beat at this time
Open state.When then continuing sublayer after growth, gallium source is first closed, magnesium source and nitrogen source are kept open at this time；Gallium source is opened again,
Magnesium source and nitrogen source are in the open state at this time.
In practical applications, the increase of molecular layers thick can be realized by gradually extending the growth time of sublayer；It can lead to
The flow for increasing magnesium source is crossed, realizes the raising of magnesium doping concentration.
The embodiment of the present invention is all passed through one before every section of growth by the way that the growth of p type semiconductor layer is divided into multistage in advance
The magnesium source of section time and nitrogen source form gallium vacancy in the growing surface of sublayer, magnesium atom can be promoted to mix in subsequent growth,
When increasing to the doping concentration of magnesium in p type semiconductor layer and the growth temperature of p type semiconductor layer, the self compensation of magnesium is avoided to imitate
Cope with the limitation caused by number of cavities increases in p type semiconductor layer.In such a situa-tion, it then gradually rises in multiple sublayers
The growth temperature of the growth temperature of the doping concentration of magnesium and multiple sublayers, sublayer is higher, and the activation efficiency of magnesium is higher, therefore sublayer
Growth temperature and sublayer in magnesium doping concentration cooperate, the integrally provided hole of p type semiconductor layer can be effectively increased
Quantity；Growth temperature simultaneously in p type semiconductor layer close to the sublayer of active layer is lower, high temperature can be avoided to active as far as possible
The destruction of layer.And cooperate the thickness change of multiple sublayers and the doping concentration and growth temperature of magnesium, close to active layer
The growth temperature of sublayer is lower, and crystal quality is poor, and defect concentration is big, uses lesser thickness at this time, is conducive to fill and lead up defect,
To reduce the defect concentration of p type semiconductor layer entirety；With the growth temperature of sublayer and wherein, the doping concentration of magnesium is gradually simultaneously
It increases, increases accordingly the thickness of sublayer, it is ensured that it is integrally provided to further increase p type semiconductor layer for enough magnesium nitrogen ratios
Number of cavities.In addition, first open indium source before first sublayer is grown, magnesium is activated, it can be in p type semiconductor layer
Formation initial stage changes the form of covalent bond in compound, promotes magnesium atom that gallium atom is replaced to form covalent bond with nitrogen-atoms to generate
Hole, on this basis, the magnesium atom in p type semiconductor layer being subsequently formed can also easily replace gallium atom and nitrogen former
Son forms covalent bond and generates hole, increases the number of cavities that p type semiconductor layer provides on the whole.
Optionally, the elevation amplitude of the growth temperature of multiple sublayers can be with the raising of the doping concentration of magnesium in multiple sublayers
Multiple is directly proportional.The elevation amplitude of multiple sublayer growth temperatures is directly proportional to the wherein raising multiple of magnesium doping concentration, and the two is same
Step increases, and mutual cooperation is preferable, and the increase effect of number of cavities becomes apparent in final p type semiconductor layer.
Further, in two neighboring sublayer, the growth temperature for the sublayer being laminated afterwards can be than the life for the sublayer being first laminated
Long temperature is 5 DEG C high~and 30 DEG C.If the difference of two neighboring sublayer growth temperature, may be due to growth temperature less than 5 DEG C
Change number of cavities smaller that p type semiconductor layer offer to be provided；If the difference of two neighboring sublayer growth temperature
Value is greater than 30 DEG C, then may cause adverse effect to crystal growth since the change of growth temperature is larger, reduce epitaxial wafer
Crystal quality.
Further, in two neighboring sublayer, the growth temperature for the sublayer being laminated afterwards can be than the sublayer being first laminated
Growth temperature is 10 DEG C high~30 DEG C, such as 20 DEG C, realize that effect is good.
Illustratively, the growth temperature of sublayer can be 880 DEG C~980 DEG C.For example, the growth temperature of sublayer can be from
900 DEG C gradually rise to 960 DEG C.
Further, in two neighboring sublayer, the doping concentration of magnesium can be the sublayer that is first laminated in the sublayer that is laminated afterwards
1.5 times of the doping concentration of middle magnesium~5 times.It, may be by if the ratio between doping concentration of magnesium is less than 1.5 in two neighboring sublayer
Number of cavities smaller that p type semiconductor layer offer to be provided is differed in the doping concentration of magnesium；If two neighboring son
The ratio between doping concentration of magnesium is greater than 5 in layer, then may differ larger due to the doping concentration of magnesium and cause to crystal growth bad
It influences, reduces the crystal quality of epitaxial wafer.
Further, in two neighboring sublayer, the doping concentration of magnesium can be the son that is first laminated in the sublayer that is laminated afterwards
1.5 times~3 times of the doping concentration of magnesium in layer, such as 2.5 times realize that effect is good.
Illustratively, the doping concentration of magnesium can be 10 in sublayer18/cm3~1020/cm3.For example, in sublayer magnesium doping
Concentration can be from 2*1018/cm3It gradually rises to 8*1019/cm3。
Optionally, the increase multiple of the thickness of multiple sublayers can be with the raising multiple of the doping concentration of magnesium in multiple sublayers
It is identical.The increase multiple of multiple molecular layers thicks is identical as the wherein raising multiple of magnesium doping concentration, the synchronous variation of the two, mutually it
Between cooperation it is preferable, the increase effect of number of cavities is preferable in final p type semiconductor layer, the crystal quality of epitaxial wafer entirety also compared with
It is good.
Further, in two neighboring sublayer, the thickness for the sublayer being laminated afterwards can be the thickness for the sublayer being first laminated
1.5 times~4 times.If the ratio between thickness of two neighboring sublayer less than 1.5 or greater than 4, possibly can not be effectively matched sublayer
The variation of the doping concentration of middle magnesium,
Further, in two neighboring sublayer, the thickness for the sublayer being laminated afterwards can be the thickness for the sublayer being first laminated
1.5 times~3 times, such as 2.5 times, realize effect it is good.
Illustratively, the thickness of p type semiconductor layer can be 80nm~200nm, such as 140nm；The thickness of sublayer can be
10nm~30nm is such as gradually increased from 10nm to 25nm.
Optionally, the duration for forming gallium vacancy can be 5s~20s.If the duration for forming gallium vacancy is less than 5s, can
It can not be effectively formed gallium vacancy since the processing time is shorter, cause the increase of number of cavities in p type semiconductor layer unobvious；
If the duration for forming gallium vacancy is greater than 20s, the waste of resource may be led to since the processing time is too long, it is unnecessary to increase
Production cost.
Further, the duration for forming gallium vacancy can be 5s~15s, such as 10s, realize that effect is good.
In practical applications, the duration for gallium vacancy being formed on the growing surface of multiple sublayers can be along the stacking of multiple sublayers
Direction gradually extends, alternatively, the flow for forming the gallium vacancy source Shi Mei on the growing surface of multiple sublayers can be along multiple sublayers
Stacking direction gradually increases, to gradually increase the formation effect in gallium vacancy, with the growth temperatures of multiple sublayers and wherein magnesium
Doping concentration gradually rises matching, and the increase effect of number of cavities in p type semiconductor layer is made to reach highest.
Optionally, the quantity of multiple sublayers can be 3~8.If the quantity of multiple sublayers, may less than 3
The growth temperature of each sublayer, thickness and the wherein doping concentration of magnesium can not be effectively adjusted since the quantity of sublayer is very little,
Cause the increase effect of number of cavities in p type semiconductor layer unobvious；If the quantity of multiple sublayers is greater than 8, may be to P
The increase of number of cavities helps less, to will cause the adverse effects such as production cost increase instead in type semiconductor layer.
Further, the quantity of multiple sublayers can be 3~6, such as 4, realize that effect is good.
Optionally, the doping concentration of indium can be indium in Quantum Well in the gallium indium nitride layer formed when activating to magnesium
The 1/20~1/10 of doping concentration.If the doping concentration of indium is less than 1/ of the doping concentration of indium in Quantum Well in gallium indium nitride layer
20, then it may cannot achieve the activation of magnesium since the doping concentration of indium is lower, influence the formation in hole in p type semiconductor layer；
If the doping concentration of indium is greater than 1/10 of the doping concentration of indium in Quantum Well in gallium indium nitride layer, may be due to the doping of indium
Concentration is higher and causes poor crystal quality, influences the adverse effects such as hole injection active layer.
It should be noted that p type semiconductor layer is grown in electronic blocking if growth has electronic barrier layer on active layer
On layer.
Optionally, after step 105, which can also include:
Contact layer is grown, on p type semiconductor layer with thin with the electrode or electrically conducting transparent that are formed in chip fabrication technique
Ohmic contact is formed between film.
Further, the material of contact layer can be using the InGaN or gallium nitride of p-type doping；The thickness of contact layer
It can be 5nm~300nm, preferably 100nm；The doping concentration of P-type dopant can be 10 in contact layer21/cm3~1022/
cm3, preferably 5*1021/cm3。
Illustratively, contact layer is grown on p type semiconductor layer, may include:
Controlled at 850 DEG C~1050 DEG C (preferably 950 DEG C), pressure be 100torr~300torr (preferably
200torr), contact layer is grown on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 650 DEG C~850 DEG C (preferably
It is 750 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again
The temperature of epitaxial wafer is reduced to room temperature.
Control temperature, pressure each mean temperature, pressure in the reaction chamber of control growth epitaxial wafer, and specially metal is organic
Compound chemical gaseous phase deposition (English: Metal-organic Chemical Vapor Deposition, referred to as: MOCVD) set
Standby reaction chamber, such as Veeco K465i MOCVD or Veeco C4MOCVD.With hydrogen or nitrogen or hydrogen when realization
The mixed gas of gas and nitrogen is as carrier gas, trimethyl gallium or triethyl-gallium as gallium source, and high-purity ammonia is as nitrogen source, trimethyl
Indium is as indium source, and trimethyl aluminium is as silicon source, and silane is as silicon source, and two luxuriant magnesium are as magnesium source.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of growing method of LED epitaxial slice, which is characterized in that the growing method includes:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate；
Wherein, the p type semiconductor layer includes the multiple sublayers stacked gradually, and the sublayer of first stacking uses such as lower section
Formula growth:
Magnesium source and nitrogen source are opened, forms gallium vacancy on the surface of the active layer；
Indium source and gallium source are opened, magnesium is activated；
Indium source is closed, forms the sublayer on the surface of the active layer；
Other sublayers in addition to the sublayer being laminated in the multiple sublayer except first are grown in the following way:
Gallium source is closed, forms gallium vacancy on the surface of the established sublayer；
Gallium source is opened, forms the sublayer on the surface of the established sublayer；
The thickness of the multiple sublayer is gradually increased along the stacking direction of the multiple sublayer, the doping of magnesium in the multiple sublayer
Concentration gradually rises along the stacking direction of the multiple sublayer, the layer of the growth temperature of the multiple sublayer along the multiple sublayer
Folded direction gradually rises.
2. growing method according to claim 1, which is characterized in that the elevation amplitude of the growth temperature of the multiple sublayer
It is directly proportional to the raising multiple of the doping concentration of magnesium in the multiple sublayer.
3. growing method according to claim 2, which is characterized in that in the two neighboring sublayer, what is be laminated afterwards is described
The growth temperature of sublayer is 5 DEG C~30 DEG C higher than the growth temperature for the sublayer being first laminated.
4. growing method according to claim 2, which is characterized in that in the two neighboring sublayer, what is be laminated afterwards is described
The doping concentration of magnesium is 1.5 times~5 times of the doping concentration of magnesium in the sublayer being first laminated in sublayer.
5. growing method according to any one of claims 1 to 4, which is characterized in that the increasing of the thickness of the multiple sublayer
Big multiple is identical as the raising multiple of doping concentration of magnesium in the multiple sublayer.
6. growing method according to claim 5, which is characterized in that in the two neighboring sublayer, what is be laminated afterwards is described
1.5 times of the thickness with a thickness of the sublayer being first laminated of sublayer~4 times.
7. growing method according to any one of claims 1 to 4, which is characterized in that formed gallium vacancy when a length of 5s~
20s。
8. growing method according to any one of claims 1 to 4, which is characterized in that the quantity of the multiple sublayer is 3
~8.
9. growing method according to any one of claims 1 to 4, which is characterized in that the active layer includes stacking gradually
Multiple periodic structures, each periodic structure includes that the Quantum Well stacked gradually and quantum are built, the material of the Quantum Well
Using the gallium nitride of doped indium, the material that the quantum is built uses undoped gallium nitride.
10. growing method according to claim 9, which is characterized in that the gallium indium nitride layer formed when being activated to magnesium
The doping concentration of middle indium is 1/20~1/10 of the doping concentration of indium in the Quantum Well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910069091.7A CN109888064B (en) | 2019-01-24 | 2019-01-24 | Growth method of light emitting diode epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910069091.7A CN109888064B (en) | 2019-01-24 | 2019-01-24 | Growth method of light emitting diode epitaxial wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114883464A (en) * | 2022-04-26 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer capable of improving reliability and preparation method thereof |
| CN119133328A (en) * | 2024-11-07 | 2024-12-13 | 苏州立琻半导体有限公司 | P-type AlGaN material and preparation method thereof, and preparation method of ultraviolet photoelectronic device |
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| CN106848025A (en) * | 2016-12-13 | 2017-06-13 | 华灿光电（浙江）有限公司 | Growth method of light-emitting diode epitaxial wafer |
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| CN114883464A (en) * | 2022-04-26 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer capable of improving reliability and preparation method thereof |
| CN119133328A (en) * | 2024-11-07 | 2024-12-13 | 苏州立琻半导体有限公司 | P-type AlGaN material and preparation method thereof, and preparation method of ultraviolet photoelectronic device |
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