CN109887847A - Semiconductor structure and method of making the same - Google Patents
Semiconductor structure and method of making the same Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 45
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 13
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
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Abstract
本申请提供了一种半导体结构与其制作方法，该制作方法包括：在衬底上依次设置多个应变缓冲层，各应变缓冲层的材料为SiGe，任意相邻的两个应变缓冲层中，与衬底之间距离大的应变缓冲层中Ge的重量含量大于另一个应变缓冲层中Ge的重量含量，与衬底距离最小的应变缓冲层为第一应变缓冲层，第一应变缓冲层的厚度大于第一应变缓冲层中的Ge的重量含量对应的关键厚度，衬底为Si衬底或SOI衬底；在与衬底距离最大的应变缓冲层的裸露表面上设置沟道结构，沟道结构包括导电沟道层，导电沟道层的材料包括Si、Ge和/或SiGe。该方法使得导电沟道层中的缺陷较少，保证了器件具有较好的性能。
The present application provides a semiconductor structure and a method for fabricating the same. The fabrication method includes: sequentially arranging a plurality of strain buffer layers on a substrate, the material of each strain buffer layer is SiGe, and in any two adjacent strain buffer layers, a The weight content of Ge in the strain buffer layer with a large distance between the substrates is greater than that in the other strain buffer layer, and the strain buffer layer with the smallest distance from the substrate is the first strain buffer layer, and the thickness of the first strain buffer layer greater than the critical thickness corresponding to the weight content of Ge in the first strain buffer layer, the substrate is a Si substrate or SOI substrate; a channel structure is set on the exposed surface of the strain buffer layer with the largest distance from the substrate, and the channel structure A conductive channel layer is included, and the material of the conductive channel layer includes Si, Ge and/or SiGe. The method results in fewer defects in the conductive channel layer and ensures better performance of the device.
Description
Technical field
This application involves semiconductor fields, in particular to a kind of semiconductor structure and its production method.
Background technique
Miniature with device feature size, the three-dimensional FinFET and nano-wire devices of mobility channel become research
Hot spot.Wherein, control becomes integrated Major Difficulties the defects of the line dislocation of the importing of high mobility material.This is because
There is 4.2% lattice mismatch in Ge and Si material, after crucial thickness of the epitaxial thickness more than the material, just will form such as Fig. 1
Shown in line dislocation the defects of.The performance that dislocation defects will lead to device is poor.
In addition, due to the introducing of the new materials such as SiGe or Ge, and the technique of traditional STI liner (general 1050 degree, O2Environment
Middle oxidation) and STI deposit after annealing process and they there is a problem of compatible, for example oxidizing temperature is excessively high leads to SiGe,
The problem of Ge is unstable and aoxidizes, the final pattern for influencing Fin, as shown in Figure 2.
Disclosed information above is used only to reinforce the background technique to technology described herein in the background section
Understanding may include therefore certain information in background technique, these information are to those skilled in the art and not formed
The home known prior art.
Summary of the invention
The main purpose of the application is to provide a kind of semiconductor structure and its production method, high in the prior art to solve
The problem of device of mobility material is caused due to threading dislocation defects.
To achieve the goals above, according to the one aspect of the application, a kind of production method of semiconductor structure is provided,
The production method includes: to set gradually multiple strained buffer layers on substrate, and the material of each strained buffer layer is SiGe, is appointed
In two strained buffer layers for anticipating adjacent, the weight of Ge contains in the big strained buffer layer of distance between the substrate
Amount is greater than the weight content of Ge in another described strained buffer layer, is with the smallest strained buffer layer of the substrate distance
First strained buffer layer, the thickness of first strained buffer layer are greater than the weight content of the Ge in first strained buffer layer
Corresponding key thickness, the substrate are Si substrate or SOI substrate；With the maximum strained buffer layer of the substrate distance
Exposed surface on channel structure is set, the channel structure includes conductivity channel layer, and the material of the conductivity channel layer includes
Si, Ge and/or SiGe.
Further, the process for each strained buffer layer being arranged includes: that prestrain is arranged on the surface of the substrate
Buffer layer；It anneals to the prestrain buffer layer, forms the strained buffer layer.
It further, is top with the maximum strained buffer layer of the substrate distance in multiple strained buffer layers
The process of the top layer strained buffer layer is arranged in ply strain buffer layer further include: to the strained buffer layer formed after annealing
Carry out planarization process.
Further, the temperature of the annealing is between 750~950 DEG C, the time of the annealing between 5~30min,
The atmosphere of the annealing includes nitrogen and hydrogen.
Further, there are three the strained buffer layers, respectively the first strained buffer layer, the second strained buffer layer and
Three strained buffer layers, the material of preferably described first strained buffer layer are Si1-xGex, 5%≤x≤30%, second strain
The material of buffer layer is Si1-yGey, 15%≤y≤45%, the material of the third strained buffer layer is Si1-zGez, 25%≤z
≤ 60%；The thickness of further preferred first strained buffer layer is between 100~1000nm, second strained buffer layer
Thickness between 200~1000nm, the thickness of second strained buffer layer is between 500~1500nm.
Further, the production method further include: pre- cap, institute are set on the exposed surface of the channel structure
The material for stating pre- cap is Si.
Further, the production method further include: the channel structure and the part strained buffer layer are carved
Erosion forms fin；Exposed table on the exposed surface of the fin and with the maximum strained buffer layer of the substrate distance
Gasket material is set on face；Shallow-trench isolation material is set on the exposed surface of the gasket material；Described in etching removal part
Shallow-trench isolation material and the part gasket material retain the lining of the two sides of the strained buffer layer after being located at etching
Cushion material and the shallow-trench isolation material.
Further, the material of the liner includes Si3N4。
Further, the production method includes: that false grid are arranged on the partial denudation surface of the fin；In the fin
Side wall is arranged on the partial denudation surface and two sides of the false grid；It is arranged on the exposed surface of the fin of the side wall two sides
Source/drain region；Remove the false grid；It is sequentially filled high K dielectric and grid material in the groove formed after removing the false grid,
In the case that the channel structure includes sacrificial layer, before filling the high K dielectric, the production method further includes that release is received
The process of rice noodles, after discharging the nano wire, the production method further includes the sky formed after discharging the nano wire
The successively high K dielectric and the grid material are filled in gap.
According to the another aspect of the application, a kind of semiconductor structure is provided, the semiconductor structure is by any described
Production method be made.
According to the another aspect of the application, a kind of semiconductor structure is provided, the semiconductor structure includes: substrate, institute
Stating substrate is Si substrate or SOI substrate；Multiple strained buffer layers are sequentially stacked along far from the direction of the substrate, each described to answer
Become the material of buffer layer as Si1-xGex, in two strained buffer layers of arbitrary neighborhood, distance is big between the substrate
The weight content of Ge is greater than the weight content of Ge in another described strained buffer layer, each strain in the strained buffer layer
The thickness of buffer layer is greater than the corresponding crucial thickness of weight content of the Ge in the corresponding strained buffer layer；At least one is led
Electric channel, on the surface far from the substrate of the strained buffer layer, the material of the conducting channel includes Si, Ge
And/or SiGe.
Further, there are three the strained buffer layers, respectively the first strained buffer layer, the second strained buffer layer and
Three strained buffer layers, the weight content of the Ge in preferably described first strained buffer layer is between 5~30%, second strain
The weight content of Ge in buffer layer between 15~45%, the weight content of the Ge in the third strained buffer layer 25~
Between 60%；The thickness of further preferred first strained buffer layer is between 100~1000nm, second strain relief
The thickness of layer is between 200~1000nm, and the thickness of second strained buffer layer is between 500~1500nm.
It further, include flat part and protruding portion with the maximum strained buffer layer of the substrate distance, it is described prominent
Portion is located on the surface far from the substrate of the flat part out, and the conducting channel is located at the separate described of the protruding portion
On the surface of flat part, the semiconductor structure further include: laying, it is on the two sides side wall of the protruding portion and described
On the partial denudation surface of flat part；Shallow trench isolation region, on the exposed surface of the flat part of the laying two sides；
Source/drain region positioned at the conducting channel two sides and is located on the surface far from the substrate of the flat part；Grid is located at
It include the feelings of multiple conducting channels in the semiconductor structure on the surface far from the strained buffer layer of the conducting channel
Under condition, there is gap between conducting channel described in any two, the grid is also located in the gap；High K dielectric is located at institute
It states between the two sides and the grid and the strained buffer layer of grid, includes multiple conducting channels in the semiconductor structure
In the case where, the high K dielectric is also located at the periphery in the gap and being located at the grid；Side wall is located at the conductive ditch
On the surface far from the strained buffer layer in road and positioned at the two sides of the high K dielectric.
Using the technical solution of the application, in above-mentioned production method, it is provided between substrate and conductivity channel layer more
A strained buffer layer, also, the thickness of the first strained buffer layer is greater than its corresponding crucial thickness, in this way in the strained buffer layer
Defect it is more, due to the first strain relief of weight content ratio of the Ge in the strained buffer layer that is arranged on the first strained buffer layer
The weight content of Ge in layer is high, can make in this way the defects of the strained buffer layer of defect on the first strained buffer layer compared with
It is few, keep the influence to the conductivity channel layer to subsequent setting smaller, so that the defects of conductivity channel layer is less, ensure that device
Part has preferable performance.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows a kind of TEM figure of threading dislocation defects in the prior art；
Fig. 2 is to show the TEM figure for the fin that a kind of production method in the prior art obtains；
Fig. 3 to Figure 13 shows the structural schematic diagram of the semiconductor structure of the application in the production process.
Wherein, the above drawings include the following reference numerals:
10, substrate；20, the first strained buffer layer；30, the second strained buffer layer；40, third strained buffer layer；41, flat
Portion；42, protruding portion；50, channel structure；51, sacrificial layer；52, conductivity channel layer；500, fin；60, gasket material；61, it pads
Layer；70, shallow-trench isolation material；71, shallow trench isolation region.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
It should be understood that when element (such as layer, film, region or substrate) is described as at another element "upper", this yuan
Part can be directly on another element, or intermediary element also may be present.Moreover, in specification and claims, when
When description has element " connected " to another element, which " can be directly connected to " to another element, or pass through third element
" connected " to another element.
As background technique is introduced, due to introducing in nano-wire devices in the prior art or three-dimensional FinFET
High mobility material causes the performance of device to be affected so that being easy to produce threading dislocation defects in conducting channel, in order to solve
Technical problem as above, present applicant proposes a kind of semiconductor structures and its production method.
In a kind of typical embodiment of the application, a kind of production method of semiconductor structure, the production side are provided
Method includes:
Multiple strained buffer layers are set gradually on substrate 10, as shown in figure 3, the material of each above-mentioned strained buffer layer is
SiGe, in two above-mentioned strained buffer layers of arbitrary neighborhood, between above-mentioned substrate 10 in the big above-mentioned strained buffer layer of distance
The weight content of Ge is greater than the weight content of Ge in another above-mentioned strained buffer layer, i.e., along the direction far from above-mentioned substrate 10
On, the weight content of the Ge in strained buffer layer gradually increases, and is apart from the smallest above-mentioned strained buffer layer with above-mentioned substrate 10
First strained buffer layer 20, the thickness of above-mentioned first strained buffer layer 20 are greater than the weight of the Ge in above-mentioned first strained buffer layer 20
Measure the corresponding crucial thickness of content, i.e. weight content corresponding pass of the thickness of the first strained buffer layer 20 greater than the Ge in this layer
Key thickness, above-mentioned substrate 10 are Si substrate or SOI substrate；
With channel structure 50 is set on exposed surface of the above-mentioned substrate 10 apart from maximum above-mentioned strained buffer layer, formed
Such as Fig. 4 or structure shown in fig. 5, as shown in figure 4, above-mentioned channel structure 50 only includes conductivity channel layer 52, above-mentioned conducting channel
The material of layer 52 includes Si, Ge and/or SiGe, as shown in figure 5, above-mentioned channel structure 50 only includes the sacrificial layer 51 being arranged alternately
With conductivity channel layer 52.
In above-mentioned production method, multiple strained buffer layers, also, first are provided between substrate and conductivity channel layer
The thickness of strained buffer layer is greater than its corresponding crucial thickness, and the defects of strained buffer layer in this way is more, answers due to first
The weight content for becoming the Ge in the first strained buffer layer of weight content ratio of the Ge in the strained buffer layer being arranged on buffer layer is high,
It can make the defects of the strained buffer layer of defect on the first strained buffer layer less in this way, make to subsequent setting
The influence of conductivity channel layer is smaller, so that the defects of conductivity channel layer is less, ensure that device has preferable performance.
It should be noted that the concrete mode of each structure sheaf of setting in the application can be come according to the actual situation really
It is fixed, such as can choose the modes such as MOCVD, MBE or LPCVD and come extension strained buffer layer and channel structure.
In order to be further reduced the defects of each strained buffer layer, so that fewer defects extend to conductivity channel layer
In, the defect for further ensuring conductivity channel layer is less, and quality is preferable, in a kind of embodiment of the application, is arranged each above-mentioned
The process of strained buffer layer includes: the setting prestrain buffer layer on the surface of above-mentioned substrate；To above-mentioned prestrain buffer layer into
Row annealing, forms above-mentioned strained buffer layer.
In a kind of embodiment of the application, the temperature of above-mentioned annealing is between 750~950 DEG C, and the time of above-mentioned annealing is 5
Between~30min, the atmosphere of above-mentioned annealing includes nitrogen and hydrogen.The annealing process can be further reduced in strained buffer layer
Defect.
It should be noted that the specific process parameter of the application annealing is not limited to above-mentioned process parameters range, it can be with
It is arranged according to the actual situation.
The number of the above-mentioned strained buffer layer of the application can be arranged according to the actual situation, can for more than or equal to
2 any number, in a kind of specific embodiment of the application, as shown in figure 3, there are three above-mentioned strained buffer layers, respectively
First strained buffer layer 20, the second strained buffer layer 30 and third strained buffer layer 40.Gradually increased by three Ge weight contents
The strained buffer layer added reduces defect, so that the defects of conductivity channel layer 52 is less even without defect.
When in semiconductor structure including three strained buffer layers, the weight content of the Ge in corresponding each layer can basis
Actual conditions are arranged, as long as ensuring along the direction far from substrate, the weight content of the Ge in each strained buffer layer gradually increases
Add, specifically, the material of above-mentioned first strained buffer layer is Si1-xGex, 5%≤x≤30%, above-mentioned second strain relief
The material of layer is Si1-yGey, 15%≤y≤45%, the material of above-mentioned third strained buffer layer is Si1-zGez, 25%≤z≤
60%.The content range of Ge in material in three strained buffer layers is arranged in above-mentioned range, can be further ensured that
Along the direction far from substrate, the quantity of the defects of strained buffer layer is gradually decreased, to be further ensured that subsequent production
The defects of conductivity channel layer is less, and it is with good performance to further ensure semiconductor structure.
By above-mentioned content range it is found that the weight content range of the Ge in three strained buffer layers can have overlapping portion
Point, for example, the material of above-mentioned first strained buffer layer is Si1-xGex, 5%≤x≤20%, the material of above-mentioned second strained buffer layer
Material is Si1-yGey, 15%≤y≤25%, the material of above-mentioned third strained buffer layer is Si1-zGez, 20%≤z≤35%, still
As x=15%, y > 15% is also to ensure that the weight of the Ge of three strained buffer layers contains along on the direction far from substrate
Amount is gradually incremented by.
The weight content range of Ge may be nonoverlapping part in three strained buffer layers, such as should slow down second
It rushing in layer and the first strained buffer layer juncture area, the weight content of Ge can be identical, it is gradually distance from the first strained buffer layer, the
The weight content of Ge in two strained buffer layers is gradually increased, than big in the first strained buffer layer.Those skilled in the art can
The strained buffer layer of corresponding Ge content to be arranged according to the actual situation.For example, the material of above-mentioned first strained buffer layer is Si1- xGex, 5%≤x≤15%, the material of above-mentioned second strained buffer layer is Si1-yGey, 15%≤y≤25%, above-mentioned third strain
The material of buffer layer is Si1-zGez, 25%≤z≤35%.
In the above embodiments, the thickness of each strained buffer layer can be arranged according to the actual situation, in principle,
The thickness of three can be the same or different, and three of suitable thickness can be arranged in those skilled in the art according to the actual situation
Strained buffer layer.
In order to reduce the difficulty of technique and reduce the time of preparation, in a kind of embodiment of the application, above-mentioned first is answered
Become buffer layer thickness between 100~1000nm, the thickness of above-mentioned second strained buffer layer between 200~1000nm, on
The thickness of the second strained buffer layer is stated between 500~1500nm.
In order to be further reduced the defects of subsequent conductivity channel layer, in a kind of embodiment of the application, multiple strains
In buffer layer, it is top layer strained buffer layer with the maximum strained buffer layer of substrate distance, above-mentioned top layer strained buffer layer is set
Process further include: planarization process is carried out to the above-mentioned strained buffer layer formed after annealing, i.e. this layer of manufacturing process includes: upper
State setting prestrain buffer layer on the surface of substrate；It anneals to above-mentioned prestrain buffer layer, forms strained buffer layer；To moving back
Above-mentioned strained buffer layer after fire carries out planarization process, removes the strained buffer layer of part, and it is lesser to form surface roughness
Above-mentioned strained buffer layer.
In order to be protected to conducting channel, prevent the techniques such as subsequent cleaning, injection and etching to conducting channel not
Good influence, in a kind of embodiment not shown in the figure of the application, above-mentioned production method further include: in the naked of above-mentioned channel structure
Pre- cap is set on dew surface, and the material of above-mentioned pre- cap is Si.
Above-mentioned pre- cap can extension synchronous with channel structure, can also be with asynchronous extension, synchronous extension just refers to outer
Prolong the pre- cap of the direct extension of channel structure, after asynchronous extension just refers to the complete channel of extension, first carries out other techniques, then
The pre- cap of extension again.
The semiconductor structure of the application can be any structure for including substrate and conducting channel, corresponding production method
It can be the production method of any semiconductor structure including substrate and conducting channel, those skilled in the art can be by the system
It is applied in the manufacturing process of suitable semiconductor structure as method.
In a kind of specific embodiment, the above-mentioned semiconductor structure of the application is nano-wire devices or three-dimensional FinFET,
Therefore, after channel structure 50 is set, above-mentioned production method further include: above-mentioned to above-mentioned channel structure 50 and part to slow down
It rushes layer to perform etching, remainder channel structure 50 and part strained buffer layer, wherein wrap in remaining part channel structure 50
Fin 500 is included, includes that conducting channel can specifically pass through side wall transfer techniques (Sidewall as is seen in fig. 6 or fig. 7 in fin 500
Transfer lithography, abbreviation STL)) or other photoetching techniques form the figure of hard exposure mask, which can be
SiN, SiO2Or SiN/SiO2Lamination；On the exposed surface of above-mentioned fin 500 and with above-mentioned substrate 10 on maximum
Setting gasket material 60 on the exposed surface of strained buffer layer is stated, as shown in Fig. 8 or Fig. 9, specific set-up mode can basis
Actual conditions are set, for example can be arranged gasket material 60 using PECVD or ALD；In the naked of above-mentioned gasket material 60
Reveal and shallow-trench isolation material 70 is set on surface, after the above-mentioned shallow-trench isolation material of CMP to conducting channel exposes, forms such as Figure 10 or figure
Structure shown in 11；The above-mentioned shallow-trench isolation material 70 in etching removal part and the above-mentioned gasket material 60 in part retain to be located at and carve
The above-mentioned gasket material 60 of the two sides of above-mentioned strained buffer layer after erosion and above-mentioned shallow-trench isolation material 70 form Figure 12 or figure
Structure shown in 13.In addition, the gasket material and shallow-trench isolation material of strained buffer layer two sides can be prominent with strained buffer layer
The flush of the separate substrate in portion out specifically can also may be used lower than the surface of the separate substrate of the protruding portion of strained buffer layer
To obtain suitable structure according to the actual situation.
Specifically, the process of the etching above-mentioned shallow-trench isolation material 70 in removal part and the above-mentioned gasket material 60 in part can be with
Include: using HF wet etching+dry etch process (such as F base gas dry method high selectivity ratio removal gasket material 60 or
SiCONI method) or time quarter that the technique that SiCoNi is cleaned carries out shallow-trench isolation material 70 is directlyed adopt, remove shallow-trench isolation material
70 and gasket material 60.The liner material of reservation forms laying 61, and the shallow-trench isolation material 70 of reservation forms shallow trench isolation region 71.
The thickness of the laying of the application can be set according to the actual situation, in a kind of specific embodiment, above-mentioned lining
The thickness of bed course not only can play the high-temperature technology opposite of isolation subsequent oxidation or annealing between 1~10nm
Channel structure is not oxidized, can also increase the process window of subsequent shallow-trench isolation material deposit.
Shallow-trench isolation material and gasket material all can be any feasible material in the prior art, such as shallow-trench isolation
Material is silica, gasket material Si3N4。Si3N4In the event of high temperatures, it can be avoided the material of conducting channel by oxygen
Change, and then guarantees to be formed the fin of predetermined pattern.
In order to further ensure the isolated insulation better performances of the shallow trench isolation region of formation, a kind of embodiment of the application
In, after shallow-trench isolation material is arranged, before etching, also need to move back shallow-trench isolation material in the production method
Fire, the process annealed in order to prevent generate biggish adverse effect to other structures, in a kind of embodiment of the application, control
Annealing temperature at 850 DEG C hereinafter, while in order to further ensure annealing effect guarantee it is smaller to the adverse effect of device, should
Annealing temperature in the process is 750 DEG C.
For nano-wire devices or three-dimensional FinFET, the production method of semiconductor structure further include: in above-mentioned fin
Partial denudation surface on false grid are set, the production method of false grid may refer to feasible mode in the prior art；Above-mentioned
Side wall is arranged on the partial denudation surface of the fin and two sides of above-mentioned false grid；On the exposed surface of the above-mentioned fin of above-mentioned side wall two sides
Source/drain region is set；Remove above-mentioned false grid；High K dielectric and grid material are sequentially filled in the groove formed after removing above-mentioned false grid
Material includes the conductivity channel layer being arranged alternately in above-mentioned channel structure in the case that the semiconductor structure is nano-wire devices
And sacrificial layer, for this structure, before filling above-mentioned high K dielectric, above-mentioned production method further includes discharging the mistake of nano wire
Journey removes the process of sacrificial layer, after discharging above-mentioned nano wire, above-mentioned production method further includes discharging above-mentioned nano wire
Successively above-mentioned high K dielectric and above-mentioned grid material are filled in the gap formed afterwards.Due to these structures setting position with it is existing
It is essentially identical in technology, therefore, in the application it is not drawn into specific structure chart.
Certainly, the production method of nano-wire devices or three-dimensional FinFET are not limited to above-mentioned method, can also use
Other methods make, and those skilled in the art can select suitable manufacture craft that false grid, side are arranged according to the actual situation
Wall, source/drain region, high K dielectric and grid material etc..Also, each making step in specific above-mentioned manufacturing process can root
It is determined according to actual conditions, as long as can be realized the production of counter structure.
In the typical embodiment of the another kind of the application, a kind of semiconductor structure is provided, which is to adopt
It is prepared with above-mentioned production method.
The semiconductor structure is due to making to obtain using above-mentioned production method, the defects of line dislocation in conducting channel
It is less, the better performances of device.
In the typical embodiment of another of the application, a kind of semiconductor structure is provided, as shown in Fig. 7 to Figure 13,
The semiconductor structure includes:
Substrate 10, above-mentioned substrate 10 are Si substrate or SOI substrate；
Multiple strained buffer layers are sequentially stacked, the material of each above-mentioned strained buffer layer along the direction far from above-mentioned substrate 10
For Si1-xGex, in two above-mentioned strained buffer layers of arbitrary neighborhood, the big above-mentioned strain relief of distance between above-mentioned substrate 10
The weight content of Ge is greater than the weight content of Ge in another above-mentioned strained buffer layer, the thickness of each above-mentioned strained buffer layer in layer
Key thickness corresponding greater than the weight content of the Ge in corresponding above-mentioned strained buffer layer；
At least one conducting channel, on the surface far from above-mentioned substrate 10 of above-mentioned strained buffer layer, above-mentioned conduction
The material of channel includes Si, Ge and/or SiGe.
In above-mentioned semiconductor structure, multiple strained buffer layers are provided between substrate 10 and conductivity channel layer 52, and
And first the thickness of strained buffer layer 20 be greater than its corresponding crucial thickness, the defects of strained buffer layer in this way is more, by
Ge in the first strained buffer layer of weight content ratio 20 of Ge in the strained buffer layer being arranged on the first strained buffer layer 20
Weight content it is high, can make the defects of the strained buffer layer of defect on the first strained buffer layer 20 less in this way, make
To which the influence of the conductivity channel layer 52 to subsequent setting is smaller, so that the defects of conductivity channel layer 52 is less, device ensure that
Part has preferable performance.
The number of the above-mentioned strained buffer layer of the application can be arranged according to the actual situation, can for more than or equal to
2 any number, in a kind of specific embodiment of the application, as shown in Fig. 7 to Figure 13, there are three above-mentioned strained buffer layers,
Respectively the first strained buffer layer, the second strained buffer layer and third strained buffer layer.Gradually increased by three Ge weight contents
The strained buffer layer added reduces defect, so that the defects of conductivity channel layer is less.
When that should go back buffer layer including three in semiconductor structure, the weight content of the Ge in corresponding each layer can basis
Actual conditions are arranged, as long as ensuring along the direction far from substrate, the weight content of the Ge in each strained buffer layer gradually increases
Add, specifically, the material of above-mentioned first strained buffer layer is Si1-xGex, 5%≤x≤30%, above-mentioned second strain relief
The material of layer is Si1-yGey, 15%≤y≤45%, the material of above-mentioned third strained buffer layer is Si1-zGez, 25%≤z≤
60%.The content range of Ge in material in three strained buffer layers is arranged in above-mentioned range, can be further ensured that
Along the direction far from substrate, the quantity of the defects of strained buffer layer is gradually decreased, to be further ensured that subsequent production
The defects of conductivity channel layer is less, and it is with good performance to further ensure semiconductor structure.
By above-mentioned content range it is found that the weight content of the Ge in three strained buffer layers can not be overlapped for range and
The range gradually increased, or range that is having overlapping and gradually increasing, such as answered in the second strained buffer layer with first
Become in buffer layer juncture area, the weight content of Ge can be identical, is gradually distance from the first strained buffer layer, the second strained buffer layer
In the weight content of Ge be gradually increased, than big in the first strained buffer layer.Those skilled in the art can be according to practical feelings
The strained buffer layer of corresponding Ge content is arranged in condition.
The weight content range of Ge in three strained buffer layers can have lap, for example, above-mentioned first strain
The material of buffer layer is Si1-xGex, 5%≤x≤20%, the material of above-mentioned second strained buffer layer is Si1-yGey, 15%≤y≤
25%, the material of above-mentioned third strained buffer layer is Si1-zGez, 20%≤z≤35%, but as x=15%, y > 15%,
Also it is to ensure that the weight content of the Ge of three strained buffer layers is gradually incremented by along on the direction far from substrate.
The weight content range of Ge may be nonoverlapping part in three strained buffer layers, such as should slow down second
It rushing in layer and the first strained buffer layer juncture area, the weight content of Ge can be identical, it is gradually distance from the first strained buffer layer, the
The weight content of Ge in two strained buffer layers is gradually increased, than big in the first strained buffer layer.Those skilled in the art can
The strained buffer layer of corresponding Ge content to be arranged according to the actual situation.For example, the material of above-mentioned first strained buffer layer is Si1- xGex, 5%≤x≤15%, the material of above-mentioned second strained buffer layer is Si1-yGey, 15%≤y≤25%, above-mentioned third strain
The material of buffer layer is Si1-zGez, 25%≤z≤35%.
In the above embodiments, the thickness of each strained buffer layer can be arranged according to the actual situation, in principle,
The thickness of three can be the same or different, and three of suitable thickness can be arranged in those skilled in the art according to the actual situation
Strained buffer layer.
In order to reduce the difficulty of technique and reduce the time of preparation, in a kind of embodiment of the application, above-mentioned first is answered
Become buffer layer thickness between 100~1000nm, the thickness of above-mentioned second strained buffer layer between 200~1000nm, on
The thickness of the second strained buffer layer is stated between 500~1500nm.
In actual semiconductor structure, with above-mentioned substrate 10 apart from maximum above-mentioned strained buffer layer include flat part 41 and
Protruding portion 42, as shown in Figure 6 and Figure 7, above-mentioned protruding portion 42 are located on the surface far from above-mentioned substrate 10 of above-mentioned flat part 41,
Above-mentioned conducting channel is located on the surface far from above-mentioned flat part 41 of above-mentioned protruding portion 42, and one kind of the application is specific to be implemented
In example, above-mentioned semiconductor structure further includes laying 61, shallow trench isolation region 71, source/drain region, grid, high K dielectric and side wall,
Laying 61 and shallow trench isolation region 71 are merely illustrated in Figure 12 or Figure 13.Wherein, laying 61 is located at above-mentioned protruding portion 42
On the side wall of two sides and on the partial denudation surface of above-mentioned flat part 41；Shallow trench isolation region 71 is located at above-mentioned 61 two sides of laying
Above-mentioned flat part 41 exposed surface on；Source/drain region is located at above-mentioned conducting channel two sides and is located at the remote of above-mentioned flat part 41
On surface from above-mentioned substrate 10, at least the part of the source/drain region of conducting channel and its two sides forms fin；Grid is located at above-mentioned
On the surface far from above-mentioned strained buffer layer of conducting channel, include the case where multiple conducting channels in above-mentioned semiconductor structure
Under, there is gap, above-mentioned grid is also located in above-mentioned gap between the above-mentioned conducting channel of any two；High K dielectric is located at above-mentioned
It include multiple conducting channels in above-mentioned semiconductor structure between the two sides of grid and above-mentioned grid and above-mentioned strained buffer layer
In the case of, above-mentioned high K dielectric is also located at the periphery in above-mentioned gap and being located at above-mentioned grid；Side wall is located at above-mentioned conducting channel
Two sides on surface far from above-mentioned strained buffer layer and positioned at above-mentioned high K dielectric.
In order to be protected to conducting channel, prevent in the production process, the techniques such as subsequent cleaning, injection and etching
Adverse effect is generated to conducting channel, in a kind of embodiment not shown in the figure of the application, above-mentioned semiconductor structure further includes
Cap, this layer are located on the surface of the separate strained buffer layer of conducting channel, and the material of above-mentioned cap is Si.
The semiconductor structure of application is not limited to above-mentioned nano-wire devices or three-dimensional FinFET, and can also be includes lining
Any structure of bottom and conducting channel.
It can be seen from the above description that the application the above embodiments realize following technical effect:
1), in the production method of the application, multiple strained buffer layers are provided between substrate and conductivity channel layer, and
And first the thickness of strained buffer layer be greater than its corresponding crucial thickness, the defects of strained buffer layer in this way is more, due to
The weight of Ge in the first strained buffer layer of weight content ratio for the Ge in strained buffer layer being arranged on first strained buffer layer
Content is high, can make the defects of the strained buffer layer of defect on the first strained buffer layer less in this way, makes to rear
The influence of the conductivity channel layer of continuous setting is smaller, so that the defects of conductivity channel layer is less, it is preferable to ensure that device has
Performance.
2), in the semiconductor structure of the application, multiple strained buffer layers are provided between substrate and conductivity channel layer, and
And first the thickness of strained buffer layer be greater than its corresponding crucial thickness, the defects of strained buffer layer in this way is more, due to
The weight of Ge in the first strained buffer layer of weight content ratio for the Ge in strained buffer layer being arranged on first strained buffer layer
Content is high, can make the defects of the strained buffer layer of defect on the first strained buffer layer less in this way, makes to rear
The influence of the conductivity channel layer of continuous setting is smaller, so that the defects of conductivity channel layer is less, it is preferable to ensure that device has
Performance.
It above are only preferred embodiment of the present application above, be not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (13)
1. a kind of production method of semiconductor structure characterized by comprising
Setting gradually multiple strained buffer layers on substrate, the material of each strained buffer layer is SiGe, the two of arbitrary neighborhood
In a strained buffer layer, between the substrate in the big strained buffer layer of distance the weight content of Ge be greater than it is another
The weight content of Ge in a strained buffer layer should slow down with the smallest strained buffer layer of the substrate distance for first
Layer is rushed, the thickness of first strained buffer layer is greater than the corresponding key of weight content of the Ge in first strained buffer layer
Thickness, the substrate are Si substrate or SOI substrate；
With channel structure, the channel structure are set on the exposed surface of the maximum strained buffer layer of the substrate distance
Including conductivity channel layer, the material of the conductivity channel layer includes Si, Ge and/or SiGe.
2. manufacturing method according to claim 1, which is characterized in that the process of each strained buffer layer of setting includes:
Prestrain buffer layer is set on the surface of the substrate；
It anneals to the prestrain buffer layer, forms the strained buffer layer.
3. production method according to claim 1 or 2, which is characterized in that in multiple strained buffer layers, with the lining
Bottom is top layer strained buffer layer apart from the maximum strained buffer layer, and the process that the top layer strained buffer layer is arranged also is wrapped
It includes:
Planarization process is carried out to the strained buffer layer formed after annealing.
4. production method according to claim 2, which is characterized in that the temperature of the annealing between 750~950 DEG C,
The time of the annealing, the atmosphere of the annealing included nitrogen and hydrogen between 5~30min.
5. manufacturing method according to claim 1, which is characterized in that there are three the strained buffer layers, and respectively first
Strained buffer layer, the second strained buffer layer and third strained buffer layer, the material of preferably described first strained buffer layer are Si1- xGex, 5%≤x≤30%, the material of second strained buffer layer is Si1-yGey, 15%≤y≤45%, the third strain
The material of buffer layer is Si1-zGez, 25%≤z≤60%；The thickness of further preferred first strained buffer layer 100~
Between 1000nm, the thickness of second strained buffer layer is between 200~1000nm, the thickness of second strained buffer layer
Between 500~1500nm.
6. manufacturing method according to claim 1, which is characterized in that the production method further include:
Pre- cap is set on the exposed surface of the channel structure, and the material of the pre- cap is Si.
7. manufacturing method according to claim 1, which is characterized in that the production method further include:
The channel structure and the part strained buffer layer are performed etching, fin is formed；
On the exposed surface of the fin and with set on the exposed surface of the maximum strained buffer layer of the substrate distance
Set gasket material；
Shallow-trench isolation material is set on the exposed surface of the gasket material；
The etching removal part shallow-trench isolation material and the part gasket material, retain the strain after being located at etching
The gasket material of the two sides of buffer layer and the shallow-trench isolation material.
8. production method according to claim 7, which is characterized in that the material of the liner includes Si3N4。
9. production method according to claim 7, which is characterized in that the production method includes:
False grid are set on the partial denudation surface of the fin；
On the partial denudation surface of the fin and side wall is arranged in the two sides of the false grid；
Source/drain region is set on the exposed surface of the fin of the side wall two sides；
Remove the false grid；
It is sequentially filled high K dielectric and grid material in the groove formed after removing the false grid, includes in the channel structure
In the case where sacrificial layer, before filling the high K dielectric, the production method further includes discharging the process of nano wire, is being released
After putting the nano wire, the production method further include filled in the gap formed after discharging the nano wire it is successively described
High K dielectric and the grid material.
10. a kind of semiconductor structure, which is characterized in that semiconductor structure system as described in any one of claims 1 to 9
It is made as method.
11. a kind of semiconductor structure, which is characterized in that the semiconductor structure includes:
Substrate, the substrate are Si substrate or SOI substrate；
Multiple strained buffer layers are sequentially stacked along the direction far from the substrate, and the material of each strained buffer layer is Si1- xGex, in two strained buffer layers of arbitrary neighborhood, the Ge in the big strained buffer layer of distance between the substrate
Weight content is greater than the weight content of Ge in another described strained buffer layer, and the thickness of each strained buffer layer, which is greater than, to be corresponded to
The strained buffer layer in Ge the corresponding crucial thickness of weight content；
At least one conducting channel, on the surface far from the substrate of the strained buffer layer, the conducting channel
Material includes Si, Ge and/or SiGe.
12. semiconductor structure according to claim 11, which is characterized in that there are three the strained buffer layers, respectively
First strained buffer layer, the second strained buffer layer and third strained buffer layer, Ge's in preferably described first strained buffer layer
Weight content is between 5~30%, and the weight content of the Ge in second strained buffer layer is between 15~45%, and described
The weight content of Ge in three strained buffer layers is between 25~60%；The thickness of further preferred first strained buffer layer
Between 100~1000nm, the thickness of second strained buffer layer is between 200~1000nm, second strain relief
The thickness of layer is between 500~1500nm.
13. semiconductor structure according to claim 11, which is characterized in that with the maximum strain of the substrate distance
Buffer layer includes flat part and protruding portion, and the protruding parts are described on the surface far from the substrate of the flat part
Conducting channel is located on the surface far from the flat part of the protruding portion, the semiconductor structure further include:
Laying, on the two sides side wall of the protruding portion and on the partial denudation surface of the flat part；
Shallow trench isolation region, on the exposed surface of the flat part of the laying two sides；
Source/drain region positioned at the conducting channel two sides and is located on the surface far from the substrate of the flat part；
Grid includes more in the semiconductor structure on the surface far from the strained buffer layer of the conducting channel
In the case where a conducting channel, there is gap between conducting channel described in any two, the grid is also located in the gap；
High K dielectric, between the two sides and the grid and the strained buffer layer of the grid, in the semiconductor junction
In the case that structure includes multiple conducting channels, the high K dielectric is also located at the periphery in the gap and being located at the grid；
Side wall, on the surface far from the strained buffer layer of the conducting channel and positioned at the two sides of the high K dielectric.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1656603A (en) * | 2002-05-31 | 2005-08-17 | 华威大学 | Forming lattice-tuned semiconductor substrates |
| CN101207093A (en) * | 2006-12-21 | 2008-06-25 | 中国科学院半导体研究所 | A kind of SiGe relaxation substrate material and preparation method thereof |
| CN102315246A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院上海硅酸盐研究所 | Relaxation SiGe virtual substrate and preparation method thereof |
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2019
- 2019-03-08 CN CN201910176511.1A patent/CN109887847A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1656603A (en) * | 2002-05-31 | 2005-08-17 | 华威大学 | Forming lattice-tuned semiconductor substrates |
| CN101207093A (en) * | 2006-12-21 | 2008-06-25 | 中国科学院半导体研究所 | A kind of SiGe relaxation substrate material and preparation method thereof |
| CN102315246A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院上海硅酸盐研究所 | Relaxation SiGe virtual substrate and preparation method thereof |
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Application publication date: 20190614 |