CN109874008B - Method for distinguishing crash problem through fault test - Google Patents
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Abstract
The invention relates to the technical field of intelligent televisions, in particular to a method for distinguishing a crash problem through fault testing, which comprises the following steps: step S1, performing a plurality of different types of fault tests on the SOC to obtain a plurality of reaction conditions corresponding to different types of fault types, summarizing the reaction conditions, and storing the reaction conditions and the corresponding fault types in a storage unit; and step S2, matching the corresponding reaction information of the system on chip to be tested with the reaction condition stored in the storage unit to obtain the current fault type of the system on chip to be tested. Has the advantages that: according to the corresponding reaction information of the system on chip to be detected, the current fault type of the system on chip to be detected is obtained by matching the corresponding reaction information with the reaction condition stored in the storage unit, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
Description
Technical Field
The invention relates to the technical field of intelligent televisions, in particular to a method for distinguishing a crash problem through fault testing.
Background
At present, the system functions of the smart television are increasing, the dominant frequency of a Central Processing Unit (CPU) is also increasing, and the requirement for the stability of a peripheral power supply is also increasing. In order to ensure the stability of the product and to take the life of the product into consideration, a large number of pressure tests are required in the development stage, including high and low temperature tests (45-15 degrees), or alternating current on-off tests, or remote control on-off tests. The tests are characterized by a large number of samples and a long test period, and when random leaks occur in the test process, the problem troubleshooting and verification take a long time, so that the whole test progress is greatly influenced, and even the development progress of the whole product is influenced.
The solution in the prior art is that, in the development process of a software architecture, as many debugging nodes as possible are added, the running state of the whole system is expected to be recorded, if an abnormal condition occurs during the aging process, the printed error log will become the most valuable analysis data, but because the system-on-chip driver has a relatively independent mark, when a module is abnormal in the test process, the error log can point to the related module, such as the error of the related modules like the EMMC (embedded multimedia Card), the DDR (Double Data Rate), the TUNER (radio coordinator) and so on, can obviously get the information from the error log, but the output of the error log is the premise that the system on chip operates normally, if the system on chip makes a mistake, no information can be output, and in this case, the problem cannot be analyzed through the wrong information. The problem related to the depth abnormality of the system is the most troublesome and time-consuming problem in the aging experiment.
Disclosure of Invention
In view of the above problems in the prior art, a method for distinguishing the crash problem through the fault test is provided.
The specific technical scheme is as follows:
a method for distinguishing a crash problem through fault testing is used for an intelligent television, and comprises the following steps:
step S1, carrying out a plurality of different types of fault tests on the system on chip to obtain a plurality of reaction conditions of the system on chip corresponding to different types of fault types, summarizing the plurality of reaction conditions, and storing the reaction conditions and the corresponding fault types in a storage unit;
and step S2, matching the corresponding reaction information of the system on chip to be tested with the reaction condition stored in the storage unit to obtain the current fault type of the system on chip to be tested.
Preferably, in the step S1, for each of the reaction situations of the soc, corresponding reaction information is obtained, where the reaction information includes a screen display and a correspondingly generated error log.
Preferably, the system on chip comprises a power module; and/or a memory module; and/or a radio tuner module.
Preferably, in step S1, the fault test on the power module includes a fixed pin short circuit test; and/or crystal oscillator output short circuit testing.
Preferably, in step S1, the failure test on the memory module includes a memory clock data short circuit test; and/or memory data line short circuit testing.
Preferably, in the step S1, in the step S1, the fault test of the radio tuner module includes a short circuit test of a positive phase power input pin and a negative phase power input pin; and/or short circuit test of a positive phase clock signal pin of the low-voltage differential signal and a negative phase clock signal pin of the low-voltage differential signal; and/or a short circuit test of a positive phase clock signal pin of the high-definition multimedia interface and a negative phase clock signal pin of the high-definition multimedia interface.
Preferably, the fixed pin short test comprises a memory short test.
Preferably, the fixed pin short circuit test comprises a graphics processor short circuit test.
Preferably, the fixed pin short circuit test includes a cpu short circuit test.
Preferably, the fixed pin short circuit test includes a short circuit test of a power supply regulation output pin of 3.3V or a voltage analog front end pin of 1.8V.
The technical scheme of the invention has the beneficial effects that: according to the method, the corresponding reaction information of the system on chip to be tested is matched with the reaction condition stored in the storage unit to obtain the current fault type of the system on chip to be tested, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a flowchart illustrating steps of a method for distinguishing crash problems through fault testing according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
In the prior art, because the ambient temperature is greatly different from the normal temperature in the aging process, the change of the temperature can cause the performance of a semiconductor to have some differences, such as the increase of leakage current; the low temperature will cause the effective capacitance value of the capacitor to decrease, the variation will cause the ripple of the power supply to become large, the load will become large as long as the system has sudden operation, the system will be likely to be crashed, and the monitoring of the power supply of a plurality of experiment platforms and a plurality of modules through the instrument is difficult to realize under the condition of high temperature or low temperature.
Therefore, in order to solve the above problems in the prior art, the present invention discloses a method for distinguishing a crash problem through a fault test, which is used for a smart tv, and comprises:
step S1, performing a plurality of different types of fault tests on the SOC to obtain a plurality of reaction conditions corresponding to different types of fault types, summarizing the reaction conditions, and storing the reaction conditions and the corresponding fault types in a storage unit;
and step S2, matching the corresponding reaction information of the system on chip to be tested with the reaction condition stored in the storage unit to obtain the current fault type of the system on chip to be tested.
Through the technical scheme of the method for distinguishing the crash problem through the fault test, as shown in fig. 1, the method is applied to an intelligent television, fault tests of a plurality of different types are carried out on a system on chip, so that a plurality of reaction conditions of the system on chip corresponding to the fault types of the different types are obtained, the plurality of reaction conditions are summarized and are stored in a storage unit together with the corresponding fault types, wherein the system on chip comprises a power module; and/or a memory module; and/or the radio tuner module is matched with the reaction condition stored in the storage unit according to the corresponding reaction information of the system on chip to be tested so as to obtain the current fault type of the system on chip to be tested, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
In a preferred embodiment, in step S1, corresponding response information is obtained for each response of the soc, and the response information includes a screen display and a corresponding generated error log. Images of various hardware abnormal states can be associated with the error log in a short time, a good example is provided for analyzing the vulnerability of random crash, and a good example is provided for further positioning problems and eliminating the problems.
In a preferred embodiment, as shown in the first chart, in step S1, the fault test for the power module includes a pin short test; and/or crystal oscillator output short circuit testing. The fixed pin short circuit test comprises a memory short circuit test, a graphic processor short circuit test, a central processing unit short circuit test and a short circuit test of a 3.3V power supply adjustment output pin or a 1.8V voltage simulation front end pin.
Specifically, when the memory is tested for short circuit, the picture corresponding to the DDR _1V2 is displayed as a lost picture, a red screen, and/or the generated error log is dead, the printing is stopped, and no obvious error indication is given; the screen corresponding to DDR _2V5 appears as screen lost, blank screen, and/or the generated error log is dead, printing stops, with no apparent error indication.
Further, when the graphic processor is subjected to short circuit test, the corresponding picture is displayed as picture disappearance, a black screen and/or a generated error log is dead, printing is stopped, and no obvious error indication exists; when the CPU is in short circuit test, the corresponding picture is displayed as still, and/or the generated error log is dead, the printing is stopped, and no obvious error indication exists; when the 3.3V power supply adjustment output pin is subjected to short circuit test, the corresponding picture is displayed as system restart, and/or the generated error log is printed without abnormal condition before restart; when the voltage of 1.8V simulates the short-circuit test of the front-end pin, the corresponding picture is displayed as picture disappearance, black screen and/or the generated error log is dead halt, the printing is stopped, and no obvious error indication exists; when the crystal oscillator outputs a short circuit test, the corresponding picture is displayed as picture disappearance, a red screen and/or a generated error log is dead, printing is stopped, and no obvious error indication exists. Furthermore, images of various hardware abnormal states can be associated with the error logs in a short time, and a good example is provided for analyzing the vulnerability of random crash, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
Watch 1
| Interference mode | On-screen display | Error log prompting |
| Short DDR _1V2 | Disappearing picture and red screen | Halt, stop printing, no obvious error prompt |
| Short DDR _2V5 | Disappearing picture and black screen | Halt, stop printing, no obvious error prompt |
| Short circuit VDDEE (GPU) | Disappearing picture and black screen | Halt, stop printing, no obvious error prompt |
| Short circuit VCCK (CPU) | Still picture | Halt, stop printing, no obvious error prompt |
| Short circuit AO _3.3V | System restart | Exception printing before restart |
| Short circuit AFE _1.8V | Disappearing picture and black screen | Halt, stop printing, no obvious error prompt |
| Short circuit crystal oscillator output | Disappearing picture and red screen | Halt, stop printing, no obvious error prompt |
Further, a plurality of different types of fault tests are performed on the system-on-chip to obtain a plurality of reaction conditions of the system-on-chip corresponding to the different types of fault types, the plurality of reaction conditions are collected and stored in a storage unit together with the corresponding fault types, and then the reaction conditions stored in the storage unit are matched according to the corresponding reaction information of the system-on-chip to be tested to obtain the current fault type of the system-on-chip to be tested.
In a preferred embodiment, the failure test of the memory module in step S1 includes a memory clock data short circuit test; and/or memory data line short circuit testing.
Specifically, as shown in the second graph, when the DDR clock data of the memory is subjected to a short circuit test, the corresponding picture is displayed as a picture disappeared, a screen is red, and/or the generated error log is a dead halt restart, and no obvious error indication exists; or when the memory EMMC clock data is subjected to short circuit test, the corresponding picture is displayed as a still picture, and/or the generated error log is normally output by printing to prompt an EMMC error; when the data line of the memory EMMC is subjected to short-circuit test, the corresponding picture is displayed to be normal, and/or the generated error log is printed and normally output to prompt EMMC errors. Furthermore, images of various hardware abnormal states can be associated with the error logs in a short time, and a good example is provided for analyzing the vulnerability of random crash, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
In a preferred embodiment, in step S1, the fault test for the radio tuner module includes a short circuit test of the positive phase power input pin and the negative phase power input pin; and/or short circuit test of a positive phase clock signal pin of the low-voltage differential signal and a negative phase clock signal pin of the low-voltage differential signal; and/or a short circuit test of a positive phase clock signal pin of the high-definition multimedia interface and a negative phase clock signal pin of the high-definition multimedia interface.
Specifically, as shown in the second diagram, when the positive-phase power input pin and the negative-phase power input pin are subjected to a short-circuit test, the corresponding picture is displayed as a still picture, the picture is recovered to be normal after the interference is stopped, and/or the generated error log is printed for normal output to prompt no signal output; when a positive phase clock signal pin of the low-voltage differential signal and a negative phase clock signal pin of the low-voltage differential signal are subjected to short circuit test, a corresponding picture is displayed as a lost picture, the picture is normal after the interference is stopped, and/or a generated error log indicates that the printing is not abnormal; when the positive phase clock signal pin of the high-definition multimedia interface and the negative phase clock signal pin of the high-definition multimedia interface are subjected to short circuit test, the corresponding picture is displayed as a lost picture, the picture is normal after the interference is stopped, and/or the generated error log is normally output after printing, so that no signal output is prompted. Furthermore, images of various hardware abnormal states can be associated with the error logs in a short time, and a good example is provided for analyzing the vulnerability of random crash, so that the problem can be quickly positioned or the range of the problem can be narrowed through the elimination method, and a good example is provided for eliminating the problem.
Watch two
Further, a plurality of different types of fault tests are performed on the system-on-chip to obtain a plurality of reaction conditions of the system-on-chip corresponding to the different types of fault types, the plurality of reaction conditions are collected and stored in a storage unit together with the corresponding fault types, and then the reaction conditions stored in the storage unit are matched according to the corresponding reaction information of the system-on-chip to be tested to obtain the current fault type of the system-on-chip to be tested.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A method for distinguishing a crash problem through fault testing is used for an intelligent television, and is characterized by comprising the following steps:
step S1, carrying out a plurality of different types of fault tests on the system on chip to obtain a plurality of reaction conditions of the system on chip corresponding to different types of fault types, summarizing the plurality of reaction conditions, and storing the reaction conditions and the corresponding fault types in a storage unit;
step S2, matching the corresponding reaction information of the system-on-chip to be tested with the reaction condition stored in the storage unit to obtain the current fault type of the system-on-chip to be tested;
in step S1, corresponding reaction information is obtained for each of the reaction conditions of the soc, where the reaction information includes a screen display and a correspondingly generated error log.
2. The method of distinguishing between crash problems via fault testing of claim 1 wherein said system on a chip includes a power module; and/or a memory module; and/or a radio tuner module.
3. The method for distinguishing the crash problem through the fault test according to claim 2, wherein in the step S1, the fault test on the power module comprises a fixed pin short circuit test; and/or crystal oscillator output short circuit testing.
4. The method for distinguishing between crash problems through failure testing of claim 2 wherein in said step S1, the failure testing of said memory module includes a memory clock data short circuit test; and/or memory data line short circuit testing.
5. The method for distinguishing the crash problem through the fault test as claimed in claim 2, wherein in the step S1, the fault test for the radio tuner module comprises a short circuit test of a positive phase power input pin and a negative phase power input pin; and/or short circuit test of a positive phase clock signal pin of the low-voltage differential signal and a negative phase clock signal pin of the low-voltage differential signal; and/or a short circuit test of a positive phase clock signal pin of the high-definition multimedia interface and a negative phase clock signal pin of the high-definition multimedia interface.
6. The method of differentiating dead halt problems with fault testing of claim 3 wherein said fixed pin short circuit test comprises a memory short circuit test.
7. The method of differentiating dead halt problems with fault testing of claim 3 wherein said fixed pin short circuit test comprises a graphics processor short circuit test.
8. The method of differentiating dead halt problems with fault testing of claim 3 wherein said fixed pin short circuit test comprises a central processor short circuit test.
9. The method of distinguishing between crash problems via fault testing of claim 3 wherein the fixed pin short circuit test comprises a short circuit test of a 3.3V supply regulated output pin or a 1.8V voltage analog front end pin.
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| US8026726B2 (en) * | 2009-01-23 | 2011-09-27 | Silicon Image, Inc. | Fault testing for interconnections |
| CN104460649A (en) * | 2014-10-21 | 2015-03-25 | 北京汽车股份有限公司 | Fault testing circuit and method |
| CN107027063B (en) * | 2017-04-19 | 2020-03-20 | 广州视源电子科技股份有限公司 | Recording playback method and system for detecting television menu function |
| CN107783005B (en) * | 2017-10-11 | 2020-07-31 | 广东小天才科技有限公司 | Method, device, device, system and storage medium for equipment fault diagnosis |
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