CN104182290A - Debugging device and debugging method - Google Patents
Debugging device and debugging method Download PDFInfo
- Publication number
- CN104182290A CN104182290A CN201310196117.7A CN201310196117A CN104182290A CN 104182290 A CN104182290 A CN 104182290A CN 201310196117 A CN201310196117 A CN 201310196117A CN 104182290 A CN104182290 A CN 104182290A
- Authority
- CN
- China
- Prior art keywords
- detection signal
- start detection
- storage element
- information code
- execution time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a debugging device and a debugging method, which are applied to a server comprising a control chip. The debugging device comprises a first signal transmission unit, a processing unit, a first storage unit and a second storage unit, wherein the first signal processing unit is coupled to the control chip, and is used for receiving a startup detection signal; the processing unit is coupled to the first signal processing unit, and is used for receiving the startup detection signal, and acquiring an information code of the startup detection signal and execution time corresponding to the information code of the startup detection signal; the first storage unit is coupled to the processing unit, and is used for storing the information code of the startup detection signal; the second storage unit is coupled to the processing unit, and is used for storing the execution time of the startup detection signal. According to the debugging device, a startup program can be simply checked whether to be abnormal or not to prevent the dead halt of the server.
Description
Technical field
The present invention relates to a kind of apparatus for debugging, particularly a kind of apparatus for debugging and debug method that is suitable for a server.
Background technology
In current server, when startup of server, Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) will be activated at first, to allow Basic Input or Output System (BIOS) carry out complete check and test to the hardware device in server, this check with test action be otherwise known as start selftest (Power On Self Test, POST).And hardware device in server is by after check and test, Basic Input or Output System (BIOS) just can be given the hardware information in server operating system, allows operating system continue the flow process of start.But, if having certain element or certain procedure operation in server when not normal, will make boot program rest on certain outpost of the tax office and cannot continue normal boot-strap.
Therefore, in boot program, do not enter operating system before, while there is the abnormal situation of start, as long as go for out the code of specific input/output port (IO Port), Port80 for example, finding out the corresponding examination phase of this code, there is the abnormal situation of running in which element that just can detect server again.The most often apply at present the mode of debug for utilizing the debug module (Debug Module) being disposed on motherboard to capture the code of Port80, and the code of Port80 is shown, for user, judge whether server produces error condition.
Yet, limited space due to the motherboard of server, manufacturer is under various considering, tend to when shipment debug module removal from motherboard, that is can not dispose debug module on the motherboard of shipment, so just cannot learn the information of the code of Port80, and cause after the motherboard volume production of subsequent server, be difficult for carrying out debug and error analysis.Therefore, how to provide a simple and effective apparatus for debugging to user, will be an important problem.
Summary of the invention
The object of the invention is to propose a kind of apparatus for debugging and debug method, can allow user when carrying out debug program, and do not go for the information meaning of seeking error message requiring a great deal of time, and can save the time of user's scrutiny program and promote usefulness.
A kind of apparatus for debugging of the present invention, is suitable for a server, and this server comprises a control chip.This apparatus for debugging includes first signal transmission unit, processing unit, the first storage element and the second storage element.First signal transmission unit is coupled to control chip, in order to receive a start detection signal.Processing unit is coupled to first signal transmission unit, in order to receive start detection signal, and captures the information code of this start detection signal, and the execution time of the start detection signal of corresponding informance code.The first storage element is coupled to processing unit, in order to store the information code of start detection signal.The second storage element is coupled to processing unit, in order to store the execution time of start detection signal.
According to one embodiment of the invention, aforementioned apparatus for debugging more includes secondary signal transmission unit.Secondary signal transmission unit is coupled to the first storage element and the second storage element, in order to export the information code of the first storage element and the execution time of output the second storage element.
According to one embodiment of the invention, aforementioned secondary signal transmission unit includes baseboard management controller (Baseboard Management Controller, BMC) interface.
According to one embodiment of the invention, aforementioned first signal transmission unit includes low pin number interface (Low Pin Count, LPC).
According to one embodiment of the invention, the first signal transmission unit of aforementioned apparatus for debugging is more coupled to the first storage element and the second storage element.First signal transmission unit is in order to export the information code of the first storage element, and the execution time of the second storage element is to control chip.
The present invention also proposes a kind of debug method, is applicable on a server, and this server comprises a control chip.This debug method comprises the following step.Receive the start detection signal that control chip produces.The information code of acquisition start detection signal, and the execution time of the start detection signal of corresponding informance code.Store the information code of start detection signal.Store the execution time of start detection signal.
According to one embodiment of the invention, aforementioned debug method more includes the information code of output start detection signal, and the execution time of output start detection signal.
According to one embodiment of the invention, aforementioned debug method includes the following step.Utilize first signal transmission unit to export the information code of the start detection signal in the first storage element, and the execution time of the start detection signal in output the second storage element.
According to one embodiment of the invention, aforementioned debug method includes the following step.Utilize secondary signal transmission unit to export the information code of the start detection signal in the first storage element, and the execution time of the start detection signal in output the second storage element.
Comprehensive the above, apparatus for debugging and its debug method by one embodiment of the invention can reach: user can, from the table of information code and the table of the execution time in the second storage element of corresponding informance code in the first storage element, simply find out that the execution time of which program is too short or too fast.If the execution time that has a program too soon or too slow, user can directly test for the program of query so.Saved in the past in order to test out which program has problem and plenty of time of spending.
Below in conjunction with the drawings and specific embodiments, describe the present invention, but not as a limitation of the invention.
Accompanying drawing explanation
Fig. 1 is according to the block diagram of the server of one embodiment of the invention;
Fig. 2 is the block diagram of server according to another embodiment of the present invention;
Fig. 3 is the debug method process flow diagram according to one embodiment of the invention;
Fig. 4 is debug method process flow diagram according to another embodiment of the present invention.
Wherein, Reference numeral
100 servers
110 apparatus for debugging
120 first signal transmission units
130 processing units
140 first storage elements
150 second storage elements
160 secondary signal transmission units
170 control chips
172 CPU (central processing unit)
174 memory bodys
176 basic input/output systems
178 baseboard management controllers
Embodiment
In embodiment, describe below detailed features of the present invention and advantage in detail, its content is enough to make any related art techniques person of haveing the knack of understand technology contents of the present invention and implement according to this, and the content of inventing according to this instructions, claim scope and accompanying drawing, any related art techniques person of haveing the knack of can understand object and the advantage that the present invention is relevant easily.Following embodiment further describes viewpoint of the present invention, but non-to limit anyways category of the present invention.
Please refer to Fig. 1, it is according to the block diagram of the server of one embodiment of the invention.Server 100 includes a control chip 170, a CPU (central processing unit) (Central Processing unit, CPU) 172, one memory body (Dual In-line Memory Module, DIMM) 174, one Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) 176, one baseboard management controller (Baseboard Management Controller, BMC) and apparatus for debugging of the present invention 110.Wherein, CPU (central processing unit) 172 couples memory body 174, and control chip 170 is coupled to CPU (central processing unit) 172 and basic input/output system 176.
And control chip 170 for example couples CPU (central processing unit) 172 by direct media interface (Direct Media Interface, DMI) bus.Control chip 170 for example couples Basic Input or Output System (BIOS) 176 by serial circumference interface (Serial Peripheral Interface, SPI) bus.And control chip 170 can be the South Bridge chip on motherboard (South Bridge Chip, SB Chip) or platform control hub (Platform Controller Hub, PCH) chip, but not as limit.Therefore the chipset that, has a function of said chip can be the control chip 170 in embodiments of the invention.Wherein, CPU (central processing unit) 172, memory body 174 are not emphasis of the present invention with Basic Input or Output System (BIOS) memory body 176, therefore do not repeat them here.
Apparatus for debugging 110 includes a first signal transmission unit 120, a processing unit 130, one first storage element 140, one second storage element 150 and a secondary signal transmission unit 160.
First signal transmission unit 120 couples control chip 170, and first signal transmission unit 120 can comprise a low pin number (Low Pin Count, LPC) interface.First signal transmission unit 120 is in order to receive a start detection signal from control chip 170.Processing unit 130 coupled with first signal transmission units 120, in order to receive start detection signal.After processing unit 130 receives start detection signal, can capture the information code in start detection signal, and an execution time of the start detection signal of acquisition corresponding informance code.
The first storage element 140 is coupled to the information code that processing unit 130, the first storage elements 140 go out from start inspection signal acquisition in order to store processing unit 130.The second storage element 150 is coupled to processing unit 130, the second storage elements 150 in order to store the execution time of the start detection signal of corresponding informance code.Wherein, the first storage element 140 and the second storage element 150 can be Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) or SRAM (Static random access memory, and any memory storage that has above-mentioned feature SRAM).
In practical application, Basic Input or Output System (BIOS) 176 can store a plurality of start selftest codes (Power On Self Test Code, POST Code) in advance, is used for representing the stage of different start selftests.When server 100 will enter the stage of certain start selftest, the start selftest yardage value of this stage representative can be sent to specific input/output port (IO Port), for example Port80.
According in one embodiment of the invention, control chip 170 can transmit the start detection signal of corresponding start selftest code.First signal transmission unit 120 receives after aforementioned start detection signal, can send start detection signal to processing unit 130.Then, processing unit 130 can capture out by the information code of start detection signal, and in start detection signal execution time of corresponding informance code.Wherein, this information code corresponding aforementioned start selftest code for example.After processing unit 130 captures the execution time of information code and corresponding informance code, can respectively information code be stored in to the first storage element 140 and the execution time of corresponding informance code is stored in to the second storage element 150.
The apparatus for debugging 110 of the present embodiment more includes a secondary signal transmission unit 160.Secondary signal transmission unit 160 is coupled to baseboard management controller 178, the first storage element 140 and the second storage element 150.Secondary signal transmission unit 160 is in order to export the information code storing in the first storage element 140, and the execution time storing in output the second storage element 150 is to baseboard management controller 178.
When user learns the situation in the start process of server 100, can, by baseboard management controller 178 via secondary signal transmission unit 160, read the information code of the first storage element 140 and the execution time of the second storage element 150.Then, baseboard management controller 178 is for example sent to a display unit by read information code and execution time, to demonstrate information code and execution time so that the execution time that allows user can inspect information code and corresponding informance code whether produce extremely.
Furthermore, user can compare the execution time of the shown corresponding informance code of display unit and a default execution time, with confirm server 100 in start process, be have produce abnormal.For instance, when comparing out the execution time when exceeding or being shorter than the default execution time, represent that server 100 produces abnormality, user can be by the information code that finds corresponding this execution time, and learns that server 100 produces mistake in the program of which start process.Even if the program of all start process can completely be carried out, but the above-mentioned long or too short execution time may be the sign that program goes wrong.Therefore, user just can safeguard or upgrade for long or too short program of execution time, avoids whole boot program to be dragged situation slow or even crash (Shut Down).
Please refer to shown in Fig. 2, it is the block diagram of server according to another embodiment of the present invention.Inner member, coupling mode and the associative operation thereof of the server 200 of the present embodiment is similar to the server 100 of Fig. 1, can be with reference to the explanation of the embodiment of figure 1, therefore do not repeat them here.Wherein, the first signal transmission unit 120 of server 200 more couples the first storage element 140 and the second storage element 150, in order to export the information code of the first storage element 140 and the execution time of the second storage element 150 to control chip 170.Then, control chip 170 for example can be sent to a display unit by read information code and execution time, to demonstrate information code and execution time so that the execution time that allows user can inspect information code and corresponding informance code whether produce extremely.And whether server 100 produces abnormal mode, can be with reference to the explanation of the embodiment of figure 1, therefore do not repeat them here.
In the present embodiment, except can be by the stored information code of secondary signal transmission unit 160 output the first storage elements 140 and the second storage element 150 stored execution time, also can be by the execution time of the information code of corresponding start detection signal in the stored information code of first signal transmission unit 120 output the first storage elements 140 and the second storage element 150.Thus, user can pass through baseboard management controller 178 or control chip 170, require anywhere or anytime secondary signal transmission unit 160 or first signal transmission unit 120, export the stored information code of the first storage element 140 and the second stored execution time of storage element 150, to inspect server 100, whether there are any abnormal conditions to occur, and then increase the convenience using.
According in aforementioned enumerated embodiment, can summarize a kind of debug method.Please refer to Fig. 3, it is the debug method process flow diagram according to one embodiment of the invention.In step S200, receive the start detection signal that control chip produces.In step S210, the information code of acquisition start detection signal, and the execution time of the start detection signal of corresponding informance code.In step S220, store the information code of start detection signal.In step S230, store the execution time of start detection signal.
Please refer to Fig. 4, it is debug method process flow diagram according to another embodiment of the present invention.In step S200, receive the start detection signal that control chip produces.In step S210, the information code of acquisition start detection signal, and the execution time of the start detection signal of corresponding informance code.In step S220, store the information code of start detection signal.In step S230, store the execution time of start detection signal.In step S240, the information code of output start detection signal and the execution time of start detection signal.
Furthermore, in one embodiment, step S240 comprises and utilizes first signal transmission unit, the information code of the start detection signal in output the first storage element, and the execution time of the start detection signal in the second storage element.In another embodiment, step S240 comprises and utilizes secondary signal transmission unit, this information code of the start detection signal in output the first storage element, and the execution time of the start detection signal in the second storage element.
Comprehensive the above, the apparatus for debugging of one embodiment of the invention is with debug method, by processing unit, pass through first signal transmission unit, receive the start detection signal that control chip produces, and capture execution time of information code and corresponding this information code of start detection signal, and storing information code and execution time, then by the first transmission unit or the second transmission unit output information code and execution time.Thus, can simply learn in the start process of server, whether there is something special abnormal, to increase efficiency and the convenience of debug.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. an apparatus for debugging, is suitable for a server, and this server comprises a control chip, it is characterized in that, this apparatus for debugging comprises:
One first signal transmission unit, couples this control chip, in order to receive a start detection signal;
One processing unit, couples this first signal transmission unit, in order to receive this start detection signal, and captures an information code of this start detection signal, and the execution time to this start detection signal that should information code;
One first storage element, couples this processing unit, in order to store this information code of this start detection signal; And
One second storage element, couples this processing unit, in order to store this execution time of this start detection signal.
2. apparatus for debugging according to claim 1, is characterized in that, more comprises:
One secondary signal transmission unit, couples this first storage element and this second storage element, in order to export this information code of this first storage element and this execution time of this second storage element.
3. apparatus for debugging according to claim 2, is characterized in that, this secondary signal transmission unit comprises a baseboard management controller interface.
4. apparatus for debugging according to claim 1, is characterized in that, this first signal transmission unit comprises a low pin number interface.
5. apparatus for debugging according to claim 1, it is characterized in that, this first signal transmission unit more couples this first storage element and this second storage element, in order to export this information code of this first storage element and this execution time of this second storage element to this control chip.
6. a debug method, is applicable on a server, and this server comprises a control chip, it is characterized in that, this debug method comprises:
Receive the start detection signal that this control chip produces;
Capture an information code of this start detection signal, and the execution time to this start detection signal that should information code;
Store this information code of this start detection signal; And
Store this execution time of this start detection signal.
7. debug method according to claim 6, is characterized in that, more comprises:
Export this information code of this start detection signal and this execution time of this start detection signal.
8. debug method according to claim 7, is characterized in that, comprises:
Utilize a first signal transmission unit, export this information code of this start detection signal in this first storage element, and this execution time of this start detection signal in this second storage element.
9. debug method according to claim 7, is characterized in that, comprises:
Utilize a secondary signal transmission unit, export this information code of this start detection signal in this first storage element, and this execution time of this start detection signal in this second storage element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310196117.7A CN104182290A (en) | 2013-05-23 | 2013-05-23 | Debugging device and debugging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310196117.7A CN104182290A (en) | 2013-05-23 | 2013-05-23 | Debugging device and debugging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104182290A true CN104182290A (en) | 2014-12-03 |
Family
ID=51963364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310196117.7A Pending CN104182290A (en) | 2013-05-23 | 2013-05-23 | Debugging device and debugging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104182290A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101411A1 (en) * | 2014-12-25 | 2016-06-30 | 中兴通讯股份有限公司 | Server display method and device |
| CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
| CN112634977A (en) * | 2019-09-24 | 2021-04-09 | 新唐科技股份有限公司 | Chip with debugging memory interface and debugging method thereof |
| CN114385247A (en) * | 2020-10-21 | 2022-04-22 | 环达电脑(上海)有限公司 | Starting-up method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030163765A1 (en) * | 1998-12-29 | 2003-08-28 | Donald J. Eckardt | Method and apparatus for providing diagnosis of a processor without an operating system boot |
| CN1983179A (en) * | 2005-12-15 | 2007-06-20 | 英业达股份有限公司 | Boot self-test debugging system and method |
| KR20090016286A (en) * | 2007-08-10 | 2009-02-13 | 엘지전자 주식회사 | Computer system and its boot control method |
| CN102819473A (en) * | 2011-06-08 | 2012-12-12 | 联想(北京)有限公司 | Method for detecting faults of computer, computer and display device |
-
2013
- 2013-05-23 CN CN201310196117.7A patent/CN104182290A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030163765A1 (en) * | 1998-12-29 | 2003-08-28 | Donald J. Eckardt | Method and apparatus for providing diagnosis of a processor without an operating system boot |
| CN1983179A (en) * | 2005-12-15 | 2007-06-20 | 英业达股份有限公司 | Boot self-test debugging system and method |
| KR20090016286A (en) * | 2007-08-10 | 2009-02-13 | 엘지전자 주식회사 | Computer system and its boot control method |
| CN102819473A (en) * | 2011-06-08 | 2012-12-12 | 联想(北京)有限公司 | Method for detecting faults of computer, computer and display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101411A1 (en) * | 2014-12-25 | 2016-06-30 | 中兴通讯股份有限公司 | Server display method and device |
| CN105786421A (en) * | 2014-12-25 | 2016-07-20 | 中兴通讯股份有限公司 | Server display method and device |
| CN105786421B (en) * | 2014-12-25 | 2020-11-03 | 中兴通讯股份有限公司 | Server display method and device |
| CN112634977A (en) * | 2019-09-24 | 2021-04-09 | 新唐科技股份有限公司 | Chip with debugging memory interface and debugging method thereof |
| CN112634977B (en) * | 2019-09-24 | 2023-11-17 | 新唐科技股份有限公司 | Chip with debug memory interface and debug method thereof |
| CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
| CN112579178B (en) * | 2019-09-29 | 2022-04-05 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
| CN114385247A (en) * | 2020-10-21 | 2022-04-22 | 环达电脑(上海)有限公司 | Starting-up method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8370816B2 (en) | Device, method and computer program product for evaluating a debugger script | |
| CN106055438A (en) | Method and system for rapidly locating anomaly of memory banks on mainboard | |
| CN107111595B (en) | Method, device and system for detecting early boot errors | |
| US20070220228A1 (en) | Computer memory configuration inspection method and system | |
| CN104182290A (en) | Debugging device and debugging method | |
| US20140143601A1 (en) | Debug device and debug method | |
| TWI497279B (en) | Debug device and debug method | |
| CN113535509A (en) | Memory bank abnormity detection method and device and BMC | |
| CN115292113B (en) | Method and device for fault detection of internal memory of server and electronic equipment | |
| US10289467B2 (en) | Error coordination message for a blade device having a logical processor in another system firmware domain | |
| US11593209B2 (en) | Targeted repair of hardware components in a computing device | |
| CN102053888A (en) | Self-testing method and system for computing device | |
| CN115934446A (en) | A self-test method, server, device and storage medium | |
| CN116521414A (en) | Fault code positioning method, cloud server, system and storage medium | |
| CN115756935A (en) | Abnormal fault positioning method, device and equipment of embedded software system | |
| CN111061603B (en) | Motherboard capable of recording self-checking data, computer and recording method of self-checking data | |
| US10846162B2 (en) | Secure forking of error telemetry data to independent processing units | |
| US8489927B2 (en) | Device for use in inspecting a CPU and method thereof | |
| CN102567159B (en) | Memory detecting method | |
| US20190179721A1 (en) | Utilizing non-volatile phase change memory in offline status and error debugging methodologies | |
| CN113220510A (en) | Device detection method, detection device, and computer-readable storage medium | |
| CN113535494B (en) | Equipment debugging method and electronic equipment | |
| TWI823556B (en) | Memory abnormality detection system, motherboard, electronic device and abnormality detection method | |
| CN114780283B (en) | Fault processing method and device | |
| US20070179635A1 (en) | Method and article of manufacure to persistently deconfigure connected elements |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20141203 |