CN109756104B - Two-phase dynamic synchronous clock generation circuit applied to charge pump system - Google Patents
Two-phase dynamic synchronous clock generation circuit applied to charge pump system Download PDFInfo
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- CN109756104B CN109756104B CN201711083315.7A CN201711083315A CN109756104B CN 109756104 B CN109756104 B CN 109756104B CN 201711083315 A CN201711083315 A CN 201711083315A CN 109756104 B CN109756104 B CN 109756104B
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Abstract
The invention relates to a two-phase dynamic synchronous clock generation circuit applied to a charge pump system, which comprises a first path of ring oscillator and a second path of ring oscillator. The two-phase dynamic synchronous clock generating circuit applied to the charge pump system realizes the effect of dynamic synchronization by mutual pushing and acceleration when the output clock signal generates the asynchronous change of the phase through the two-path interactive ring oscillator structure, can be suitable for occasions with higher requirements on frequency and phase synchronization, and has better application value.
Description
Technical Field
The invention relates to the technical field of digital chips, in particular to the technical field of clock synchronization, and particularly relates to a two-phase dynamic synchronous clock generation circuit applied to a charge pump system.
Background
In digital chip systems, the clock signal occupies a very important place. Such as digital to analog converter ADC, data interface circuits, charge pump circuits, etc., all require an accurate clock signal. The clock signal is typically generated by an external clock source or crystal oscillator, but when the external clock source cannot provide the required frequency and phase, a clock generation circuit is required to be designed inside the chip to generate the clock signal. In standard CMOS processes, ring oscillators are typically used to generate the oscillation frequency.
Referring to fig. 1, a schematic circuit structure of a ring oscillator in the prior art is shown, the circuit structure is relatively simple, the integration level is high, the oscillation frequency is determined by the delay time of the inverter, the size of the capacitor and the number of stages of the inverter, and the capacitor is usually a MOS capacitor.
Fig. 2 is a schematic circuit structure diagram of a two-phase dynamic synchronous clock generating circuit in the prior art, in which an RS flip-flop is added to convert one-phase clock into two-phase inverted clocks, but the two-phase clock generated by the method has poor phase synchronization effect due to delay of a gate circuit, and is not suitable for use particularly when the frequency is fast and the synchronization requirement is high.
If the two-phase clock is generated by the method of fig. 1 and 2, the two clock signals may be phase-shifted more due to the higher frequency requirement of the oscillator and the small gate delay. The charge pump has higher synchronous requirement on two non-overlapping clocks, and the capacitor on one side needs to be opened and the capacitor on the other side needs to be turned off in time, otherwise, the problem of current leakage can occur, and the high voltage required by the circuit can not be output.
Disclosure of Invention
The present invention has been made to overcome at least one of the above-mentioned drawbacks of the prior art, and provides a two-phase dynamic synchronous clock generating circuit for a charge pump system, which can achieve a better clock synchronization effect.
In order to achieve the above object, a two-phase dynamic synchronous clock generating circuit applied to a charge pump system of the present invention has the following constitution:
the two-phase dynamic synchronous clock generating circuit applied to the charge pump system is mainly characterized by comprising:
the first path of ring oscillator is formed by connecting odd-level oscillation modules end to end and is used for generating synchronous clock signals;
the second path of ring oscillator is formed by connecting odd-level oscillation modules end to end and interacts with the first path of ring oscillator to generate synchronous clock signals;
the input ends of the at least two inverters are respectively connected with the output ends of the same-stage oscillating module of the two-phase dynamic synchronous clock generating circuit and are used for filtering the output signals of the two-phase dynamic synchronous clock generating circuit, and the output ends of the at least two inverters output the signals of the two-phase dynamic synchronous clock generating circuit through the output ports.
The output end of the odd-numbered stage oscillating module of the first path of ring oscillator and the output end of the odd-numbered stage oscillating module of the second path of ring oscillator are respectively connected with the input end of the corresponding odd-numbered stage oscillating module of the first path of ring oscillator, and the output end of the odd-numbered stage oscillating module of the first path of ring oscillator and the output end of the odd-numbered stage oscillating module of the second path of ring oscillator are respectively connected with the input end of the corresponding odd-numbered stage oscillating module of the first path of ring oscillator.
The first path of ring oscillator applied to the two-phase dynamic synchronous clock generating circuit of the charge pump system comprises a first oscillator module, a first oscillator sub-module, a second oscillator sub-module, a third oscillator sub-module and a fourth oscillator sub-module, wherein the second path of ring oscillator comprises a second oscillator module, a fifth oscillator sub-module, a sixth oscillator sub-module, a seventh oscillator sub-module and an eighth oscillator sub-module.
The first input end of the first oscillator module of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system inputs an enabling signal, the second input end of the first oscillator module inputs the output signal of the fourth oscillator sub-module, the third input end of the first oscillator module inputs the output signal of the fifth oscillator sub-module, the first input end of the first oscillator sub-module inputs the output signal of the first oscillator module, the second input end of the first oscillator sub-module inputs the output signal of the second oscillator module, the first input ends of the second oscillator sub-modules to the fourth oscillator sub-module respectively input the output signals of the first oscillator sub-module to the third oscillator sub-module, the second input ends of the second oscillator sub-module to the fourth oscillator sub-module respectively input the output signals of the sixth oscillator sub-module to the eighth oscillator sub-module,
the first input end of the fifth oscillator sub-module inputs the output signal of the eighth oscillator sub-module, the second input end of the fifth oscillator sub-module inputs the output signal of the first oscillator sub-module, the first input end of the second oscillator sub-module inputs an enabling signal, the second input end of the second oscillator sub-module inputs the output signal of the fifth oscillator sub-module, the third input end of the second oscillator sub-module inputs the output signal of the first oscillator sub-module, the first input end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the second input end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the first input ends of the seventh oscillator sub-module and the eighth oscillator sub-module respectively inputs the output signals of the sixth oscillator sub-module and the seventh oscillator sub-module, and the second input end of the eighth oscillator sub-module respectively inputs the output signals of the fourth oscillator sub-module and the fifth oscillator sub-module.
The output end of the second oscillator sub-module of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system is connected with a third inverter, the third inverter is connected with a third output end, the output end of the fourth oscillator sub-module is connected with a first inverter, the first inverter is connected with a first output end, the output end of the sixth oscillator sub-module is connected with a fourth inverter, the fourth inverter is connected with a fourth output end, the output end of the eighth oscillator sub-module is connected with a second inverter, and the second inverter is connected with a second output end.
The oscillation submodule applied to the two-phase dynamic synchronous clock generation circuit of the charge pump system comprises:
the first-stage CMOS inverter comprises a first PMOS tube and a first NMOS tube, wherein the source electrode of the first PMOS tube inputs power supply voltage, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the second input end of the oscillator sub-module;
the second-stage CMOS inverter comprises a second PMOS tube and a second NMOS tube, wherein the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrodes of the second PMOS tube and the second NMOS tube are both connected with the output end of the oscillation submodule, and the grid electrodes of the second PMOS tube and the second NMOS tube are both connected with the first input end of the oscillation submodule;
the third-stage CMOS inverter comprises a third PMOS tube and a third NMOS tube, wherein the source electrode of the third PMOS tube is input with power supply voltage, the source electrode of the third NMOS tube is grounded, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube are connected with the output end of the oscillation submodule, and the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube are connected with the first input end of the oscillation submodule.
The oscillator starting module applied to the two-phase dynamic synchronous clock generating circuit of the charge pump system comprises:
the fourth-stage CMOS inverter comprises a fourth PMOS tube and a fourth NMOS tube, wherein the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and the output end of the oscillator starting module, and the grid electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube are both connected with the first input end of the oscillator starting module;
the fifth-stage CMOS inverter comprises a fifth PMOS tube and a fifth NMOS tube, wherein the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the grid electrodes of the fifth PMOS tube and the fifth NMOS tube are both connected with the second input end of the oscillator starting module;
the sixth-stage CMOS inverter comprises a sixth PMOS tube and a sixth NMOS tube, wherein the source electrode of the sixth PMOS tube is connected with the source electrode of the fifth PMOS tube, the source electrode of the sixth NMOS tube is grounded, the drain electrode of the sixth PMOS tube and the drain electrode of the sixth NMOS tube are both connected with the output end of the oscillator starting module, and the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube are both connected with the first input end of the oscillator starting module;
the device comprises a seventh PMOS enabling tube and a seventh NMOS enabling tube, wherein an enabling signal is input to the grid electrode of the seventh PMOS enabling tube, a power supply voltage is input to the source electrode of the seventh PMOS enabling tube, the drain electrode of the seventh PMOS enabling tube is connected with the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube, an enabling signal is input to the grid electrode of the seventh NMOS enabling tube, the source electrode of the seventh NMOS enabling tube is grounded, and the drain electrode of the seventh NMOS enabling tube is connected with the output end of the oscillator module.
The output ends of the odd-numbered stage oscillation modules of the first path of ring oscillators and the odd-numbered stage oscillation modules of the second path of ring oscillators of the two-phase dynamic synchronous clock generation circuit applied to the charge pump system are connected with capacitors, and the capacitors are used for changing clock frequency.
The capacitance of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system is MOS capacitance.
The two-phase dynamic synchronous clock generating circuit applied to the charge pump system realizes the effect of dynamic synchronization by mutual pushing and acceleration when the output clock signal generates the asynchronous change of the phase through the two-path interactive ring oscillator structure, can be suitable for occasions with higher requirements on frequency and phase synchronization, and has better application value.
Drawings
Fig. 1 is a schematic circuit diagram of a ring oscillator in the prior art.
Fig. 2 is a schematic circuit diagram of a two-phase dynamic synchronous clock generating circuit in the prior art.
Fig. 3 is a schematic circuit diagram of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention.
Fig. 4 is a schematic diagram of another circuit structure of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system according to the present invention.
Fig. 5 is a schematic circuit diagram of an oscillator module of the two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention.
Fig. 6 is a schematic circuit diagram of a vibrator starting module of the two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention.
Fig. 7 is a schematic circuit diagram of a circuit structure of any one of the two-stage oscillating units of the two-stage ring oscillator applied to the two-phase dynamic synchronous clock generating circuit of the charge pump system.
Fig. 8 is a phase advance timing diagram of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
Fig. 3 is a schematic circuit diagram of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention. The two-phase dynamic synchronous clock generating circuit applied to the charge pump system is mainly characterized by comprising:
the first path of ring oscillator is formed by connecting odd-level oscillation modules end to end and is used for generating synchronous clock signals;
the second path of ring oscillator is formed by connecting odd-level oscillation modules end to end and interacts with the first path of ring oscillator to generate synchronous clock signals;
the input ends of the at least two inverters are respectively connected with the output ends of the same-stage oscillating module of the two-phase dynamic synchronous clock generating circuit and are used for filtering the output signals of the two-phase dynamic synchronous clock generating circuit, and the output ends of the at least two inverters output the signals of the two-phase dynamic synchronous clock generating circuit through the output ports. The difference between the oscillator starting module and the oscillator sub-module is whether an enabling signal exists, when the enabling signal ENL of the oscillator starting module is high, the two-phase dynamic synchronous clock generating circuit applied to the charge pump system does not work, and when ENL is pulled down, the oscillator starting module applied to the two-phase dynamic synchronous clock generating circuit of the charge pump system is enabled, and the oscillator starting module starts to generate an oscillating signal. The input of each stage of oscillation module is the output of the previous stage of oscillation module, and meanwhile, one output signal is used as the feedback control input of the other path to push each other to accelerate overturning.
The output end of the odd-numbered stage oscillating module of the first path of ring oscillator and the output end of the odd-numbered stage oscillating module of the second path of ring oscillator are respectively connected with the input end of the corresponding odd-numbered stage oscillating module of the first path of ring oscillator, and the output end of the odd-numbered stage oscillating module of the first path of ring oscillator and the output end of the odd-numbered stage oscillating module of the second path of ring oscillator are respectively connected with the input end of the corresponding odd-numbered stage oscillating module of the first path of ring oscillator. The first path of ring oscillator comprises a first oscillator module, a first oscillator sub-module, a second oscillator sub-module, a third oscillator sub-module and a fourth oscillator sub-module, the second path of ring oscillator comprises a second oscillator module, a fifth oscillator sub-module, a sixth oscillator sub-module, a seventh oscillator sub-module and an eighth oscillator sub-module, a first input end of the first oscillator module inputs a first enabling signal, a second input end of the first oscillator module inputs an output signal of the fourth oscillator sub-module, a third input end of the first oscillator module inputs an output signal of the fifth oscillator sub-module, a second input end of the first oscillator sub-module inputs an output signal of the first oscillator module, a second input end of the first oscillator sub-module inputs an output signal of the second oscillator module, a first input end of the second oscillator sub-module inputs an output signal of the first oscillator sub-module to the third oscillator sub-module, a first input end of the second oscillator sub-module inputs an output signal of the fifth oscillator sub-module to the fifth oscillator sub-module, a first input end of the second oscillator sub-module inputs an output signal of the second oscillator sub-module to the fifth oscillator sub-module respectively, the first input end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the second output end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the first input ends of the seventh oscillator sub-module and the eighth oscillator sub-module respectively input the output signals of the sixth oscillator sub-module and the seventh oscillator sub-module, and the second input ends of the seventh oscillator sub-module and the eighth oscillator sub-module respectively input the output signals of the fourth oscillator sub-module and the fifth oscillator sub-module.
In practical application, please refer to fig. 3, which is a schematic diagram of a circuit structure of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention. The output end of the second oscillator sub-module applied to the charge pump system is connected with a third inverter, the third inverter is connected with a third output end OUT3, the output end of the fourth oscillator sub-module is connected with a first inverter, the first inverter is connected with a first output end OUT1, the output end of the sixth oscillator sub-module is connected with a fourth inverter, the fourth inverter is connected with a fourth output end OUT4, the output end of the eighth oscillator sub-module is connected with a second inverter, and the second inverter is connected with a second output end OUT2, wherein, as the third output end OUT3 and the first output end OUT1 of the first loop oscillator are different nodes of the same loop oscillator, clocks with different phases can be output, and in the same level nodes of the two loop oscillators applied to the charge pump system, such as the nodes of the two loop oscillators applied to the charge pump system in the two loop oscillator dynamic clock generation circuit, the third output end OUT3 and the first loop oscillator output end OUT1 and the second loop oscillator 2 of the first loop oscillator are the same. In practical applications, the number of output terminals of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system can be set according to specific requirements.
Fig. 5 is a schematic circuit diagram of an oscillator module of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention. The oscillation submodule includes:
the first-stage CMOS inverter comprises a first PMOS tube P1 and a first NMOS tube N1, wherein the source electrode of the first PMOS tube P1 inputs power supply voltage, the source electrode of the first NMOS tube N1 is grounded, and the grid electrode of the first PMOS tube P1 and the grid electrode of the first NMOS tube N1 are both connected with the second input end of the oscillator sub-module;
the second-stage CMOS inverter comprises a second PMOS tube P2 and a second NMOS tube N2, wherein the source electrode of the second PMOS tube P2 is connected with the drain electrode of the first PMOS tube P1, the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2, the source electrode of the second NMOS tube N2 is connected with the drain electrode of the first NMOS tube N1, the drain electrode of the second PMOS tube P2 and the drain electrode of the second NMOS tube N2 are both connected with the output end of the oscillation submodule, and the grid electrode of the second PMOS tube P2 and the grid electrode of the second NMOS tube N2 are both connected with the first input end of the oscillation submodule;
the third-stage CMOS inverter comprises a third PMOS tube P3 and a third NMOS tube N3, wherein the source electrode of the third PMOS tube P3 is input with power supply voltage, the source electrode of the third NMOS tube N3 is grounded, the drain electrode of the third PMOS tube P3 and the drain electrode of the third NMOS tube N3 are both connected with the output end of the oscillation submodule, and the grid electrode of the third PMOS tube P3 and the grid electrode of the third NMOS tube N3 are both connected with the first input end of the oscillation submodule.
Fig. 6 is a schematic circuit diagram of a vibrator starting module of a two-phase dynamic synchronous clock generating circuit applied to a charge pump system according to the present invention. The vibrator starting module includes:
the fourth-stage CMOS inverter comprises a fourth PMOS tube P4 and a fourth NMOS tube N4, wherein the drain electrode of the fourth PMOS tube P4 and the drain electrode of the fourth NMOS tube N4 are both connected with the output end of the oscillator starting module, and the grid electrode of the fourth PMOS tube P4 and the grid electrode of the fourth NMOS tube N4 are both connected with the first input end of the oscillator starting module;
the fifth-stage CMOS inverter comprises a fifth PMOS tube P5 and a fifth NMOS tube N5, wherein the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the fourth PMOS tube P4, the drain electrode of the fifth NMOS tube N5 is connected with the source electrode of the fourth NMOS tube N4, the source electrode of the fifth NMOS tube N5 is grounded, and the grid electrode of the fifth PMOS tube P5 and the grid electrode of the fifth NMOS tube N5 are both connected with the second input end of the oscillator starting module;
the sixth-stage CMOS inverter comprises a sixth PMOS tube P6 and a sixth NMOS tube N6, wherein the source electrode of the sixth PMOS tube P6 is connected with the source electrode of the fifth PMOS tube P5, the source electrode of the sixth NMOS tube N6 is grounded, the drain electrode of the sixth PMOS tube P6 and the drain electrode of the sixth NMOS tube N6 are both connected with the output end of the oscillator starting module, and the grid electrode of the sixth PMOS tube P6 and the grid electrode of the sixth NMOS tube N6 are both connected with the first input end of the oscillator starting module;
a seventh PMOS enable tube P7 and a seventh NMOS enable tube N7, where a gate of the seventh PMOS enable tube P7 inputs an enable signal, a source of the seventh PMOS enable tube P7 inputs a power supply voltage, a drain of the seventh PMOS enable tube P7 is connected with a source of the fifth PMOS tube P5 and a source of the sixth PMOS tube P6, a gate of the seventh NMOS enable tube N7 inputs an enable signal, a source of the seventh NMOS enable tube N7 is grounded, and a drain of the seventh NMOS enable tube N7 is connected with an output end of the oscillator module.
In practical application, in the oscillator sub-module of the two-phase dynamic synchronous clock generating circuit (see fig. 5), when signals input by the first input end A1 and the second input end A2 of the oscillator sub-module are synchronous, the width-to-length ratio of the first PMOS transistor P1 and the second PMOS transistor P2 after being connected in series is the same as that of the third PMOS transistor P3, and the width-to-length ratio of the first NMOS transistor N1 and the second NMOS transistor N2 after being connected in series is the same as that of the third NMOS transistor N3, i.e. the corresponding driving is the same, so the circuit can be simplified into a CMOS inverter, the ring oscillator stably outputs clock signals, and the working speed can reach the fastest.
In practical application, in the oscillator starting module (refer to fig. 6) of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system, when signals input by the first input end A1 and the second input end A2 of the oscillator starting module are synchronous, the aspect ratio of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 after being connected in series is the same as that of the sixth PMOS transistor P6, and the aspect ratio of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 after being connected in series is the same as that of the sixth NMOS transistor N6, i.e. the corresponding driving is the same, so that the circuit can be simplified into a CMOS inverter, the ring oscillator stably outputs clock signals, and the working speed can reach the fastest.
When the input signals of the first input end A1 and the second input end A2 of the oscillator sub-module (or the oscillator starting module) are not synchronous, the driving of the inverter formed by the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2 is weaker than that of the inverter formed by the third PMOS tube P3 and the third NMOS tube N3. The inverter formed by the fourth PMOS transistor P4, the fifth PMOS transistor P5, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 is driven weaker than the inverter formed by the sixth PMOS transistor P6 and the sixth NMOS transistor N6. The drive is reduced, the inverter is turned over for a delay time, so that the phase of the output signal is delayed, and the working speed is reduced.
When the signals input by the first input end A1 and the second input end A2 of the oscillator sub-module (or the oscillator starting module) are not synchronous, please refer to fig. 7, which is a schematic circuit diagram of any stage of the oscillating unit of the two-way ring oscillator applied to the two-phase dynamic synchronous clock generating circuit of the charge pump system. The circuit structure is composed of the same-stage oscillator sub-modules of 2 ring oscillators, wherein the first input end of the oscillator sub-module of the first ring oscillator and the first input end of the oscillator sub-module of the second ring oscillator respectively input UP_n time and DOWN_n signals, the output end of the oscillator sub-module of the first ring oscillator and the output end of the oscillator sub-module of the second ring oscillator respectively output UP_n+1 time and DOWN_n+1 time signals, and meanwhile the UP_n+1 time and DOWN_n+1 time signals are respectively used as feedback signals of the oscillator sub-module of the second ring oscillator and the oscillator sub-module of the first ring oscillator, in practical application, it is assumed that the phase of UP_n is advanced by Deltat from the falling edge of DOWN_n, the falling edge of UP_n is inverted by T, the delay of the inverter is inverted by UP_n+1, and the phase of DOWN+1Deltat' (see FIG. 8). When DOWN_n is flipped high, DOWN_n+1 is flipped low after the inverter delay T if there is no effect of the feedback signal UP_n+1; however, under the action of the feedback signal UP_n+1, the UP_n+1 advances the DOWN_n+1Deltat 'to turn over, at this time, the N1 and N2 pipes are conducted and connected with the N3 pipe in parallel, the overall width-to-length ratio is increased, the load charging current is increased, the DOWN_n+1 is pushed to accelerate the turning over, and the advance time Deltat > Deltat'. Over N cycles Δt' will be pulled smaller and smaller, making up_n+1 and down_n+1 more and more synchronous, and the phase lag is the same.
The output ends of the odd-numbered stage oscillation modules of the first path of ring oscillator and the odd-numbered stage oscillation modules of the second path of ring oscillator of the two-phase dynamic synchronous clock generation circuit applied to the charge pump system are connected with capacitors (refer to fig. 4) for changing clock frequency. In practical applications, the clock frequency is also determined by the delay and the number of stages of the oscillating unit.
The capacitor of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system can be a MOS capacitor.
The two-phase dynamic synchronous clock generating circuit applied to the charge pump system realizes the effect of dynamic synchronization by mutual pushing and acceleration when the output clock signal generates the asynchronous change of the phase through the two-path interactive ring oscillator structure, can be suitable for occasions with higher requirements on frequency and phase synchronization, and has better application value.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. A two-phase dynamic synchronous clock generation circuit applied to a charge pump system, characterized in that the two-phase dynamic synchronous clock generation circuit comprises:
the first path of ring oscillator is formed by connecting oscillation modules end to end and is used for generating synchronous clock signals;
the second path of ring oscillator is formed by connecting end to end of the oscillation module and interacts with the first path of ring oscillator to generate synchronous clock signals;
the input ends of the at least two inverters are respectively connected with the output ends of the same-stage oscillation module of the two-phase dynamic synchronous clock generation circuit and are used for filtering the output signals of the two-phase dynamic synchronous clock generation circuit, and the output ends of the at least two inverters output the signals of the two-phase dynamic synchronous clock generation circuit through the output ports;
the output end of the oscillation module of the first path of ring oscillator is respectively connected with the input end of the oscillation module of the corresponding second path of ring oscillator, the output end of the oscillation module of the second path of ring oscillator is respectively connected with the input end of the oscillation module of the corresponding first path of ring oscillator, and the oscillation module of the first path of ring oscillator and the oscillation module of the second path of ring oscillator both comprise a vibrator starting module and an oscillation submodule;
the first path of ring oscillator comprises a first oscillator module, a first oscillator sub-module, a second oscillator sub-module, a third oscillator sub-module and a fourth oscillator sub-module, and the second path of ring oscillator comprises a second oscillator module, a fifth oscillator sub-module, a sixth oscillator sub-module, a seventh oscillator sub-module and an eighth oscillator sub-module;
the first input end of the first oscillator module inputs an enabling signal, the second input end of the first oscillator module inputs the output signal of the fourth oscillator sub-module, the third input end of the first oscillator module inputs the output signal of the fifth oscillator sub-module, the first input end of the first oscillator sub-module inputs the output signal of the first oscillator module, the second input end of the first oscillator sub-module inputs the output signal of the second oscillator module, the first input ends of the second oscillator sub-module to the fourth oscillator sub-module respectively input the output signals of the first oscillator sub-module to the third oscillator sub-module, the second input ends of the second oscillator sub-module to the fourth oscillator sub-module respectively input the output signals of the sixth oscillator sub-module to the eighth oscillator sub-module,
the first input end of the fifth oscillator sub-module inputs the output signal of the eighth oscillator sub-module, the second input end of the fifth oscillator sub-module inputs the output signal of the first oscillator sub-module, the first input end of the second oscillator sub-module inputs an enabling signal, the second input end of the second oscillator sub-module inputs the output signal of the fifth oscillator sub-module, the third input end of the second oscillator sub-module inputs the output signal of the first oscillator sub-module, the first input end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the second input end of the sixth oscillator sub-module inputs the output signal of the second oscillator sub-module, the first input ends of the seventh oscillator sub-module and the eighth oscillator sub-module respectively inputs the output signals of the sixth oscillator sub-module and the seventh oscillator sub-module, and the second input end of the eighth oscillator sub-module respectively inputs the output signals of the fourth oscillator sub-module and the fifth oscillator sub-module.
2. The circuit of claim 1, wherein the output terminal of the second oscillator sub-module is connected to a third inverter, the third inverter is connected to a third output terminal, the output terminal of the fourth oscillator sub-module is connected to a first inverter, the first inverter is connected to the first output terminal, the output terminal of the sixth oscillator sub-module is connected to a fourth inverter, the fourth inverter is connected to a fourth output terminal, the output terminal of the eighth oscillator sub-module is connected to a second inverter, and the second inverter is connected to the second output terminal.
3. The two-phase dynamic synchronous clock generation circuit for a charge pump system according to claim 1, wherein the oscillation submodule comprises:
the first-stage CMOS inverter comprises a first PMOS tube (P1) and a first NMOS tube (N1), wherein the source electrode of the first PMOS tube (P1) inputs power supply voltage, the source electrode of the first NMOS tube (N1) is grounded, and the grid electrode of the first PMOS tube (P1) and the grid electrode of the first NMOS tube (N1) are connected with the second input end of the oscillator module;
the second-stage CMOS inverter comprises a second PMOS tube (P2) and a second NMOS tube (N2), wherein the source electrode of the second PMOS tube (P2) is connected with the drain electrode of the first PMOS tube (P1), the drain electrode of the second PMOS tube (P2) is connected with the drain electrode of the second NMOS tube (N2), the source electrode of the second NMOS tube (N2) is connected with the drain electrode of the first NMOS tube (N1), the drain electrode of the second PMOS tube (P2) and the drain electrode of the second NMOS tube (N2) are both connected with the output end of the oscillation submodule, and the grid electrode of the second PMOS tube (P2) and the grid electrode of the second NMOS tube (N2) are both connected with the first input end of the oscillation submodule;
the third-stage CMOS inverter comprises a third PMOS tube (P3) and a third NMOS tube (N3), wherein a source electrode of the third PMOS tube (P3) is input with a power supply voltage, a source electrode of the third NMOS tube (N3) is grounded, a drain electrode of the third PMOS tube (P3) and a drain electrode of the third NMOS tube (N3) are both connected with an output end of the oscillation submodule, and a grid electrode of the third PMOS tube (P3) and a grid electrode of the third NMOS tube (N3) are both connected with a first input end of the oscillation submodule.
4. The two-phase dynamic synchronous clock generation circuit for a charge pump system according to claim 1, wherein the oscillator module comprises:
the fourth-stage CMOS inverter comprises a fourth PMOS tube (P4) and a fourth NMOS tube (N4), wherein the drain electrode of the fourth PMOS tube (P4) and the drain electrode of the fourth NMOS tube (N4) are connected with the output end of the oscillator starting module, and the grid electrode of the fourth PMOS tube (P4) and the grid electrode of the fourth NMOS tube (N4) are connected with the first input end of the oscillator starting module;
the fifth-stage CMOS inverter comprises a fifth PMOS tube (P5) and a fifth NMOS tube (N5), wherein the drain electrode of the fifth PMOS tube (P5) is connected with the source electrode of the fourth PMOS tube (P4), the drain electrode of the fifth NMOS tube (N5) is connected with the source electrode of the fourth NMOS tube (N4), the source electrode of the fifth NMOS tube (N5) is grounded, and the grid electrode of the fifth PMOS tube (P5) and the grid electrode of the fifth NMOS tube (N5) are both connected with the second input end of the oscillator starting module;
the sixth-stage CMOS inverter comprises a sixth PMOS tube (P6) and a sixth NMOS tube (N6), wherein the source electrode of the sixth PMOS tube (P6) is connected with the source electrode of the fifth PMOS tube (P5), the source electrode of the sixth NMOS tube (N6) is grounded, the drain electrode of the sixth PMOS tube (P6) and the drain electrode of the sixth NMOS tube (N6) are both connected with the output end of the oscillator starting module, and the grid electrode of the sixth PMOS tube (P6) and the grid electrode of the sixth NMOS tube (N6) are both connected with the first input end of the oscillator starting module;
a seventh PMOS enabling tube (P7) and a seventh NMOS enabling tube (N7), wherein an enabling signal is input to the gate of the seventh PMOS enabling tube (P7), a power supply voltage is input to the source of the seventh PMOS enabling tube (P7), the drain of the seventh PMOS enabling tube (P7) is connected with the source of the fifth PMOS tube (P5) and the source of the sixth PMOS tube (P6), an enabling signal is input to the gate of the seventh NMOS enabling tube (N7), the source of the seventh NMOS enabling tube (N7) is grounded, and the drain of the seventh NMOS enabling tube (N7) is connected with the output end of the oscillator module.
5. The circuit of claim 1, wherein the output terminals of the oscillating module of the first ring oscillator and the oscillating module of the second ring oscillator are connected to capacitors for changing clock frequency.
6. The circuit of claim 5, wherein the capacitor is a MOS capacitor.
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| CN105141295A (en) * | 2015-07-30 | 2015-12-09 | 灿芯半导体(上海)有限公司 | Self-calibration circuit of built-in clock |
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