CN109755290A - Nanowire transistor and method of making the same - Google Patents

Abstract

The invention discloses a kind of nano-wire transistors and preparation method thereof, comprising: the sacrificial layer and nano wire being stacked with are formed in substrate；Pseudo- grid are formed, pseudo- grid are located above the sacrificial layer and nano wire stacked；The sacrificial layer and nano wire between adjacent pseudo- grid are removed, to form source/drain region；Isolation structure is formed, isolation structure is located at the substrate surface of source/drain region bottom, source/drain region and substrate is isolated；With form source/drain in source/drain region, source/drain is located above isolation structure, and contacts with the side of adjacent nano wire.Source/drain and substrate is isolated in isolation structure, avoids between the two that there is a phenomenon where leakage of current.Meanwhile there are internal side wall between gate structure and source/drain, solve the problems, such as that parasitic capacitance is excessive between source/drain and gate structure.

Description

Nanowire transistor and method of making the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a nanowire transistor and a preparation method thereof.

Background technique

For a long time, reducing the size of transistors and improving the integration of integrated circuits has been the eternal pursuit of the semiconductor industry. From FinFETs (fin transistors) to NWFETs (nanowire transistors), the physical size of the gate continues to decrease. In NWFETs, the gate thickness and the width of the source/drain regions are relatively small, which effectively enhances the control function of the gate. However, the reduction of its own size is prone to generate parasitic capacitance, which affects the performance of the transistor. At present, in order to solve this problem, researchers have proposed a technical scheme of forming sidewalls at the bottom of the gate to cut off the path of parasitic transistor current and improve the DC characteristics of NWFETs.

However, currently in the prior art, the source/drain of the NWFET nanowire transistor is in direct contact with the substrate, and there is no effective isolation between the two. When the nanowire transistor works, the leakage phenomenon is likely to occur where the source/drain of the nanowire transistor is in contact with the substrate.

Therefore, there is an urgent need in the prior art for a method that can achieve electrical isolation between the substrate and the source/drain of the nanowire transistor and reduce leakage.

SUMMARY OF THE INVENTION

The invention provides a nanowire transistor and a preparation method thereof, which realizes the electrical isolation between the source/drain and the substrate, and reduces the excessive capacitance between the bottom gate and the source/drain of the nanowire transistor.

The present invention provides a nanowire transistor, comprising: a gate structure disposed on a substrate; source/drain, the source/drain are located on both sides of the gate structure; nanowire, the nanowire is disposed inside the gate structure , both sides of the nanowire are in contact with the source/drain; and an isolation structure formed between the substrate and the source/drain to isolate the substrate and the source/drain.

According to an aspect of the present invention, the number of nanowires is one or more, and when there are multiple nanowires, the multiple nanowires are longitudinally spaced and distributed inside the gate structure.

According to one aspect of the present invention, the isolation structure covers the substrate under the source/drain so that the source/drain is not in contact with the substrate.

According to one aspect of the invention, the highest points of both sides of the isolation structure are lower than the top surface of the bottommost nanowire.

According to one aspect of the present invention, the highest points of both sides of the isolation structure are not higher than the bottom surface of the bottommost nanowire.

According to one aspect of the present invention, the isolation structure includes: a sidewall isolation structure and a bottom isolation structure, wherein the sidewall isolation structure is located on both sides of the isolation structure, and the bottom isolation structure is located between the sidewall isolation structures and is separated from the sidewall isolation structure contact.

According to an aspect of the present invention, the two side surfaces of the isolation structure are respectively the two side surfaces of the sidewall isolation structure that are not in contact with the bottom isolation structure.

According to one aspect of the present invention, the sidewall isolation structure is a sidewall spacer, and the bottom isolation structure is a bottom sidewall or a bottom barrier.

According to one aspect of the present invention, the bottom barrier layer includes a diffusion barrier layer and/or a conduction barrier layer.

According to one aspect of the present invention, it further includes: when the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom sidewall, the sidewall isolation structure and the bottom isolation structure are made of the same material, which is SiO ₂ , SiN, SiON , one or more of SiOCN.

According to one aspect of the present invention, when the sidewall isolation structure is a sidewall spacer, and the bottom isolation structure is a bottom barrier layer, the material of the sidewall isolation structure is one or more of SiO ₂ , SiN, SiON, and SiOCN , the material of the bottom isolation structure is one or more of Si, SiGe, Ge, GaAs, SiC, and SiGeC.

According to an aspect of the present invention, further comprising: inner spacers located between the source/drain and the gate structure in contact with the bottom surface of the nanowire.

According to one aspect of the present invention, the gate structure includes: a gate electrode and a gate dielectric layer covering a surface of the gate electrode.

According to an aspect of the present invention, further comprising: a protective structure covering the top surface of the topmost nanowire.

According to an aspect of the present invention, it further includes: a first spacer, the first spacer covering both side walls of the gate structure above the protection structure; a first dielectric layer, the first dielectric layer covering the source/drain; Two dielectric layers, the second dielectric layer covers the gate structure, the first dielectric layer and the surface of the first sidewall spacer; and a metal line, the metal line penetrates the second dielectric layer and is in contact with the gate structure.

The invention also discloses a method for preparing a nanowire transistor, which includes: forming a sacrificial layer and nanowires stacked on a substrate; forming a dummy gate, where the dummy gate is located above the stacked sacrificial layer and the nanowire; removing adjacent dummy gates between the sacrificial layer and the nanowires to form the source/drain regions; forming isolation structures located on the substrate surface at the bottom of the source/drain regions to isolate the source/drain regions and the substrate; and within the source/drain regions A source/drain is formed over the isolation structure and in contact with the sides of adjacent nanowires.

According to one aspect of the present invention, the bottommost sacrificial layer is in contact with the substrate surface, and the bottommost nanowire is not in contact with the substrate.

According to one aspect of the present invention, the number of stacked nanowires is one or more.

According to one aspect of the present invention, an isolation structure covers the substrate below the source/drain regions.

According to one aspect of the present invention, forming the isolation structure includes: forming a sidewall isolation structure and a bottom isolation structure, the sidewall isolation structure is located on both sides of the bottom isolation structure, the formed bottom isolation structure is located between the sidewall isolation structures, and is connected with the sidewall isolation structure. The sidewall isolation structures are in contact.

According to one aspect of the present invention, the step of forming the sidewall isolation structure and the bottom isolation structure includes: forming second sidewall spacers covering dummy gate sides, nanowire sides, sacrificial layer sides on both sides of the source/drain region, and The bottom substrate surface of the source/drain region; a dielectric layer covering the second sidewall surface at the bottom of the source/drain region is formed, and the top surface of the dielectric layer is lower than the top surface of the bottommost nanowire and higher than the bottommost sacrificial layer. and removing part of the second spacers on both sides of the source/drain region, so that the top surfaces of the remaining second spacers on both sides of the source/drain region are flush with the top surface of the dielectric layer to form the sidewall spacers and bottom sidewalls, wherein the remaining second sidewalls on both sides of the source/drain region are sidewall sidewalls, and the sidewall sidewalls are sidewall isolation structures, the second sidewalls located at the bottom of the dielectric layer are bottom sidewalls, and The bottom side wall is the bottom isolation structure.

According to one aspect of the invention, the highest points of both sides of the isolation structure are lower than the top surface of the bottommost nanowire.

According to one aspect of the present invention, the highest points of both sides of the isolation structure are not higher than the bottom surface of the bottommost nanowire.

According to an aspect of the present invention, the two side surfaces of the isolation structure are respectively the side surfaces of the sidewall isolation structure that are not in contact with the bottom isolation structure.

According to one aspect of the present invention, the sidewall isolation structure is a sidewall spacer, and the bottom isolation structure is a bottom sidewall or a bottom barrier.

According to one aspect of the present invention, when the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom spacer, the sidewall isolation structure and the bottom isolation structure are made of the same material, which is one of SiO ₂ , SiN, SiC, and SiOCN. one or more of.

According to one aspect of the present invention, when the sidewall isolation structure is a sidewall spacer, and the bottom isolation structure is a bottom barrier layer, the material of the sidewall isolation structure is one or more of SiO ₂ , SiN, SiON, and SiOCN , the material of the bottom isolation structure is one or more of Si, SiGe, Ge, GaAs, SiC, and SiGeC.

According to one aspect of the present invention, the steps of forming the sidewall isolation structure and the bottom isolation structure further include: removing the dielectric layer; removing the bottom spacer to expose the substrate; and forming a bottom barrier layer on the surface of the substrate between the sidewall spacers , the bottom barrier layer is a bottom isolation structure.

According to one aspect of the present invention, the bottom barrier layer includes a diffusion barrier layer and/or a conduction barrier layer.

According to one aspect of the present invention, the type of ions doped in the diffusion barrier layer is opposite to that of the source/drain electrode, and the ions doped in the diffusion barrier layer are one or more of boron (B) and gallium (Ga).

According to one aspect of the present invention, the conduction barrier layer is doped with the same ion type as the source/drain, and is doped with: one or more of boron (B), gallium (Ga), or arsenic (As), One or more of Rhodium (Rh).

According to an aspect of the present invention, further comprising: before forming the second spacer, removing part of the sacrificial layer to form openings on both sides of each sacrificial layer; and when forming the second spacer, filling each opening to form an interior side wall.

According to an aspect of the present invention, the depth of the openings ranges from 2 nm to 20 nm.

According to one aspect of the present invention, after forming the source/drain, it further includes: forming a first dielectric layer covering the source/drain; removing the dummy gate and the sacrificial layer to form a trench; and forming a gate in the trench polar structure.

According to one aspect of the present invention, after the gate structure is formed, the method further includes: forming a second dielectric layer covering the gate structure and the first dielectric layer; and forming a metal wire penetrating the second dielectric layer, the metal wire being connected to the second dielectric layer. The gate structure contacts.

According to an aspect of the present invention, before forming the dummy gate, the method further includes: forming a protection structure, and the protection structure covers the top surface of the stacked sacrificial layer and the nanowire.

According to an aspect of the present invention, after the dummy gate is formed and before the isolation structure is formed, the method further includes: forming a first spacer covering both sidewalls of the dummy gate.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

Since the nanowire transistor of the embodiment of the present invention has an isolation structure, the isolation structure is located between the substrate and the source/drain to isolate the substrate and the source/drain. The purpose of the isolation structure is to isolate the source/drain and the substrate and eliminate the leakage of current between the source/drain and the substrate.

Further, the highest points on both sides of the isolation structure are lower than the bottom surface of the bottommost nanowire. Such a positional distribution can effectively prevent the top surface of the bottom barrier layer from being too high to increase the parasitic resistance inside the nanowire transistor, thereby better improving the performance of the nanowire transistor.

Further, the nanowire transistor also includes internal spacers between the source/drain and the gate structure in contact with the bottom surface of the nanowire. It can play the role of isolating source/drain and gate structure.

In the embodiments of the present invention, an isolation structure is formed when the nanowire transistor is formed, and the isolation structure is located on the surface of the substrate where the isolation structure is located at the bottom of the source/drain region, so as to isolate the source/drain region and the substrate. The purpose of forming the isolation structure is to subsequently isolate the source/drain and the substrate to eliminate the leakage of current between the source/drain and the substrate.

Further, a dielectric layer is formed covering the surface of the second spacer at the bottom of the source/drain region, and the top surface of the dielectric layer is lower than the top surface of the bottommost nanowire and higher than the bottom surface of the sacrificial layer in contact with the substrate. The purpose of forming the dielectric layer is to provide an etching stop position for the subsequent etching to remove part of the second spacer, so that the top surface of the sidewall spacer is also located at the same position.

Further, the highest point of the non-contact side surface of the sidewall isolation structure and the bottom isolation structure is not higher than the top surface of the sacrificial layer in contact with the substrate. The purpose of limiting the height of the top surface of the sidewall isolation structure is to prevent the surface from being too high, and to promote the conduction between the source/drain and the channel, thereby achieving a better effect.

Further, before forming the second spacer, part of the sacrificial layer is removed to form openings on both sides of each sacrificial layer; when forming the second spacer, all the openings are filled to form internal spacers. The purpose of this is to form internal spacers between the subsequently formed gate structure and the source/drain, increase the distance between the source/drain and the gate structure, and effectively solve the problem between the gate and the source/drain of the nanowire transistor. The problem of excessive capacitance between drains.

Description of drawings

1-9 are schematic cross-sectional structural diagrams of a nanowire transistor formation process according to an embodiment of the present invention;

10-15 are schematic cross-sectional structural diagrams of a nanowire transistor formation process according to yet another embodiment of the present invention;

16-25 are schematic cross-sectional structural diagrams of a nanowire transistor formation process according to still another embodiment of the present invention.

Detailed ways

As mentioned above, there is a phenomenon of current leakage between the existing nanowire transistor substrate and the source/drain.

Through research, it is found that the reason for the above problem is that there is no effective isolation between the substrate and the source/drain of the nanowire transistor. Therefore, a solution of forming an isolation structure between the substrate and the source/drain is proposed to solve the above problems.

After further research, it is also found that the distance between the gate and the source/drain of the nanowire transistor is relatively short, there is no effective isolation structure, and the parasitic capacitance is too large. Therefore, it is proposed to form internal spacers between the bottom of the gate and the source/drain to solve the above problems.

In order to solve this problem, the present invention provides a nanowire transistor and a preparation method thereof, which form an effective isolation structure between the substrate and the source/drain, so as to avoid the source/drain caused by direct contact between the substrate and the source/drain. Leakage of pole bottom current. At the same time, an internal spacer is formed between the gate and the source/drain of the nanowire transistor to electrically isolate the gate and the source/drain, which solves the problem of excessive capacitance between the bottom of the gate and the source/drain of the nanowire transistor. The problem.

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the invention unless specifically stated otherwise.

In addition, it should be understood that, for ease of description, the dimensions of various components shown in the drawings are not necessarily drawn to an actual scale relationship, for example, the thickness or width of some layers may be exaggerated relative to other layers.

The following description of exemplary embodiments is illustrative only and is not intended to limit the invention, its application or use in any way.

Techniques, methods, and apparatuses known to those of ordinary skill in the relevant art may not be discussed in detail, but where applicable, these techniques, methods, and apparatuses should be considered part of this specification.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined or described in one figure, it will not need to be further explained in the description of subsequent figures discuss.

first embodiment.

Referring to FIG. 1 , a substrate 100 is formed on which a sacrificial layer 110 and nanowires 120 are stacked on each other, and a dummy gate 150 is formed above the sacrificial layer 110 and the nanowires 120 .

The substrate 100 is the basis for subsequent formation of gates, source/drain and other processes. The material of the substrate 100 includes Si, SiGe, etc., which are not specifically limited here.

The sacrificial layer 110 is the basis for the subsequent formation of the gate. Materials of the sacrificial layer 110 include: Si, SiGe, SiC, etc., which are not specifically limited here.

Nanowire 120 acts as a channel region for subsequent nanowire transistors. Materials of the nanowires 120 include: Si, SiGe, SiC, etc., which are not specifically limited here. Since the nanowire 120 is not in contact with the substrate 100, the material of the nanowire 120 and the material of the substrate 100 may be the same or different, which is not limited herein.

Obviously, since the sacrificial layer 110 and the nanowires 120 are stacked on each other, it should be satisfied that the materials of the sacrificial layer 110 and the nanowires 120 are different. Preferably, in the embodiment of the present invention, the material of the sacrificial layer 110 is SiGe, and the material of the nanowires 120 is Si.

The thicknesses of the sacrificial layer 110 and the nanowires 120 are both between 4 nm and 30 nm (here, the thickness is greater than or equal to 4 nm and less than or equal to 30 nm, that is, the range includes endpoint values, and the following range expressions have the same meaning as here). The thicknesses of the sacrificial layer 110 and the nanowires 120 may be the same or different, which are not specifically limited here. In one embodiment of the present invention, the thickness of the sacrificial layer 110 is 4 nm, and the thickness of the nanowires 120 is 30 nm. In another embodiment of the present invention, the thickness of the sacrificial layer 110 is 15 nm, and the thickness of the nanowires 120 is 20 nm.

The number of layers of the sacrificial layer 110 and the nanowires 120 is not particularly limited, and may be one layer or multiple layers. However, the bottommost sacrificial layer 110 should be in contact with the surface of the substrate 100 , and the bottommost nanowire 120 should not be in contact with the substrate 100 .

Specifically, in the embodiment of the present invention, the layers of the sacrificial layer 110 and the nanowires 120 are respectively two layers, that is, the first sacrificial layer 110a covering the surface of the substrate 100 is formed, and the second sacrificial layer 110a covering the surface of the first sacrificial layer 110a is formed. For a nanowire 120a, a second sacrificial layer 110b covering the surface of the first nanowire 120a is formed, and then a second nanowire 120b covering the surface of the second sacrificial layer 110b is formed. Both the first nanowire 120 a and the second nanowire 120 b belong to the nanowire 120 . Similarly, the first sacrificial layer 110 a and the second sacrificial layer 110 b both belong to the sacrificial layer 110 .

In the embodiment of the present invention, a dummy gate 150 is further formed on the surface of the topmost nanowire 120b. The dummy gate 150 is the basis for the subsequent formation of the gate. Specifically, in the embodiment of the present invention, the material of the dummy gate 150 includes polysilicon (Poly-Si) or the like.

Here, the purpose of using the dummy gate 150 instead of directly forming the gate electrode is to avoid damage to the gate electrode caused by the subsequent process and affect the performance of the nanowire transistor.

It should be noted that, in other embodiments of the present invention, the material of the dummy gate 150 may also be other materials, as long as the condition that the structure of the dummy gate 150 is not damaged in subsequent processes is satisfied.

In the embodiment of the present invention, before forming the dummy gate 150 , the method further includes: forming a protection structure 130 . The protection structure 130 covers the top surface of the topmost nanowire 120b and covers the sidewalls of the stacked sacrificial layer 110 and the nanowire 120 . Here, the function of the protection structure 130 is to avoid damage to the stacked sacrificial layer 110 and the nanowires 120 caused by subsequent processes. In other embodiments of the present invention, the protection structure 130 may serve as a gate dielectric layer of part of the MOS transistor.

Materials of the protection structure 130 include oxides, nitrides, and the like. Specifically, in the embodiment of the present invention, the material of the protection structure 130 is SiO ₂ .

In the embodiment of the present invention, after the dummy gate 150 is formed and before the isolation structure is formed, the method further includes: forming a first spacer 140 covering both side walls of the dummy gate 150 . The function of the first spacer 140 is to protect the dummy gate 150 from being damaged by subsequent processes. The material of the first spacer 140 is oxide, nitride, etc., which is not specifically limited here.

Referring to FIG. 2 , the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 are removed to expose the substrate 100 to form source/drain regions 160 .

Removing the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 facilitates subsequent formation of isolation structures in the source/drain regions 160 . The process of removing the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 includes a dry etching process and/or a wet etching process. Specifically, in the embodiment of the present invention, the process of removing the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 is a dry etching process. And the dry etching is a reactive ion etching (Reactive Ion Etch, RIE) process.

The source/drain regions 160 provide space for the subsequent formation of isolation structures and source/drain. Since the sacrificial layer 110 and the nanowires 120 are directly formed on the surface of the substrate, the substrate 100 is exposed after the sacrificial layer 110 and the nanowires 120 are removed.

Here, the method for exposing the substrate 100 includes: removing only the sacrificial layer 110 and the nanowires 120 to expose the surface of the substrate 100, that is, without etching the substrate 100; or after removing the sacrificial layer 110 and the nanowires 120 , and then proceed to appropriately etch the substrate 100 to expose the substrate 100 , that is, to form a groove on the substrate 100 . Here, the method of exposing the substrate 100 is not particularly limited. Preferably, in the embodiment of the present invention, the method for exposing the substrate 100 is as follows: after removing the sacrificial layer 110 and the nanowires 120, the substrate 100 is appropriately etched, and after removing part of the substrate 100, the substrate 100 is exposed. Bottom 100 , that is, grooves are formed on the substrate 100 . This method makes the subsequent isolation structure formed at the bottom of the source/drain 160 relatively thick, which more effectively eliminates the leakage of current between the substrate 100 and the source/drain.

The process of etching part of the substrate 100 and the process of etching to form the source/drain regions 160 may be the same or different. In the embodiment of the present invention, the process of etching part of the substrate 100 is the same as the process of etching the sacrificial layer 110 and the nanowires 120 .

In the embodiment of the present invention, the method further includes: before the sacrificial layer 110 and the nanowire 120 are removed by etching, the protective structure 130 is removed by etching. The process of etching and removing the protection structure 130 may be the same as or different from the process of etching the sacrificial layer 110 and the nanowires 120 . Specifically, in the embodiment of the present invention, the process of etching and removing the protective structure 130 is the same as the process of etching the sacrificial layer 110 and the nanowire 120 .

Referring to FIG. 3 , second spacers 170 are formed in the source/drain regions 160 .

In the embodiment of the present invention, the second spacers 170 cover the sidewalls of the dummy gate 150 , the sidewalls of the nanowires 120 , the sidewalls of the sacrificial layer 110 and the surface of the bottom substrate 100 of the source/drain region 160 on both sides of the source/drain region 160 .

The second sidewall 170 is the basis for the subsequent formation of the sidewall isolation structure and the bottom isolation structure. The material of the second spacer 170 is one or more of SiO ₂ , SiN, SiON, and SiOCN. The thickness of the second sidewall spacer 170 is between 2 nm and 20 nm.

The process of forming the second spacer 170 includes, but is not limited to, an atomic layer deposition process (ALD process), a chemical vapor deposition process (CVD process), and the like. Specifically, in the embodiment of the present invention, the process of forming the second sidewall spacer 170 is an ALD process. The structure of the second sidewall spacer 170 formed by the ALD process is more uniform.

Referring to FIG. 4 , a dielectric layer 180 covering the surface of the second spacer 170 at the bottom of the source/drain region 160 is formed.

The purpose of forming the dielectric layer 180 is to provide an etch termination position for the subsequent etching to remove part of the second spacer 170 , so that the top surface of the remaining spacer at the bottom of the source/drain region 160 is in a proper position.

In the embodiment of the present invention, the material of the dielectric layer 180 includes organic matter, polysilicon, and the like. If the material of the dielectric layer 180 is an organic substance, the process of forming the dielectric layer 180 includes a spin coating process; if the material of the dielectric layer 180 is polysilicon, the dielectric layer 180 is formed by directly growing polysilicon. Specifically, in the embodiment of the present invention, the material of the dielectric layer 180 is an organic substance, and the formation process of the dielectric layer 180 is a spin coating process. Compared with the direct growth of polycrystalline Si, the structure of the dielectric layer 180 formed by the spin coating process is more uniform.

Here, it should be noted that in other embodiments of the present invention, the material of the dielectric layer 180 may also be other materials, which are not specifically limited here, as long as the conditions for providing a termination position for etching the second sidewall spacer 170 can be met. That's it.

The top surface of the dielectric layer 180 is lower than the top surface of the bottommost nanowire 120 and higher than the bottom surface of the bottommost sacrificial layer 110 . Specifically, in the embodiment of the present invention, the top surface of the dielectric layer 180 is not higher than the bottom surface of the bottommost nanowire 120, that is, not higher than the bottom surface of the nanowire 120a; and is higher than the bottom surface of the bottommost sacrificial layer 110 , that is, higher than the bottom surface of the sacrificial layer 110a. Here, the position of the top surface of the limiting dielectric layer 180 is for the purpose of terminating the etching at this position when the second spacer 170 is subsequently etched. The etching is stopped at this position, and the top surfaces of the remaining second sidewall spacers 170 at the bottom of both sides of the source/drain region 160 are also higher than the top surfaces of the second sidewall spacers 170 at the bottom of the source/drain region 160, so that the two are at the bottom of the source/drain region 160. The cross-sectional shape of the bottom of the source/drain region 160 is shallow U-shaped, and the sidewall spacers of the shallow U-shaped structure can more effectively isolate the subsequent source/drain from the substrate 100 .

It should be noted that, in the actual process, it is difficult to make the top surface of the dielectric layer 180 be located at the aforementioned position. Therefore, a thicker dielectric layer 180 can be formed first, and then the dielectric layer 180 can be etched, and the etching termination position can be controlled so that the top surface of the dielectric layer 180 after etching is located at the aforementioned position. Specifically, in the embodiment of the present invention, a thicker dielectric layer 180 is formed first, and then the dielectric layer 180 is etched back so that the top surface of the dielectric layer 180 is at the above position.

Referring to FIG. 5 , part of the second spacers 170 on both sides of the source/drain region 160 is removed to form an isolation structure.

The purpose of removing part of the second sidewall spacers 170 is to leave only the second sidewall spacers 170 at the bottom of the source/drain regions 160 to form an isolation structure.

The process of removing part of the second spacer 170 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of etching and removing part of the second sidewall spacer 170 is wet etching. The solution used in wet etching includes: one or a mixture of H ₃ PO ₄ , H ₂ O ₂ , SC1, deionized water, HCl, HF, and NH ₄ F.

In the embodiment of the present invention, when removing part of the second spacers 170 , all the side surfaces of the nanowires 120 are to be exposed. That is, in the embodiment of the present invention, all the side surfaces of the nanowires 120a and the nanowires 120b are exposed. In this way, the nanowire 120 is in contact with the source/drain formed subsequently, so as to achieve the purpose of conduction.

As mentioned above, the dielectric layer 180 provides an etching stop position for etching a portion of the second spacer 170 . Therefore, specifically, in the embodiment of the present invention, the remaining second sidewalls at the bottoms of the source/drain regions 160 are sidewall sidewalls 171 , and the top surfaces of the sidewall sidewalls 171 are flush with the top surface of the dielectric layer 180 . . That is, the top surface of the sidewall spacer 171 is not higher than the bottom surface of the bottommost nanowire 120a, and is higher than the bottom surface of the bottommost sacrificial layer 110a.

It should be noted that, due to the actual etching process, it is difficult to ensure that the top surface of the sidewall spacer 171 is strictly flush with the top surface of the dielectric layer 180 . Therefore, specifically, when implementing the nanowire transistor of an embodiment of the present invention, it is necessary to ensure that the highest points on both sides of the isolation structure are lower than the top surface of the bottommost nanowire 120 , that is, the top surface of the nanowire 120a. Specifically, in the embodiment of the present invention, the highest points on both sides of the isolation structure are not higher than the bottom surface of the bottommost nanowire 120 , that is, the bottom surface of the nanowire 120a. The two side surfaces of the isolation structure are respectively the side surfaces of the sidewall isolation structure that are not in contact with the bottom isolation structure.

So far, in the embodiment of the present invention, the remaining part of the second sidewall 170 includes: a sidewall sidewall 171 and a bottom sidewall 172 , and the bottom sidewall 172 is located between the sidewall sidewalls 171 and is connected to the sidewall sidewall 171 . 171 connected. Obviously, the materials of the second sidewall 170 , the sidewall sidewall 171 and the bottom sidewall 172 are the same, as described above.

So far, an isolation structure is formed at the bottom of the source/drain region 160, and the isolation structure includes a sidewall isolation structure and a bottom isolation structure. Obviously, the bottom isolation structure covers the surface of the substrate 100 between the sidewall isolation structures and is connected to the sidewall isolation structures. In the embodiment of the present invention, the sidewall isolation structure is the sidewall spacer 171 , and the bottom isolation structure is the bottom sidewall 172 .

In the embodiment of the present invention, the sidewall spacers 171 and the bottom spacers 172 are located between the subsequent source/drain and the substrate 100, which realizes the isolation of the substrate 100 and the source/drain and prevents the source/drain The current leakage from the substrate 100 improves the performance of the nanowire transistor.

Referring to FIG. 6 , a source/drain 1310 is formed in the source/drain region 160 .

The source/drain 1310 is used to make contact with the nanowire 120 (channel region). Therefore, in the embodiment of the present invention, preferably, the top surface of the source/drain 1310 is higher than the top surface of the topmost nanowire 120b, that is, the source/drain 1310 completely covers both sides of the nanowire 120, and The source/drain 1310 simultaneously covers the surface of the isolation structure.

The process steps of forming the source/drain 1310 include: firstly forming a source/drain material layer (not shown) covering the surface of the isolation structure, and then doping the source/drain material layer to form the source/drain 1310 . In an embodiment of the present invention, the process of forming the source/drain material layer includes an epitaxial growth process. The epitaxial growth process includes: chemical vapor deposition (CVD) epitaxy process or molecular beam epitaxy (MBE) process. Specifically, in the embodiment of the present invention, the process of forming the source/drain material layer is the MBE process.

The material of the source/drain material layer may be selected according to different types of the source/drain 1310 . When the source/drain 1310 is a PMOS, the material of the source/drain material layer includes but is not limited to SiGe, Si, etc., and the doped substances include but not limited to boron (B), gallium (Ga), etc.; when the source/drain material layer is When 1310 is NMOS, the material of the source/drain material layer includes but not limited to SiC, Si, etc., and the doped substances include but not limited to phosphorus (P), arsenic (As), rhodium (Rh) and the like.

The process of doping the source/drain material layer includes in-situ doping, diffusion, ion implantation or a combination thereof. Specifically, in the embodiment of the present invention, the process of doping the source/drain material layer is in-situ epitaxial doping.

In the embodiment of the present invention, the source/drain 1310 is a highly doped source/drain 1310 . High doping means that the ion concentration of the doping is greater than 1×10 ²⁰ atoms/cm ³ .

It should be noted that, since the dielectric layer 180 is previously formed, in the embodiment of the present invention, after removing part of the spacer 170 and before forming the source/drain electrode 1310 , the method further includes: removing the dielectric layer 180 .

The removal of the dielectric layer 180 is to form the source/drain 1310 directly on the surface of the isolation structure subsequently. The process of removing the dielectric layer 180 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of removing the dielectric layer 180 is dry etching.

Referring to FIG. 7 , a first dielectric layer 1320 is formed on top of the source/drain 1310 .

In the embodiment of the present invention, after forming the source/drain 1310 , the method further includes: forming a first dielectric layer 1320 covering the source/drain 1310 .

The first dielectric layer 1320 plays a role of dielectric isolation in the nanowire transistor, and also protects the source/drain 1310 from damage in subsequent processes.

In the embodiment of the present invention, the material of the first dielectric layer 1320 includes, but is not limited to, SiO _x , SiOCH, SiN, and the like.

In the specific process implementation, since it is difficult to form the first dielectric layer 1320 only on the surface of the source/drain electrode 1310 , the first dielectric layer 1320 is also formed on the top of the dummy gate 150 . Since the dummy gate 150 is to be removed later, the top of the dummy gate 150 should be exposed after the first dielectric layer 1320 is formed. Specifically, in the embodiment of the present invention, the method for exposing the top of the dummy gate 150 is to form the first dielectric layer 1320 covering the dummy gate 150 and the source/drain 1310 first, and then remove part of the first dielectric layer 1320 to expose The top of the dummy gate 150 is removed.

The process of removing part of the first dielectric layer 1320 includes dry etching and/or wet etching, chemical mechanical planarization (CMP), and the like. Specifically, in the embodiment of the present invention, the first dielectric layer 1320 is planarized by a CMP process, thereby exposing the top of the dummy gate 150 .

Referring to FIG. 8 , the dummy gate 150 and the sacrificial layer 110 are removed to form a trench (not shown), and a gate structure is formed in the trench.

The purpose of removing the dummy gate 150 and the sacrificial layer 110 is to form a gate structure in the trench. The process of removing the dummy gate 150 and the sacrificial layer 110 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of removing the dummy gate 150 and the sacrificial layer 110 includes dry etching.

In the embodiment of the present invention, the gate structure includes: a gate dielectric layer 1330 and a gate 1340 .

The purpose of the gate dielectric layer 1330 is to isolate the source/drain 1310 , the nanowire 120 and the gate 1340 to avoid excessive parasitic capacitance between the source/drain 1310 and the gate 1340 .

In the embodiment of the present invention, the process steps of forming the gate dielectric layer 1330 and the gate electrode 1340 include: firstly forming an inner dielectric layer (not shown) covering the trench, and then forming a high dielectric material layer (not shown) on the surface of the inner dielectric layer marked, the dielectric constant k is between 15 and 50). The gate dielectric layer 1330 and the gate electrode 1340 fill the trenches. In the embodiment of the present invention, the gate 1340 covers the gate dielectric layer 1330 , and the gate dielectric layer 1330 covers the nanowires 120 .

Obviously, in the embodiment of the present invention, the gate dielectric layer 1330 includes: an inner dielectric layer and a high dielectric material layer.

The material of the inner dielectric layer includes but is not limited to: SiON, SiO _x , etc., which are not specifically limited here. Specifically, in the embodiment of the present invention, the material of the internal dielectric layer is SiO ₂ .

Materials of the high dielectric material layer include but are not limited to: HfO ₂ , ZrO ₂ and the like. Specifically, in the embodiment of the present invention, the material of the high dielectric material layer is HfO ₂ .

The gate 1340 is a metal gate. The material of the gate electrode 1340 includes, but is not limited to, one or more layered materials composed of TiN, TiAlC, TiAl, TaN, W, Ti, Al, and the like. Specifically, in the embodiment of the present invention, the material of the gate electrode 1340 is a stacked material composed of TiN and TiAl.

The processes for forming the gate dielectric layer 1330 and the gate electrode 1340 include: ALD process, CVD process, physical vapor deposition (PVD), chemical vapor deposition (CVD) epitaxy, molecular beam epitaxy (MBE) process, etc., which are not performed here. specific restrictions. Specifically, in the embodiment of the present invention, the formation process of the gate dielectric layer 1330 and the gate electrode 1340 is an ALD process.

In the embodiment of the present invention, before removing the sacrificial layer 110 , it further includes removing the protective structure 130 covering the top surface of the topmost nanowire 120 b and covering the sidewalls of the stacked sacrificial layer 110 and the nanowire 120 .

Referring to FIG. 9 , a metal line 1360 is formed on top of the gate 1340 to form a second dielectric layer 1350 covering the gate structure and the first dielectric layer 1320 .

The purpose of forming the second dielectric layer 1350 is to protect the gate electrode 1340 and the metal line 1360 .

The metal line 1360 is in contact with the gate structure, enabling communication with the gate 1340 . And the metal line 1360 penetrates the second dielectric layer 1350 . Since the metal line 1360 is to be in contact with the upper semiconductor device, the top surface of the metal line 1360 is to be exposed.

Obviously, the first dielectric layer 1320 and the second dielectric layer 1350 both play the role of dielectric protection. Therefore, the materials of the first dielectric layer 1320 and the second dielectric layer 1350 may be the same or different. Specifically, in the embodiment of the present invention, the materials of the first dielectric layer 1320 and the second dielectric layer 1350 are the same.

To sum up, according to the first embodiment of the present invention, a sidewall isolation structure and a bottom isolation structure are formed between the bottom of the source/drain 1310 and the substrate 100 . Compared with the prior art nanowire transistors without sidewall isolation structures and bottom isolation structures, this isolation structure effectively isolates the substrate 100 and the source/drain 1310, eliminating the need for the substrate 100 and the source/drain The leakage of current between 1310 improves the performance of the nanowire transistor.

Accordingly, please continue to refer to FIG. 9 , an embodiment of the present invention further provides a nanowire transistor including: a substrate 100 , a nanowire 120 , an isolation structure, a source/drain 1310 and a gate structure.

The substrate 100 is the basis for subsequent gate structures and isolation structures. The material of the substrate 100 includes Si, SiGe, etc., which are not specifically limited here.

The nanowires 120 serve as channel regions of the semiconductor device. Materials of the nanowires 120 include: Si, SiGe, SiC, etc., which are not specifically limited here. The nanowires 120 are not in contact with the substrate 100 . The number of nanowires 120 is one or more, which is not specifically limited here. When there are a plurality of nanowires 120, the plurality of nanowires 120 are longitudinally spaced and distributed inside the gate structure. In FIG. 9, the direction indicated by the arrow is the longitudinal direction. Specifically, in the embodiment of the present invention, the number of nanowires 120 is two, which are 120a and 120b in order from bottom to top.

The isolation structure is located on the surface of the substrate 100 for isolating the substrate 100 and the source/drain 1310 . The isolation structure includes a sidewall isolation structure and a bottom isolation structure, wherein the sidewall isolation structure is located on both sides of the bottom isolation structure, and the bottom isolation structure is located between and in contact with the sidewall isolation structure. Specifically, in the embodiment of the present invention, the sidewall isolation structure is the sidewall sidewall 171 , and the bottom isolation structure is the bottom sidewall 172 . The sidewall isolation structure is made of the same material as the bottom isolation structure, which is one or more of SiO ₂ , SiN, SiON, and SiOCN.

The two side surfaces of the isolation structure are respectively the two side surfaces of the sidewall isolation structure that are not in contact with the bottom isolation structure. The highest points on both sides of the isolation structure are lower than the top surface of the bottommost nanowire 120 . Specifically, in the embodiment of the present invention, the highest points on both sides of the isolation structure are lower than the bottom surface of the bottommost nanowire 120 , that is, lower than the bottom surface of the nanowire 120a.

The source/drain 1310 is located on both sides of the gate structure, and the source/drain 1310 is in contact with both sides of the nanowire 120 . In an embodiment of the present invention, the source/drain 1310 covers the isolation structure. When the source/drain 1310 is a PMOS, the material of the source/drain 1310 includes but not limited to SiGe, Si, etc., and the doped substances include but not limited to boron (B), gallium (Ga), etc.; when the source/drain 1310 is When 1310 is an NMOS, the source/drain material includes but is not limited to SiC, Si, etc., and the doped material includes but is not limited to phosphorus (P), arsenic (As), rhodium (Rh), and the like.

The gate structure is located over the substrate 100 and the gate structure is located between the source/drain 1310 . The gate structure includes a gate dielectric layer 1330 and a gate 1340 .

The purpose of the gate dielectric layer 1330 is to isolate the source/drain 1310 , the nanowire 120 and the gate 1340 to avoid excessive parasitic capacitance between the source/drain 1310 and the gate 1340 . In the embodiment of the present invention, the gate dielectric layer 1330 includes: an inner dielectric layer (not shown) and a high dielectric material layer (not shown).

Materials of the inner dielectric layer include: SiON, SiO _x , etc., which are not specifically limited here. Specifically, in the embodiment of the present invention, the material of the internal dielectric layer is SiO ₂ .

Materials of the high dielectric material layer include but are not limited to: HfO ₂ , ZrO ₂ and the like. Specifically, in the embodiment of the present invention, the material of the high dielectric material layer is HfO ₂ .

The gate 1340 is a metal gate. The material of the gate electrode 1340 includes, but is not limited to, one or more layered materials composed of TiN, TiAlC, TiAl, TaN, W, Ti, Al, and the like. Specifically, in the embodiment of the present invention, the material of the gate electrode 1340 is a stacked material composed of TiN and TiAl.

In an embodiment of the present invention, the nanowire transistor further includes: a first dielectric layer 1320 , a second dielectric layer 1350 and a metal wire 1360 .

The first dielectric layer 1320 covers the top of the source/drain 1310 . The first dielectric layer 1320 plays a role of dielectric isolation in the nanowire transistor, and also protects the source/drain 1310 from damage in subsequent processes. In the embodiment of the present invention, the material of the first dielectric layer 1320 includes, but is not limited to, SiO _x , SiOCH, SiN, and the like.

The second dielectric layer 1350 covers the gate structure and the first dielectric layer 1320 . The purpose of the second dielectric layer 1350 is to protect the gate 1340 and the metal lines 1360 .

Obviously, the first dielectric layer 1320 and the second dielectric layer 1350 both play the role of dielectric protection. Therefore, the materials of the first dielectric layer 1320 and the second dielectric layer 1350 may be the same or different. Specifically, in the embodiment of the present invention, the materials of the first dielectric layer 1320 and the second dielectric layer 1350 are the same.

The metal line 1360 is in contact with the gate structure, enabling communication with the gate 1340 . And the metal line 1360 penetrates the second dielectric layer 1350 . Since the metal line 1360 is to be in contact with the upper semiconductor device, the top surface of the metal line 1360 is to be exposed.

In the embodiment of the present invention, the nanowire transistor further includes: a protection structure 130 and a first spacer 140 .

The protection structure 130 covers the top surface of the topmost nanowire 120b and covers the sidewalls of the stacked sacrificial layer 110 and the nanowire 120 . Here, the function of the protection structure 130 is to avoid damage to the stacked sacrificial layer 110 and the nanowires 120 caused by subsequent processes. In other embodiments of the present invention, the protection structure 130 may serve as a gate dielectric layer of part of the MOS transistor. Materials of the protection structure 130 include oxides, nitrides, and the like. Specifically, in the embodiment of the present invention, the material of the protection structure 130 is SiO ₂ .

The first sidewall spacers 140 cover both sidewalls of the dummy gate 150 . The function of the first spacer 140 is to protect the dummy gate 150 from being damaged by subsequent processes. The material of the first spacer 140 is oxide, nitride, etc., which is not specifically limited here.

To sum up, in the nanowire transistor provided by the first embodiment of the present invention, the sidewall isolation structure and the bottom isolation structure are included between the source/drain and the substrate, which realizes the electrical connection between the source/drain and the substrate. Isolation, which eliminates the leakage of current between the two, improves the performance of the nanowire transistor.

Second Embodiment.

The difference between the second embodiment and the first embodiment is that the second embodiment uses a bottom barrier layer to replace the bottom spacer in the first embodiment, thereby realizing the isolation between the source/drain and the substrate.

Please refer to FIG. 10. FIG. 10 is a schematic cross-sectional structure diagram of further performing an etching process on the basis of etching and removing the dielectric layer (because in the second embodiment, the process steps before etching the dielectric layer are the same as those in the first embodiment, For details, reference may be made to the relevant description of the first embodiment, and details are not repeated here).

In the embodiment of the present invention, the method further includes: after removing the dielectric layer, removing the bottom spacer to expose the substrate 200 .

The purpose of removing the bottom spacers is to form a bottom isolation structure on the surface of the substrate 200 at the bottom of the source/drain regions 260 that can isolate the source/drain and the substrate. The process of removing the bottom spacer is a reactive ion etching (Reactive Ion Etch, RIE) process.

Referring to FIG. 11 , a bottom isolation structure is formed between the sidewall spacers 271 at the bottom of the source/drain regions 260 .

In the embodiment of the present invention, after removing the dielectric layer, the method further includes: removing the bottom spacers (not shown) at the bottom of the source/drain regions 260 ; and then forming a bottom barrier on the surface of the substrate 200 between the sidewall spacers 271 Layer 272.

The function of the bottom barrier layer 272 is to subsequently isolate the source/drain from the substrate 200 to reduce the leakage of current between the source/drain and the substrate 200 .

Both the bottom spacer (as described in the first embodiment) and the bottom barrier layer 272 can isolate the source/drain from the substrate 200 . In the embodiment of the present invention, the bottom barrier layer 272 is used as the bottom isolation structure, and the sidewall spacers 271 are used as the sidewall isolation structure, and the two together constitute the isolation structure. The positional relationship between the sidewall isolation structure and the bottom isolation structure, as well as the top surface or the highest points of both sides of the isolation structure are the same as those in the first embodiment, and will not be repeated here.

Here, the material of the sidewall spacer 271 is the same as that of the sidewall spacer in the first embodiment, as described above. The bottom barrier layer 272 is made of one or more of Si, SiGe, Ge, GaAs, SiC, and SiGeC.

The process of forming the bottom barrier layer 272 includes, but is not limited to, an atomic layer deposition process, a chemical vapor deposition process, a chemical vapor deposition epitaxy process, a molecular beam epitaxy process, and the like. Specifically, in the embodiment of the present invention, the process of forming the bottom isolation structure is a molecular beam epitaxy process. The bottom barrier layer 272 grown by the epitaxial process will make the subsequent process of forming the source/drain on the bottom isolation structure easier.

In the embodiment of the present invention, the type of the bottom isolation structure includes: a diffusion barrier layer or a conduction barrier layer; or a stacked structure of a diffusion barrier layer and a conduction barrier layer, which is not specifically limited here.

Here, it should be pointed out that the names of the diffusion barrier layer and the conduction barrier layer are consistent with their functions. The diffusion barrier layer can prevent the diffusion of particles between the source/drain and the substrate 200 ; the conduction barrier layer can prevent the conduction of the parasitic capacitance between the source/drain and the substrate 200 .

Specifically, in the embodiment of the present invention, when the bottom barrier layer 272 is a diffusion barrier layer, the bottom barrier layer 272 may be undoped or lightly doped. When the bottom barrier layer 272 is not doped, the bottom barrier layer 272 can isolate the source/drain from the substrate 200, cut off the leakage channel of current, and improve the performance of the nanowire transistor. When the bottom barrier layer 272 is shallowly doped, it is doped with the same type of ions as the subsequent source/drain doping. Preferably, when the bottom barrier layer 272 is a P-type semiconductor doped with boron (B) and gallium (Ga), the material of the bottom isolation structure is SiC, SiGeC, etc.; when the bottom barrier layer 272 is doped with phosphorus (P), arsenic (As), rhodium (Rh) N-type semiconductor, the material of the bottom barrier layer 272 is SiC or the like, which is not specifically limited here.

In the embodiment of the present invention, when the bottom barrier layer 272 is shallowly doped, the ion concentration of the doping is less than or equal to 1×10 ¹⁷ atoms/cm ³ . Bottom barrier layer 272 with moderate doping (ion concentration greater than 1×10 ¹⁷ atoms/cm ³ and less than 1×10 ²⁰ atoms/cm ³ ) or high doping (ion concentration greater than or equal to 1×10 ²⁰ atoms/cm ³ ) Compared with the lightly doped bottom barrier layer 272, the leakage of current can be reduced and the performance is better.

In the embodiment of the present invention, when the bottom barrier layer 272 is a conduction barrier layer, the bottom barrier layer 272 is moderately doped, and its doping type is opposite to the ion type of the source/drain doping formed subsequently. Preferably, when the bottom barrier layer 272 is a P-type semiconductor doped with boron (B) and gallium (Ga), the material of the bottom barrier layer 272 is Si, SiGe, SiGeC, etc.; when the bottom barrier layer 272 is doped with boron (B) and gallium (Ga) When the N-type semiconductor is doped with phosphorus (P), arsenic (As), and rhodium (Rh), the material of the bottom barrier layer 272 is Si, SiC, or the like. Also, the ion concentration of the intermediate doping of the bottom barrier layer 272 is between 1×10 ¹⁷ atoms/cm ³ to 1×10 ²⁰ atoms/cm ³ .

In the embodiment of the present invention, the doping gas source for the bottom barrier layer 272 includes but is not limited to: silicon sources SiH ₂ Cl ₂ , SiH ₄ , Si ₂ H ₆ ; germanium source GeH ₄ ; doping gas source: B ₂ H ₆ (boron), AsH ₃ (As), CH ₃ CH ₃ , CH ₃ SiH ₃ (carbon content 0.1% to 5%), PH ₃ (phosphorus), etc.

Here, it should be noted that the top surface of the bottom barrier layer 272 is not higher than the bottom surface of the bottommost nanowire 220a. If the top surface of the bottom barrier layer 272 is higher than the bottom surface of the bottommost nanowire 220a, the parasitic resistance between the subsequently formed source/drain and the substrate 200 increases, affecting the performance of the nanowire transistor.

As mentioned above, the bottom barrier layer 272 may also be a stacked structure of a diffusion barrier layer and a conduction barrier layer. At this time, the uppermost layer of the stacked structure in contact with the subsequent source/drain can be a diffusion barrier layer or a conduction barrier layer, which is not limited here. The selection of specific materials and the type of doping are the same as those described above. It is consistent and will not be repeated here.

Referring to FIG. 12 , a source/drain 2310 is formed in the source/drain region 260 .

The functions of forming the source/drain 2310, the process method, the steps, the concentration of doping, and the position of the top surface are the same as those in the first embodiment, and will not be repeated here.

It should be noted that, the material of the source/drain 2310 should be selected according to the material of the bottom isolation structure, as described above.

Referring to FIG. 13 , a first dielectric layer 2320 is formed on top of the source/drain 2310 .

The functions, processes, steps, and selection of materials for forming the first dielectric layer 2320 are the same as those in the first embodiment, and will not be repeated here.

Referring to FIG. 14 , the dummy gate 250 and the sacrificial layer 210 are removed to form a trench (not shown), and a gate dielectric layer 2330 and a gate electrode 2340 are formed in the trench.

The functions, processes, steps, material selection, and positional relationship between the structures of removing the dummy gate 250 and the sacrificial layer 210 and forming the gate dielectric layer 2330 and the gate electrode 2340 are the same as those in the first embodiment, and will not be repeated here.

Referring to FIG. 15 , metal lines 2360 are formed on the surface of the gate electrode 2340 to form a second dielectric layer 2350 covering the second sub-gate structure and the first dielectric layer 2320 .

The functions, processes, steps, and selection of materials for forming the second dielectric layer 2350 and the metal lines 2360 are the same as those in the first embodiment, and will not be repeated here.

To sum up, according to the second embodiment of the present invention, the isolation structure existing between the source/drain 2310 and the substrate 200 includes a sidewall isolation structure and a bottom isolation structure. The isolation of the two reduces the leakage of current between the source/drain 2310 and the substrate 200, and improves the performance of the nanowire transistor.

Correspondingly, please continue to refer to FIG. 15. An embodiment of the present invention further provides a nanowire transistor. The nanowire transistor provided by the second embodiment of the present invention is different from the nanowire transistor of the first embodiment in that: the first The bottom sidewall of the embodiment is replaced by the bottom barrier of the second embodiment, and the top surface of the bottom barrier is not the same height as the top surface of the bottom sidewall. The positional relationship of other structures is the same as that of the nanowire transistor of the first embodiment, and will not be repeated here.

The function of the bottom barrier layer 272 is to subsequently isolate the source/drain from the substrate 200 to reduce the leakage of current between the source/drain and the substrate 200 . In the embodiment of the present invention, the bottom barrier layer 272 is a bottom isolation structure, and the types of the bottom isolation structure include: a diffusion barrier layer or a conduction barrier layer; or a stacked structure of a diffusion barrier layer and a conduction barrier layer, here No specific restrictions are made.

In an embodiment of the present invention, the top surface of the bottom barrier layer 272 is not higher than the bottom surface of the bottommost nanowire 220a.

To sum up, in the nanowire transistor provided by the second embodiment, the sidewall isolation structure and the bottom isolation structure effectively isolate the substrate 200 from the source/drain 2310, reduce leakage, and improve the performance of the nanowire transistor .

Third Embodiment.

Compared with the second embodiment, the difference of the third embodiment is that openings are formed on both sides of each sacrificial layer of the stack, and the second spacers are filled in the openings to form internal spacers to realize the source/drain connection. Isolation of pole and gate.

Please refer to FIG. 16. FIG. 16 is a schematic cross-sectional structure diagram of a process of etching each sacrificial layer of the stack to form openings on the basis of forming the source/drain regions 360 (due to the previous process steps of the third embodiment and the first The embodiments are the same, and for details, reference may be made to the relevant description of the first embodiment, and details are not repeated here).

In the embodiment of the present invention, after forming the source/drain regions 360 and before forming the second spacers, the method further includes: removing part of the sacrificial layer 310 to form openings 361 on both sides of each sacrificial layer.

The purpose of forming the opening 361 is to subsequently fill the second sidewall in the opening 361 .

In this embodiment of the present invention, the depth of the opening 361 is between 2 nm and 20 nm, which is not specifically limited here. In one embodiment of the present invention, the depth of the opening 361 is 2 nm. In another embodiment of the present invention, the depth of the opening 361 is 20 nm.

The process of forming the opening 361 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of forming the opening 361 includes wet etching, and is a lateral wet etching process. The lateral direction here refers to the direction indicated by the arrow in FIG. 16 .

The solution for lateral wet etching includes: one or more mixtures of NH ₄ OH, NaOH, KOH, H ₂ O ₂ , CH ₃ COOH, deionized water, HCl, HF, and NH ₄ F.

Referring to FIG. 17 , a second sidewall 370 is formed, and the second sidewall 370 fills the interior of the opening 361 .

In the embodiment of the present invention, the second sidewall spacers 370 are formed to cover the sidewalls of the dummy gate 350 , the sidewalls of the nanowires 320 , the sidewalls of the sacrificial layer 310 and the bottom substrate 300 of the source/drain region 360 on both sides of the source/drain region 360 . surface, and at the same time ensure that the second sidewall 370 is filled into all the openings 361 .

The purpose of filling the second spacers 370 into all the openings 361 is to form internal spacers in the openings 361 to achieve subsequent isolation of the source/drain and the gate.

In the embodiment of the present invention, the thickness of the second spacer 370 is between 2 nm and 20 nm, as described in the first embodiment. The thickness of the second sidewall 370 may be the same as the depth of the opening 361 , or may be different from the depth of the opening 361 . However, the condition that the opening 361 is filled into the second sidewall 370 should be satisfied. Preferably, in the embodiment of the present invention, the thickness of the second sidewall 370 is slightly larger than the depth of the opening 361 .

Here, the function of forming the second sidewall 370 , the process method, and the selection of materials are the same as those in the second embodiment, and are not repeated here.

Referring to FIG. 18 , a dielectric layer 380 covering the surface of the second spacer 370 at the bottom of the source/drain region 360 is formed.

The function, process, and material selection for forming the dielectric layer 380 are all the same as those in the first embodiment, and will not be repeated here.

Referring to FIG. 19, a part of the second sidewall spacer 370 is removed to form an isolation structure.

The functions, processes, and steps of the second sidewalls 370 are the same as those of the first embodiment, and are not repeated here.

For the positional relationship of the isolation structure and the height of its top surface, please refer to the first embodiment.

In the embodiment of the present invention, when part of the second sidewall 370 is removed, the inner sidewall 373 should be retained. The function of the internal spacers 373 is to increase the distance between the subsequent gate and the source/drain, and reduce the excessive parasitic capacitance between the gate and the source/drain.

Obviously, in the embodiment of the present invention, the materials of the second sidewall 370 and the inner sidewall 373 are the same, as described above.

Referring to FIG. 20, the dielectric layer 380 and the bottom spacers are removed.

The functions, processes, and steps of removing the dielectric layer 380 and the bottom sidewall are the same as those in the second embodiment, and will not be repeated here.

Here, it should be noted that, after removing the dielectric layer 380, the source/drain can be formed directly on the bottom sidewall spacer (as in the first embodiment), or the bottom sidewall spacer can be removed to form the bottom isolation structure (as in the first embodiment) Second Embodiment), no specific limitation is made here. In the embodiment of the present invention, after removing the dielectric layer 380 , the bottom spacer is continued to be removed to form a bottom isolation structure, exposing the substrate 300 .

Referring to FIG. 21 , bottom isolation structures are formed between the sidewall isolation structures at the bottom of the source/drain regions 360 .

The function, type, process, steps, material selection, position of the top surface and doping type for forming the bottom isolation structure are all the same as those of the second embodiment, and will not be repeated here.

Here, it should be noted that the sidewall spacers 371 serve as the sidewall isolation structure, and the bottom barrier layer 372 serves as the bottom isolation structure.

Referring to FIG. 22 , source/drain regions 3310 are formed in the source/drain regions 360 .

The function of forming the source/drain 3310 , the process method, and the material selection are all the same as those in the second embodiment, and will not be repeated here.

Referring to FIG. 23 , a first dielectric layer 3320 is formed on top of the source/drain 3310 .

The functions, processes, steps, and selection of materials for forming the first dielectric layer 3320 are all the same as those in the second embodiment, and are not repeated here.

Referring to FIG. 24 , the dummy gate 350 and the sacrificial layer 310 are removed to form a trench, and a gate dielectric layer 3330 and a gate electrode 3340 are formed in the trench.

The functions, processes, steps, material selection, and positional relationship between the structures of removing the dummy gate 350 and the sacrificial layer 310 and forming the gate dielectric layer 3330 and the gate electrode 3340 are the same as those in the second embodiment, and will not be repeated here.

Referring to FIG. 25 , metal lines 3360 are formed on the surface of the gate electrode 3340 to form a second dielectric layer 3350 covering the second sub-gate structure and the first dielectric layer 3320 .

The functions, processes, steps, and selection of materials for forming the second dielectric layer 3350 and the metal lines 3360 are the same as those in the second embodiment, and will not be repeated here.

To sum up, according to the third embodiment of the present invention, the isolation structure existing between the source/drain 3310 and the substrate 300 includes: a sidewall isolation structure and a bottom isolation structure at the bottom of the source/drain region 360 . The isolation of the two reduces the leakage of current between the source/drain 3310 and the substrate 300 . At the same time, there are internal spacers 373 between the gate 3340 and the source/drain 3310, which increases the distance between the gate 3340 and the source/drain 3310, and solves the parasitic between the gate 3340 and the source/drain 3310. The problem of excessive capacitance improves the performance of nanowire transistors.

Correspondingly, please continue to refer to FIG. 25. An embodiment of the present invention also provides a nanowire transistor. The difference between the nanowire transistor provided by the third embodiment of the present invention and the nanowire transistor of the second embodiment is: There are internal spacers between the gate structure and the source/drain, increasing the distance between the gate structure and the source/drain. The positional relationships of other structures are the same as those of the nanowire transistor of the second embodiment, and are not repeated here.

In this embodiment of the present invention, it further includes: an inner side wall 373 .

Internal spacers 373 are located between the source/drain 3310 and the gate structure. The inner spacer 373 increases the distance between the gate structure and the source/drain 3310, reduces the excessive parasitic capacitance between the two, and improves the performance of the nanowire transistor.

To sum up, in the nanowire transistor provided in the third embodiment, the sidewall isolation structure and the bottom isolation structure effectively isolate the substrate 300 from the source/drain 3310 , with less current leakage; the internal sidewall 373 increases the source/drain The distance between the /drain 3310 and the gate structure is reduced, and the excessive parasitic capacitance between the source/drain 3310 and the gate structure is reduced.

So far, the present invention has been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concept of the present invention. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

While some specific embodiments of the present invention have been described in detail by way of example, those skilled in the art will appreciate that the above examples are provided for illustration only and not for the purpose of limiting the scope of the invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (37)

1. a kind of nano-wire transistor characterized by comprising

The gate structure being set on substrate；

Source/drain, the source/drain are located at the two sides of the gate structure；

Nano wire, the nano wire are set to inside the gate structure, the two sides of the nano wire with the source/drain Contact；With

Isolation structure, the isolation structure are formed between the substrate and the source/drain, the substrate and described is isolated Source/drain.

2. nano-wire transistor according to claim 1, which is characterized in that the nano wire number is one or more, when When the nano wire is multiple, the multiple nano wire longitudinally spaced distributions are inside the gate structure.

3. nano-wire transistor according to claim 1, which is characterized in that the isolation structure covers the source/drain The substrate of lower section so that the source/drain not with the substrate contact.

4. nano-wire transistor according to claim 3, which is characterized in that the highest point of the isolation structure two sides is low The top surface of the nano wire described in bottommost.

5. nano-wire transistor according to claim 4, which is characterized in that the highest point of the isolation structure two sides is not Higher than the bottom surface of nano wire described in bottommost.

6. nano-wire transistor according to claim 4, which is characterized in that the isolation structure includes: side wall isolation junction Structure and bottom isolation structure, wherein the sidewall isolation structure is located at the two sides of the isolation structure, the bottom isolation structure It is in contact between the sidewall isolation structure, and with the sidewall isolation structure.

7. nano-wire transistor according to claim 6, which is characterized in that the two sides of the isolation structure are respectively institute It is stating sidewall isolation structure with the non-contacting side of bottom isolation structure.

8. nano-wire transistor according to claim 6, which is characterized in that the sidewall isolation structure is side wall side wall, The bottom isolation structure is bottom side wall or bottom barrier.

9. nano-wire transistor according to claim 8, which is characterized in that the bottom barrier includes diffusion barrier layer The conducting barrier layer and/or.

10. nano-wire transistor according to claim 8, which is characterized in that when the sidewall isolation structure is the side Wall side wall, and when the bottom isolation structure is the bottom side wall, the sidewall isolation structure and the bottom isolation structure Material it is identical, be SiO₂, one of SiN, SiON, SiOCN or a variety of.

11. nano-wire transistor according to claim 8, which is characterized in that when the sidewall isolation structure is the side Wall side wall, and when the bottom isolation structure is the bottom barrier, the material of the sidewall isolation structure is SiO₂、SiN、 One of SiON, SiOCN or a variety of, the material of the bottom isolation structure are in Si, SiGe, Ge, GaAs, SiC, SiGeC It is one or more.

12. nano-wire transistor according to claim 1, which is characterized in that further include: internal side wall, the private side Wall is between the source/drain and the gate structure being in contact with the bottom surface of the nano wire.

13. nano-wire transistor according to claim 1, which is characterized in that the gate structure includes: grid and covering The gate dielectric layer of the gate surface.

14. nano-wire transistor according to claim 1, which is characterized in that further include: protection structure, the protection knot Structure covers the top surface of the nano wire of top.

15. nano-wire transistor according to claim 14, which is characterized in that further include:

First side wall, first side wall cover the two sidewalls of the gate structure of the protection superstructure；

First dielectric layer, first dielectric layer cover the source/drain；

Second dielectric layer, second dielectric layer cover the gate structure, first dielectric layer and the first side wall table Face；With

Metal wire, the metal wire are contacted through second dielectric layer and with the gate structure.

16. a kind of preparation method of nano-wire transistor characterized by comprising

The sacrificial layer and nano wire being stacked with is formed on the substrate；

Pseudo- grid are formed, the puppet grid are located above the sacrificial layer and the nano wire of the stacking；

The sacrificial layer and the nano wire between the adjacent pseudo- grid are removed, to form source/drain region；

Isolation structure is formed, the isolation structure is located at the substrate surface of the source/drain region bottom, described in isolation Source/drain region and the substrate；With

Form source/drain in the source/drain region, the source/drain is located above the isolation structure, and with adjacent institute State the side contact of nano wire.

17. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the sacrifice of bottommost Layer contacted with the surface of the substrate, the nano wire of bottommost not with the substrate contact.

18. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the nano wire of stacking Number be one or more.

19. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the isolation structure covering The substrate below the source/drain region.

20. the preparation method of nano-wire transistor according to claim 19, which is characterized in that

Formed the isolation structure include:

It forms sidewall isolation structure and bottom isolation structure, the sidewall isolation structure is located at the two of the bottom isolation structure Side, bottom isolation structure are in contact between the sidewall isolation structure, and with the sidewall isolation structure.

21. the preparation method of nano-wire transistor according to claim 20, which is characterized in that

The step of forming the sidewall isolation structure and the bottom isolation structure include:

The second side wall is formed, second side wall covers the pseudo- grid side of the source/drain region two sides, the nanometer line side Substrate surface described in face, the sacrificial layer side and the source/drain region bottom；

The dielectric layer for covering the second side wall surface described in the source/drain region bottom is formed, the top surface of the dielectric layer is low In the top surface of the nano wire of bottommost, and it is higher than the bottom surface with the sacrificial layer of bottommost；With

Part second side wall for removing the source/drain region two sides, makes the source/drain region two sides remaining described second The top surface of side wall is concordant with the top surface of the dielectric layer, to form the side wall side wall and the bottom side wall, In, remaining second side wall in source/drain region two sides is the side wall side wall, and the side wall side wall is the side wall Isolation structure, second side wall positioned at the dielectric layer bottom is the bottom side wall, and the bottom side wall is described Bottom isolation structure.

22. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the isolation structure two sides Top surface of the highest point in face lower than nano wire described in bottommost.

23. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the isolation structure two sides Bottom surface of the highest point in face not higher than nano wire described in bottommost.

24. the preparation method of nano-wire transistor according to claim 23, which is characterized in that the two of the isolation structure Side be respectively the sidewall isolation structure with the non-contacting side of bottom isolation structure.

25. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the sidewall isolation structure For side wall side wall, the bottom isolation structure is bottom side wall or bottom barrier.

26. the preparation method of nano-wire transistor according to claim 25, which is characterized in that when the side wall isolation junction Structure is the side wall side wall, and when the bottom isolation structure is the bottom side wall, the sidewall isolation structure and the bottom The material of portion's isolation structure is identical, is SiO₂, one of SiN, SiC, SiOCN or a variety of.

27. the preparation method of nano-wire transistor according to claim 25, which is characterized in that when the side wall isolation junction Structure be the side wall side wall, and the bottom isolation structure be the bottom barrier when, the material of the sidewall isolation structure For SiO₂, one of SiN, SiON, SiOCN or a variety of, the material of the bottom isolation structure is Si, SiGe, Ge, GaAs, One of SiC, SiGeC or a variety of.

28. the preparation method of nano-wire transistor according to claim 21, which is characterized in that

The step of forming the sidewall isolation structure and the bottom isolation structure further include:

Remove the dielectric layer；

Remove the bottom side wall, the exposure substrate；With

The substrate surface between the side wall side wall forms the bottom barrier, and the bottom barrier is the bottom Portion's isolation structure.

29. the preparation method of nano-wire transistor according to claim 28, which is characterized in that the bottom barrier packet Include diffusion barrier layer and/or conducting barrier layer.

30. the preparation method of nano-wire transistor according to claim 29, which is characterized in that the diffusion barrier layer with The ionic type of the source drain doping on the contrary, the ion adulterated in the diffusion barrier layer be boron (B), one in gallium (Ga) Kind is a variety of.

31. the preparation method of nano-wire transistor according to claim 29, which is characterized in that the conducting barrier layer with The ionic type of the source drain doping is identical, doped with: one of boron (B), gallium (Ga) or a variety of or arsenic (As), rhodium One of (Rh) or it is a variety of.

32. the preparation method of nano-wire transistor according to claim 21, which is characterized in that further include:

Before forming second side wall, the part sacrificial layer is removed, is opened with being formed in the two sides of every layer of sacrificial layer Mouthful；With

When forming second side wall, each opening is filled to form internal side wall.

33. the preparation method of nano-wire transistor according to claim 32, which is characterized in that the depth model of the opening It encloses for 2nm~20nm.

34. the preparation method of nano-wire transistor according to claim 16, which is characterized in that

After forming the source/drain, further includes:

Form the first dielectric layer for covering the source/drain；

The pseudo- grid and the sacrificial layer are removed, to form groove；With

Gate structure is formed in the groove.

35. the preparation method of nano-wire transistor according to claim 34, which is characterized in that

After forming the gate structure, further includes:

Form the second dielectric layer for covering the gate structure and first dielectric layer；With

The metal wire for running through second dielectric layer is formed, the metal wire is contacted with the gate structure.

36. the preparation method of nano-wire transistor according to claim 16, which is characterized in that

It is formed before the pseudo- grid, further includes:

Form protection structure, the top surface of the sacrificial layer and the nano wire that the protection structure covering stacks.

37. the preparation method of nano-wire transistor according to claim 16, which is characterized in that

After forming the pseudo- grid, before forming the isolation structure, further includes: form the covering pseudo- grid two sides First side wall.