CN109755170B - High voltage metal oxide semiconductor device and method of manufacturing the same - Google Patents

Abstract

A high-voltage metal oxide semiconductor device and a method for manufacturing the same, wherein the high-voltage metal oxide semiconductor device comprises: a well region, a drift region, a gate, a source, a drain and a plurality of buried pillars. The gate is formed on the upper surface, and part of the gate is stacked and connected directly above a part of the well region, and another part is stacked and connected directly above a part of the drift region. The source is formed below the upper surface and contacts the upper surface, and is laterally adjacent to the well region. The drain is formed below the upper surface and contacts the upper surface, and is laterally adjacent to the drift region, and is separated from the source by the well region and the drift region, and laterally, the drain and the source are located on different sides of the gate. A plurality of buried pillars are formed below a preset distance below the upper surface, and do not contact the upper surface, and the drift region surrounds at least a portion of each buried pillar, so that the plurality of buried pillars are staggered with the drift region.

Description

High voltage metal oxide semiconductor device and method of manufacturing the same

technical field

The present invention relates to a high-voltage metal oxide semiconductor (Metal Oxide Semiconductor, MOS) semiconductor element, in particular to a high-voltage metal oxide semiconductor element which can improve the breakdown protection voltage without affecting the on-resistance. The present invention also relates to a method of manufacturing a high voltage metal oxide semiconductor element.

Background technique

1A , 1B and 1C respectively show a top view, a corresponding cross-sectional view and a perspective view of a prior art high voltage metal oxide semiconductor device (N-type high voltage MOS device 100 ). As shown in FIGS. 1A , 1B and 1C, the high-voltage MOS device 100 is formed on a semiconductor substrate 11 , wherein the semiconductor substrate 11 has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction. The high-voltage MOS device 100 includes: P-type The well region 12 , the insulating oxide region 13 , the N-type drift region 14 , the gate electrode 15 , the N-type source electrode 16 and the N-type drain electrode 16 ′.

2A , 2B and 2C respectively show a top view, a corresponding cross-sectional view and a perspective view of a prior art high voltage metal oxide semiconductor device (N-type high voltage MOS device 200 ). As shown in FIGS. 2A , 2B and 2C , the high-voltage MOS device 200 is formed on the semiconductor substrate 11 . The high voltage MOS device 200 includes: a P-type well region 22 , an insulating oxide region 13 , a field oxide region 13 ′, a body region 24 , a gate electrode 25 , a source electrode 16 , a drain electrode 16 ′ and a body electrode 27 .

The prior art shown in FIGS. 1A, 1B and 1C and FIGS. 2A, 2B and 2C has the disadvantage that when the N-type high voltage metal oxide semiconductor devices 100 and 200 are in operation, due to the on-resistance and the breakdown protection voltage, the The trade-off relationship of the dilemma is that increasing the breakdown protection voltage will lead to an increase in the on-resistance; reducing the on-resistance will reduce the breakdown protection voltage. Such a situation is well known to those skilled in the art in the high-voltage MOS device, and will not be repeated here.

Compared with the prior art of FIGS. 1A , 1B and 1C and FIGS. 2A , 2B and 2C, the present invention can improve the breakdown protection voltage without affecting the on-resistance, thereby reducing cost, increasing efficiency, or expanding its application range.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and to provide a high-voltage metal oxide semiconductor device and a manufacturing method thereof, which can improve the breakdown protection voltage without affecting the on-resistance, thereby reducing the cost or increasing the efficiency, or Expand its scope of application.

In order to achieve the above object of the invention, in one aspect, the present invention provides a high-voltage metal oxide semiconductor (MOS) element formed on a semiconductor substrate, wherein the semiconductor substrate has opposite sides in a longitudinal direction. An upper surface and a lower surface, the high voltage MOS device includes: a well region with a first conductivity type, in the longitudinal direction, formed below the upper surface and connected to the upper surface; a drift region with a second conductivity type conductivity type, in the longitudinal direction, formed under the upper surface and connected to the upper surface, and the drift region is completely located on the well region, and in a lateral direction, the drift region is connected with the well region; a gate , in the longitudinal direction, formed on the upper surface, and a part of the gate is stacked and connected to a part directly above the well region, and another part of the gate is stacked and connected to a part directly above the drift region; a source electrode, It has the second conductivity type, is formed below the upper surface in the longitudinal direction and is in contact with the upper surface, is adjacent to the well region in the lateral direction, and the source electrode is connected under a first side of the gate electrode ; a drain, having the second conductivity type, in the longitudinal direction, formed below the upper surface and in contact with the upper surface, and adjacent to the drift region in the lateral direction, and the source by the well region and the The drift region is separated, and in the lateral direction, the drain is located outside a second side of the gate, and the source is located on a different side of the gate; and a plurality of buried columns have the The first conductivity type is formed under a predetermined distance below the upper surface in the longitudinal direction, and does not contact the upper surface, and the drift region surrounds at least a part of each buried column, so that the plurality of buried columns staggered with the drift region.

In a preferred embodiment, the high-voltage MOS device further includes a deep well region with the first conductivity type, formed under the well region and the drift region in the longitudinal direction, and the deep well region and the Multiple buried column connections.

In a preferred embodiment, the plurality of buried pillars and the drift region between the well region and the drain region are completely depleted during a non-conducting operation.

In a preferred embodiment, the predetermined distance is greater than 0.1 micrometer (μm).

From another point of view, the present invention also provides a high-voltage metal oxide semiconductor (Metal Oxide Semiconductor, MOS) device manufacturing method, comprising: providing a semiconductor substrate, in a longitudinal direction, has an opposite upper surface and a lower surface; A well region is formed under and connected to the upper surface, the well region has a first conductivity type; a drift region is formed under the upper surface and connected to the upper surface, and the drift region is completely located in the well On the top surface, the drift region has a second conductivity type, and in a lateral direction, the drift region is connected to the well region; a gate is formed on the upper surface, and part of the gate is stacked and connected to part of the well region just above the gate, and another part of the gate is stacked and connected to part of the drift region; a source is formed below and in contact with the upper surface, the source has the second conductivity type, and is located on the Adjacent to the well region in the lateral direction, and the source electrode is connected under a first side of the gate electrode; a drain electrode is formed under the upper surface and in contact with the upper surface, and the drain electrode has the second conductivity type, and adjacent to the drift region in the lateral direction, and the drain and the source are separated by the well region and the drift region, and the drain is located outside a second side of the gate in the lateral direction, and the source is located on a different side of the gate; and a plurality of buried columns are formed under a predetermined distance below the upper surface and not in contact with the upper surface, the buried columns have the first conductive and the drift region surrounds at least a part of each buried pillar, so that the plurality of buried pillars and the drift region are staggered.

In a preferred embodiment, the method for manufacturing a high-voltage MOS device further includes: forming a deep well region under the well region and the drift region, the deep well region has the first conductivity type, and the deep well region and The plurality of buried columns are connected.

In a preferred embodiment, the plurality of buried pillars and the drift region between the well region and the drain region are completely depleted during a non-conducting operation.

In a preferred embodiment, the predetermined distance is greater than 0.1 micrometer (μm).

From another point of view, the present invention also provides a high-voltage metal oxide semiconductor (Metal Oxide Semiconductor, MOS) device formed on a semiconductor substrate, wherein the semiconductor substrate has an opposite upper surface and a lower surface in a longitudinal direction , the high-voltage MOS device includes: a body region with a first conductivity type, in the longitudinal direction, formed below the upper surface and connected to the upper surface; a drift well region with a second conductivity type, in the longitudinally, formed below the upper surface and connected to the upper surface, and the body region is completely located on the drift well region, and in a lateral direction, the drift well region is connected to the body region; a gate, on the longitudinally, formed on the upper surface, and part of the gate is stacked and connected to part of the body region, and another part of the gate is stacked and connected to part of the drift well region; a source has the The second conductivity type, in the longitudinal direction, is formed under the upper surface and in contact with the upper surface, adjacent to the body region in the lateral direction, and the source electrode is connected under a first side of the gate electrode; a A drain, having the second conductivity type, is formed below the upper surface in the longitudinal direction and is in contact with the upper surface, and is adjacent to the drift well region in the lateral direction, and the source is connected by the body region and the The drift well regions are separated, and in the lateral direction, the drain electrode is located outside a second side of the gate electrode, and the source electrode is located on a different side of the gate electrode; and a plurality of buried columns have the The first conductivity type is formed under a predetermined distance below the upper surface in the longitudinal direction, and is not in contact with the upper surface, and the drift well region surrounds at least a part of each buried column, so that the plurality of buried pillars are buried Pillars are staggered with the drift trap region.

In a preferred embodiment, the high-voltage MOS device further includes a deep well region with the first conductivity type, formed under the drift well region in the longitudinal direction, and the deep well region is connected to the plurality of buried wells. Column connection.

In a preferred embodiment, the high-voltage MOS device further includes a field oxide region formed on the upper surface in the longitudinal direction, and a portion of the gate is stacked and connected to a portion directly above the field oxide region.

In a preferred embodiment, the high-voltage MOS device further includes a body electrode with the first conductivity type, formed under the upper surface in the longitudinal direction, connected to the upper surface, and connected to the body region, as an electrical contact for the body region.

In a preferred embodiment, the buried pillars and the drift well region between the body region and the drain are completely depleted during a non-conducting operation.

In a preferred embodiment, the predetermined distance is greater than 0.1 micrometer (μm).

From another point of view, the present invention also provides a high-voltage metal oxide semiconductor (Metal Oxide Semiconductor, MOS) device manufacturing method, comprising: providing a semiconductor substrate, in a longitudinal direction, has an opposite upper surface and a lower surface; A body region is formed under the upper surface and connected to the upper surface, the body region has a first conductivity type; a drift well region is formed under the upper surface and connected to the upper surface, the drift well region has a first conductivity type Two conductivity types, and the body region is completely located on the drift well region, and in a lateral direction, the drift well region and the body region are connected; a gate is formed on the upper surface, and part of the gate is stacked and connected A part is directly above the body region, and another part of the gate is stacked and connected to a part directly above the drift well region; a source electrode is formed under the upper surface and in contact with the upper surface, and the source electrode has the second conductive type, and is adjacent to the body region in the lateral direction, and the source electrode is connected under a first side of the gate electrode; a drain electrode is formed under the upper surface and in contact with the upper surface, and the drain electrode has the The second conductivity type is adjacent to the drift well region in the lateral direction, the drain electrode and the source electrode are separated by the body region and the drift well region, and the drain electrode is located at the gate electrode in the lateral direction outside a second side of the gate, and the source is located on a different side of the gate; and a plurality of buried columns are formed under a predetermined distance below the upper surface, not in contact with the upper surface, the The buried pillars have the first conductivity type, and the drift well region surrounds at least a part of each buried pillar, so that the plurality of buried pillars and the drift well region are staggered.

In a preferred embodiment, the high-voltage MOS device manufacturing method further includes the following steps: forming a deep well region under the drift well region, the deep well region has the first conductivity type, and the deep well region and the Multiple buried column connections.

In a preferred embodiment, the high-voltage MOS device manufacturing method further includes the following steps: forming a field oxide region on the upper surface, and a portion of the gate is stacked and connected to a portion directly above the field oxide region.

In a preferred embodiment, the high-voltage MOS device manufacturing method further includes the following steps: forming a body pole below the upper surface and connected to the upper surface, and connected to the body region to serve as an electrical contact of the body region .

In a preferred embodiment, the buried pillars and the drift well region between the body region and the drain are completely depleted during a non-conducting operation.

The following describes in detail through specific embodiments, and it should be easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

1A, 1B and 1C respectively show a schematic top view, a schematic cross-sectional view and a perspective view of a high-voltage metal oxide semiconductor device in the prior art;

2A, 2B and 2C respectively show a schematic top view, a schematic cross-sectional view and a perspective view of an embodiment of the high voltage metal oxide semiconductor device of the present invention;

3A-3C show a first embodiment of the present invention;

4A-4C show a second embodiment of the present invention;

5A-5C show a third embodiment of the present invention;

6A and 6B show a fourth embodiment of the present invention;

7A and 7B show a fifth embodiment of the present invention;

8A and 8B show a sixth embodiment of the present invention;

9A and 9B show a seventh embodiment of the present invention;

10A-10L show an eighth embodiment of the present invention;

11A-11L show a ninth embodiment of the present invention.

Description of symbols in the figure

100, 200, 300, 400, 500, 600, 700, 800, 900, 1100 high voltage MOS components

11 Semiconductor substrate

11’ top surface

11” lower surface

12 well area

13 Insulating oxide zone

13’ Field Oxidation Zone

13a Operating area

14 Drift Zone

15, 25 grid

16 Source

16' drain

22 Drift well region

24 Body area

27 Body pole

38 Deep well region

39, 49 Buried Column

A-A’ section line

d preset distance

S1 first side

S2 second side

Detailed ways

The drawings in the present invention are schematic, mainly intended to represent the process steps and the top-bottom order relationship between the layers, and the shapes, thicknesses and widths are not drawn to scale.

Please refer to FIGS. 3A-3C , which respectively show a top view and a corresponding cross-sectional view of an embodiment of a high-voltage metal oxide semiconductor device (a high-voltage MOS device 300 ) according to the present invention ( FIG. 3B corresponds to the section line A- of the top view). A') and perspective view Fig. 3C. As shown in FIGS. 3A , 3B and 3C, the high-voltage MOS device 300 is formed on a semiconductor substrate 11, which has an opposite upper surface 11' and a lower surface in a longitudinal direction (in the direction of the dashed arrow in FIG. 3B, the same below). Surface 11 ″. The high voltage MOS device 300 includes: a well region 12 , an insulating oxide region 13 , a drift region 14 , a gate electrode 15 , a source electrode 16 , a drain electrode 16 ′ and a buried column 39 .

Please continue to refer to FIGS. 3A, 3B and 3C, wherein the well region 12 has the first conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 300, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The drift region 14 has the second conductivity type, and is located below and connected to the upper surface 11' in the longitudinal direction, and the drift region 14 is completely located on the well region 12; The direction of the line arrow, the same below), the drift region 14 is connected to the well region 12 . The gate 15 is formed on the upper surface 11', and in the longitudinal direction, a part of the gate 15 is stacked and in contact with a part of the well region 12 directly above, and another part of the gate 15 is stacked directly above a part of the drift region 14; need to be explained It is important that the gate 15 only overlaps with the well region 12 in the vertical vertical projection, which is the channel region of the high voltage MOS element 300 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the well region 12 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 15 Below S1. The drain 16 ′ has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the drift region 14 in the lateral direction, and is connected to the source 16 by the well region 12 and the drift region. 14 is spaced apart, and in the lateral direction, the drain 16 ′ is located outside the second side S2 of the gate 15 , and the source 16 is located on a different side of the gate 15 .

Please continue to refer to FIGS. 3A , 3B and 3C. The buried pillars 39 are of the first conductivity type and are longitudinally formed below the upper surface 11 ′ by a predetermined distance d and do not contact the upper surface 11 ′. As shown in the figure, the drift region 14 surrounds at least a part of each buried pillar 39 , so that a plurality of buried pillars 39 and the drift region 14 are staggered. In a preferred embodiment, the plurality of buried pillars 39 and the drift region 14 between the well region 12 and the drain 16' are completely depleted during non-conducting operation.

It is worth noting that one of the technical features of the present invention over the prior art is that, according to the present invention, taking the high-voltage MOS device 300 as an example, the plurality of buried pillars 39 of the first conductivity type and the drift region 14 of the second conductivity type have When the reverse bias voltage is high, a super junction can be generated through the depletion effect of the adjacent two buried pillars 39 and the drift region 14 in the space between them, that is, two-phase In this case, the adjacent buried pillar 39 and the drift region 14 in the space are all depleted regions, so that it can withstand a higher voltage and improve the breakdown protection voltage; There is a predetermined distance d between the surfaces 11', so that the on-current of the high-voltage MOS device 300 is not reduced due to the buried pillar 39 during the on-operation, which makes the on-resistance unaffected, that is, the high-voltage MOS device according to the present invention Compared with the prior art, the 300 can increase the breakdown protection voltage without affecting the on-resistance, thereby reducing the cost, increasing the efficiency, or expanding its application range. In a preferred embodiment, the buried pillar 39 is electrically connected to the well region 12 , or the buried pillar 39 is biased by the well region 12 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm).

It should be noted that the above-mentioned "first conductivity type" and "second conductivity type" refer to the high-voltage MOS device, in which impurities of different conductivity types are doped into the semiconductor constituent regions (such as but not limited to the aforementioned drift region, In the body region, body connection region, source, drain and gate regions), the semiconductor composition region becomes the first or second conductivity type (for example, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa). In addition, it should be noted that the upper surface 11 ′ refers to the surface of the upper edge of the semiconductor substrate 11 in the longitudinal direction. When the high-voltage MOS element is turned on, a current will flow, and the upper surface 11 ′ will be affected by various parts of the high-voltage MOS element. , such as the position of the oxidation zone, and there will be ups and downs in the morphology.

In addition, it should be noted that the so-called high-voltage MOS device refers to that the voltage applied to the drain is higher than a specific voltage, such as 5V or other higher voltages during normal operation; in this embodiment, the voltage of the high-voltage MOS device is The drain 16' and the aforementioned channel region are separated by the drift region 14, and the lateral distance between the drift region 14 and the drain 16' is adjusted according to the operating voltage under normal operation, so it can operate at the aforementioned higher specific voltage.

4A-4C show a second embodiment of the present invention. 4A-4C respectively show a top view, a corresponding cross-sectional view (FIG. 4B corresponds to the section line AA' of the top view) and a perspective view of an embodiment of a high-voltage metal oxide semiconductor device (high-voltage MOS device 400 ) according to the present invention Figure 4C. As shown in FIGS. 4A , 4B and 4C, the high-voltage MOS device 400 is formed on the semiconductor substrate 11 , which has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction (in the direction of the dotted arrow in FIG. 4B , the same below). The high voltage MOS device 400 includes: a well region 12 , an insulating oxide region 13 , a drift region 14 , a gate electrode 15 , a source electrode 16 , a drain electrode 16 ′, a deep well region 38 and a buried column 49 .

Please continue to refer to FIGS. 4A, 4B and 4C, wherein the well region 12 has the first conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 400, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The drift region 14 has the second conductivity type, is located below the upper surface 11' and is connected to the upper surface 11' in the longitudinal direction, and the drift region 14 is completely located on the well region 12; The direction of the line arrow, the same below), the drift region 14 is connected to the well region 12 . The gate 15 is formed on the upper surface 11', and in the longitudinal direction, a part of the gate 15 is stacked and in contact with a part of the well region 12 directly above, and another part of the gate 15 is stacked directly above a part of the drift region 14; need to be explained It is that the gate 15 only overlaps with the well region 12 in the vertical vertical projection, which is the channel region of the high voltage MOS element 400 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the well region 12 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 15 Below S1. The drain 16 ′ has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the drift region 14 in the lateral direction, and is connected to the source 16 by the well region 12 and the drift region. 14 is spaced apart, and in the lateral direction, the drain 16 ′ is located outside the second side S2 of the gate 15 , and the source 16 is located on a different side of the gate 15 .

Please continue to refer to FIGS. 4A , 4B and 4C, the deep well region 38 has the first conductivity type, is formed vertically below the well region 12 and the drift region 14 and is connected to the well region 12 up and down, and the deep well region 38 is connected to the multiple A buried column 49 is connected. The plurality of buried pillars 49 have the first conductivity type and are formed below the upper surface 11 ′ by a predetermined distance d in the longitudinal direction, and do not contact the upper surface 11 ′, as shown in the figure, and the drift region 14 surrounds each A part of a buried pillar 49 , a plurality of buried pillars 49 are staggered with the drift region 14 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm).

The difference between this embodiment and the first embodiment is that, first of all, the plurality of buried pillars 39 in the first embodiment are arranged in parallel along the lateral direction, while the plurality of buried pillars 49 in this embodiment are arranged along the width. The directions (the directions of the dashed arrows in FIGS. 4A and 4C , the same below) are arranged in parallel. In addition, compared with the high-voltage MOS device 300 in this embodiment, the high-voltage MOS device 400 further includes a deep well region 38 , which can be electrically connected to the buried pillar 49 to bias the buried pillar 49 . In a preferred embodiment, the plurality of buried pillars 49 and the drift region 14 between the well region 12 and the drain 16' are completely depleted during non-conducting operation.

5A-5C show a third embodiment of the present invention. 5A-5C respectively show a top view, a corresponding cross-sectional view ( FIG. 5B corresponds to the section line AA' of the top view) and a perspective view of an embodiment of a high-voltage metal oxide semiconductor device (high-voltage MOS device 500 ) according to the present invention Figure 5C. As shown in FIGS. 5A , 5B and 5C, the high-voltage MOS device 500 is formed on the semiconductor substrate 11 , which has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction (in the direction of the dashed arrow in FIG. 5B , the same below). The high voltage MOS device 500 includes: drift well region 22 , insulating oxide region 13 , body region 24 , gate electrode 15 , source electrode 16 , drain electrode 16 ′, body electrode 27 , deep well region 38 and buried pillar 39 .

Please continue to refer to FIGS. 5A, 5B and 5C, wherein the drift well region 22 has the second conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 500, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The body region 24 has the first conductivity type, and is located below and connected to the upper surface 11 ′ in the longitudinal direction, and the body region 24 is completely located on the drift well region 22 and is laterally (as shown in FIG. 5B ) The direction of the solid line arrow, the same below), the drift well region 22 is connected to the body region 24 . The gate 15 is formed on the upper surface 11', and in the longitudinal direction, a part of the gate 15 is stacked and in contact with a part of the drift well region 22 directly above, and another part of the gate 15 is stacked directly above a part of the body region 24; It is noted that the position where the gate 15 only overlaps with the body region 24 in the vertical vertical projection is the channel region of the high voltage MOS device 500 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 15 Below S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source electrode 16 is formed by the drift well region 22 and The body regions 24 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 15 , and the source electrode 16 is located on a different side of the gate electrode 15 in the lateral direction.

Please continue to refer to FIGS. 5A , 5B and 5C, the deep well region 38 has the first conductivity type, and is formed vertically below the drift well region 22 and the body region 24 and is connected to the drift well region 22 up and down, and the deep well region 38 Connected to a plurality of buried pillars 39 . The plurality of buried pillars 39 have the first conductivity type, are formed vertically below the upper surface 11 ′ by a predetermined distance d, do not contact the upper surface 11 ′, as shown in the figure, and are surrounded by the drift well region 22 At least a part of each buried pillar 39 makes a plurality of buried pillars 39 staggered with the drift well region 22 . In a preferred embodiment, the buried pillar 39 is electrically connected to the deep well region 38 , or the buried pillar 39 is biased by the deep well region 38 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). In a preferred embodiment, the plurality of buried pillars 39 and the drift well region 22 between the body region 24 and the drain 16' are fully depleted during non-conducting operation. The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24.

The difference between this embodiment and the first embodiment is that, first of all, the first embodiment has a well region 12 and a drift region 14 . The drift region 14 is completely located on the well region 12 , while the body region 24 in this embodiment is completely located on the well region 12 . on the drift well region 22 . In addition, compared with the high-voltage MOS device 300 in this embodiment, the high-voltage MOS device 500 further includes a deep well region 38 , which can be electrically connected to the buried pillar 39 to bias the buried pillar 39 .

6A and 6B show a fourth embodiment of the present invention. 6A and 6B respectively show a top view and a corresponding cross-sectional view (FIG. 6B corresponds to the line A-A' of the top view) of an embodiment of a high voltage metal oxide semiconductor device (high voltage MOS device 600) according to the present invention. As shown in FIGS. 6A and 6B , the high voltage MOS device 600 is formed on the semiconductor substrate 11 , which has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction (in the direction of the dashed arrow in FIG. 6B , the same below). The high voltage MOS device 600 includes: a drift well region 22 , an insulating oxide region 13 , a body region 24 , a gate electrode 15 , a source electrode 16 , a drain electrode 16 ′, a body electrode 27 and a buried column 39 .

Please continue to refer to FIGS. 6A and 6B, wherein the drift well region 22 has the second conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 600, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The body region 24 has the first conductivity type and is located below and connected to the upper surface 11 ′ in the longitudinal direction, and the body region 24 is completely located on the drift well region 22 and is laterally (as in FIG. 6B ) The direction of the solid arrow, the same below), the drift well region 22 is connected to the body region 24 . The gate 15 is formed on the upper surface 11', and in the longitudinal direction, a part of the gate 15 is stacked and in contact with a part of the drift well region 22 directly above, and another part of the gate 15 is stacked directly above a part of the body region 24; It is noted that the position where the gate 15 only overlaps with the body region 24 in the vertical vertical projection is the channel region of the high voltage MOS device 600 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 15 Below S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source electrode 16 is formed by the drift well region 22 and The body regions 24 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 15 , and the source electrode 16 is located on a different side of the gate electrode 15 in the lateral direction.

Please continue to refer to FIGS. 6A and 6B , a plurality of buried pillars 49 of the first conductivity type are longitudinally formed below the upper surface 11 ′ by a predetermined distance d and do not contact the upper surface 11 ′, as shown in the figure As shown, the drift well region 22 surrounds at least a part of each buried pillar 49 , so that a plurality of buried pillars 49 and the drift well region 22 are staggered. In a preferred embodiment, the buried pillar 49 is electrically connected to the body region 24 , or the buried pillar 39 is biased by the body region 24 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). In a preferred embodiment, the plurality of buried pillars 49 and the drift well region 22 between the body region 24 and the drain 16' are fully depleted during non-conducting operation. The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24.

The difference between this embodiment and the third embodiment is that, firstly, the third embodiment has a deep well region 38 , while the high-voltage MOS device 600 in this embodiment does not include a deep well region. In addition, compared with the high voltage MOS device 500 in the high voltage MOS device 600 of the present embodiment, the body region 24 and the buried pillar 49 are laterally connected, and can be electrically connected to the buried pillar 49 to bias the buried pillar 49 . Furthermore, the plurality of buried pillars 39 in the third embodiment are arranged in parallel along the lateral direction, while the plurality of buried pillars 49 in this embodiment are arranged in parallel along the width direction.

7A and 7B show a fifth embodiment of the present invention. 7A and 7B respectively show a top view and a corresponding cross-sectional view (FIG. 7B corresponds to the line A-A' of the top view) of an embodiment of a high voltage metal oxide semiconductor device (high voltage MOS device 700) according to the present invention. As shown in FIGS. 7A and 7B , the high-voltage MOS device 700 is formed on the semiconductor substrate 11 , which has opposite upper and lower surfaces 11 ′ and 11 ″ in the longitudinal direction (in the direction of the dashed arrow in FIG. 7B , the same below). The high voltage MOS device 700 includes: a drift well region 22 , an insulating oxide region 13 , a body region 24 , a gate electrode 15 , a source electrode 16 , a drain electrode 16 ′, a body electrode 27 , a deep well region 38 and a buried pillar 49 .

Please continue to refer to FIGS. 7A and 7B , the deep well region 38 has the first conductivity type, is formed vertically below the drift well region 22 and the body region 24 and is connected to the drift well region 22 up and down, and the deep well region 38 is connected to the multiple A buried column 49 is connected. The drift well region 22 has the second conductivity type, is formed in the semiconductor substrate 11, and is located below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 700, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The body region 24 has the first conductivity type and is located below and connected to the upper surface 11 ′ in the longitudinal direction, and the body region 24 is completely located on the drift well region 22 and is laterally (as in FIG. 7B ) The direction of the solid arrow, the same below), the drift well region 22 is connected to the body region 24 . The gate 15 is formed on the upper surface 11', and in the longitudinal direction, a part of the gate 15 is stacked and in contact with a part of the drift well region 22 directly above, and another part of the gate 15 is stacked directly above a part of the body region 24; It is noted that the position where the gate 15 only overlaps with the body region 24 in the vertical vertical projection is the channel region of the high voltage MOS device 700 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 15 Below S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source electrode 16 is formed by the drift well region 22 and The body regions 24 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 15 , and the source electrode 16 is located on a different side of the gate electrode 15 in the lateral direction.

Please continue to refer to FIGS. 7A and 7B , the deep well region 38 has the first conductivity type, is formed vertically below the drift well region 22 and the body region 24 and is connected to the drift well region 22 up and down, and the deep well region 38 is connected to the multiple A buried column 49 is connected. The plurality of buried pillars 49 have the first conductivity type, are formed vertically below the upper surface 11 ′ by a predetermined distance d, do not contact the upper surface 11 ′, as shown in the figure, and are surrounded by the drift well region 22 At least a part of each buried pillar 49 makes a plurality of buried pillars 49 staggered with the drift well region 22 . In a preferred embodiment, the buried pillar 49 is electrically connected to the deep well region 38 , or the buried pillar 49 is biased by the deep well region 38 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). In a preferred embodiment, the plurality of buried pillars 49 and the drift well region 22 between the body region 24 and the drain 16' are fully depleted during non-conducting operation. The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24.

The difference between this embodiment and the third embodiment is that the plurality of buried pillars 39 in the third embodiment are arranged in parallel in the lateral direction, while the plurality of buried pillars 49 in this embodiment are parallel in the width direction arrangement.

8A and 8B show a sixth embodiment of the present invention. 8A and 8B respectively show a top view and a corresponding cross-sectional view (FIG. 8B corresponds to the section line A-A' of the top view) of an embodiment of a high voltage metal oxide semiconductor device (high voltage MOS device 800) according to the present invention. As shown in FIGS. 8A and 8B , the high-voltage MOS device 800 is formed on the semiconductor substrate 11 , which has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction (in the direction of the dashed arrow in FIG. 8B , the same below). The high-voltage The MOS device 800 includes a drift well region 22 , an insulating oxide region 13 , a field oxide region 13 ′, a body region 24 , a gate electrode 25 , a source electrode 16 , a drain electrode 16 ′, a body electrode 27 and a buried pillar 49 .

Please continue to refer to FIGS. 8A and 8B, wherein the drift well region 22 has the second conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 800, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The field oxide region 13' is formed on the upper surface 11' in the longitudinal direction, and a part of the gate electrode 25 is stacked and connected directly above the part of the field oxide region 13'. The body region 24 has the first conductivity type and is located below and connected to the upper surface 11 ′ in the longitudinal direction, and the body region 24 is completely located on the drift well region 22 and is laterally (as in FIG. 8B ) The direction of the solid arrow, the same below), the drift well region 22 is connected to the body region 24 . The gate 25 is formed on the upper surface 11 ′, and in the longitudinal direction, a part of the gate 25 is stacked and in contact with a part of the drift well region 22 directly above, and another part of the gate 25 is stacked directly above a part of the body region 24 ; It is noted that the gate 25 only overlaps with the body region 24 in the vertical vertical projection, which is the channel region of the high voltage MOS device 800 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and contacts the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 25 Below S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source electrode 16 is formed by the drift well region 22 and The body regions 24 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 25 , and the source electrode 16 is located on a different side of the gate electrode 25 in the lateral direction.

Please continue to refer to FIGS. 8A and 8B , the buried pillars 49 are of the first conductivity type, are longitudinally formed below the upper surface 11 ′ by a predetermined distance d, and do not contact the upper surface 11 ′ (the upper surface 11 ′). 8B), as shown in the figure, and the drift well region 22 surrounds at least a part of each buried pillar 49, so that a plurality of buried pillars 49 and the drift well region 22 are staggered. In a preferred embodiment, the buried pillar 49 is electrically connected to the body region 24 , or the buried pillar 39 is biased by the body region 24 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). In a preferred embodiment, the plurality of buried pillars 49 and the drift well region 22 between the body region 24 and the drain 16' are fully depleted during non-conducting operation. The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24.

The difference between this embodiment and the fourth embodiment is that, first, compared with the third embodiment, the high-voltage MOS device 800 of this embodiment further includes a field oxide region 13'. In addition, in the high-voltage MOS device 800 of the present embodiment, a part of the gate electrode 25 is stacked and connected to a part directly above the field oxide region 13'.

9A and 9B show a seventh embodiment of the present invention. 9A and 9B respectively show a top view and a corresponding cross-sectional view (FIG. 9B corresponds to the line A-A' of the top view) of an embodiment of a high voltage metal oxide semiconductor device (high voltage MOS device 900) according to the present invention. As shown in FIGS. 9A and 9B , the high-voltage MOS device 900 is formed on the semiconductor substrate 11 , which has opposite upper surfaces 11 ′ and lower surfaces 11 ″ in the longitudinal direction (in the direction of the dashed arrow in FIG. 9B , the same below). The high-voltage The MOS device 900 includes: a drift well region 22 , an insulating oxide region 13 , a field oxide region 13 ′, a body region 24 , a gate electrode 25 , a source electrode 16 , a drain electrode 16 ′, a body electrode 27 , a deep well region 38 and a buried pillar 39 .

Please continue to refer to FIGS. 9A and 9B , wherein the deep well region 38 has the first conductivity type, is formed vertically below the drift well region 22 and the body region 24 and is connected to the drift well region 22 up and down, and the deep well region 38 is connected to A plurality of buried pillars 39 are connected. The drift well region 22 has the second conductivity type, is formed in the semiconductor substrate 11, and is located below and connected to the upper surface 11' in the longitudinal direction. The insulating oxide region 13 is formed on the upper surface 11' to define the operating region 13a of the high-voltage MOS device 900, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. The field oxide region 13' is formed on the upper surface 11' in the longitudinal direction, and a part of the gate electrode 25 is stacked and connected directly above the part of the field oxide region 13'. The body region 24 has the first conductivity type and is located below and connected to the upper surface 11 ′ in the longitudinal direction, and the body region 24 is completely located on the drift well region 22 and is laterally (as in FIG. 9B ) The direction of the solid arrow, the same below), the drift well region 22 is connected to the body region 24 . The gate 25 is formed on the upper surface 11 ′, and in the longitudinal direction, a part of the gate 25 is stacked and in contact with a part of the drift well region 22 directly above, and another part of the gate 25 is stacked directly above a part of the body region 24 ; It is noted that the gate 25 only overlaps with the body region 24 in the vertical vertical projection, which is the channel region of the high-voltage MOS device 900 . The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and contacts the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first side of the gate electrode 25 Below S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source electrode 16 is formed by the drift well region 22 and The body regions 24 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 25 , and the source electrode 16 is located on a different side of the gate electrode 25 in the lateral direction.

Please continue to refer to FIGS. 9A and 9B , a plurality of buried pillars 39 of the first conductivity type are longitudinally formed below the upper surface 11 ′ by a predetermined distance d and do not contact the upper surface 11 ′ (the upper surface 11 ′). 9B), as shown in the figure, and the drift well region 22 surrounds at least a part of each buried pillar 39, so that a plurality of buried pillars 39 and the drift well region 22 are staggered. In a preferred embodiment, the buried pillar 39 is electrically connected to the deep well region 38 , or the buried pillar 39 is biased by the deep well region 38 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24.

The difference between this embodiment and the sixth embodiment is that, first, the high-voltage MOS device 900 of this embodiment further includes a deep well region 38 compared with the high-voltage MOS device 800 , which can be electrically connected to the buried pillar 39 to bias the buried pillar. 39. In addition, the plurality of buried pillars 39 in this embodiment are arranged in parallel along the lateral direction, while the plurality of buried pillars 49 in the sixth embodiment are arranged in parallel along the width direction.

10A-10L show an eighth embodiment of the present invention. 10A-10L show schematic top and cross-sectional views of a method for manufacturing a high-voltage MOS device (high-voltage MOS device 300 ) according to the present invention. First, as shown in the schematic top view FIG. 10A and the schematic cross-sectional view FIG. 10B ( FIG. 10B corresponds to the section line A-A' of the top view FIG. 10A ), a semiconductor substrate 11 is provided and a well region 12 is formed. The semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, and of course other semiconductor substrates. The semiconductor substrate 11 has an opposite upper surface 11 ′ and a lower surface 11 ″ in a longitudinal direction (in the direction of the dotted arrow in the figure). The well region 12 has a first conductivity type, is formed in the semiconductor substrate 11 and is in the longitudinal direction. The upper surface 11 ′ is located below and connected to the upper surface 11 ′ to form the well region 12 , such as, but not limited to, ion implantation.

Next, as shown in the schematic top view FIG. 10C and the schematic cross-sectional view FIG. 10D ( FIG. 10D corresponds to the section line AA' in the top view FIG. 10C ), an insulating oxide region 13 is formed on the upper surface 11 ′ (the upper surface 11 ′ is shown in the figure The thick black dotted line in 10D is used to define the operation area 13a of the high voltage MOS device 300, wherein the operation area 13a refers to the main range of applied voltage and current in conducting and non-conducting operations.

Next, as shown in the schematic top view FIG. 10E and the schematic cross-sectional view FIG. 10F ( FIG. 10F corresponds to the section line AA' of the top view FIG. 10E ), a drift region 14 is formed under the upper surface 11 ′ and connected to the upper surface 11 ′, The drift region 14 has the second conductivity type, and the drift region 14 is completely located on the well region 12; Among them, the method of forming the drift region 14, such as but not limited to the lithography process, the ion implantation process, and the thermal process, are well known to those skilled in the art, and will not be repeated here.

Next, as shown in the schematic top view FIG. 10G and the schematic cross-sectional view FIG. 10H ( FIG. 10H corresponds to the section line AA' of the top view FIG. 10G ), a plurality of buried columns 39 are formed under the upper surface 11 ′. Below the distance d, without contacting the upper surface 11 ′, the buried pillars 39 have the first conductivity type, and the drift region 14 surrounds at least a part of each buried pillar 39 , so that a plurality of buried pillars 39 and the drift region 14 are staggered. . The methods for forming the buried pillars 39, such as, but not limited to, a lithography process, an ion implantation process, and a thermal process are well known to those skilled in the art and will not be described here. In a preferred embodiment, the plurality of buried pillars 39 and the drift region 14 between the well region 12 and the drain 16' are completely depleted during non-conducting operation. It should be noted that, in the method of forming the buried pillar 39, for example, in the ion implantation process step, the implantation depth can be set to control the preset distance d; it can also be implanted with another ion in the subsequent steps. In the process step, in the range from the upper surface 11' to the predetermined distance d below the upper surface 11', the second conductivity type impurities are implanted, so that the range from the upper surface 11' to the predetermined distance d below the upper surface 11' is in the drift region. 14, a region of the second conductivity type is formed to avoid the region having the first conductivity type.

Next, as shown in the schematic top view FIG. 10I and the schematic cross-sectional view FIG. 10J ( FIG. 10J corresponds to the section line AA' in the top view FIG. 10I ), the gate 15 is formed on the upper surface 11 ′, and in the longitudinal direction, part of the gate is formed The electrode 15 is stacked and in contact with a part of the well region 12 directly above, and another part of the gate 15 is stacked directly above a part of the drift region 14; it should be noted that the gate 15 only overlaps with the well region 12 in the vertical vertical projection. , which is the channel region of the high-voltage MOS element 300 . The gate 15 includes a dielectric layer, a conductor layer, and a spacer layer, which are well known to those skilled in the art and will not be described here.

Next, as shown in the schematic top view FIG. 10K and the schematic cross-sectional view FIG. 10L ( FIG. 10L corresponds to the section line A-A' in the top view FIG. 10K ), a source electrode 16 and a drain electrode 16' are formed. The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the well region 12 in the lateral direction, and the source electrode 16 is connected to the first electrode of the gate electrode 15 . side S1 below. The drain 16 ′ has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the drift region 14 in the lateral direction, and is connected to the source 16 by the well region 12 and the drift region. 14 is spaced apart, and in the lateral direction, the drain 16 ′ is located outside the second side S2 of the gate 15 , and the source 16 is located on a different side of the gate 15 . The methods for forming the source electrode 16 and the drain electrode 16', such as, but not limited to, lithography process, ion implantation process, and thermal process are well known to those skilled in the art, and will not be repeated here. In a preferred embodiment, the buried pillar 39 is electrically connected to the well region 12 , or the buried pillar 39 is biased by the well region 12 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm).

11A-11L show a ninth embodiment of the present invention. 11A-11L show schematic top and cross-sectional views of a method for manufacturing a high-voltage MOS device (high-voltage MOS device 1100 ) according to the present invention. First, as shown in the schematic top view FIG. 11A and the schematic cross-sectional view FIG. 11B ( FIG. 11B corresponds to the section line A-A' of the top view FIG. 11A ), the semiconductor substrate 11 is provided and the deep well region 38 and the drift well region 22 are formed. The semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, and of course other semiconductor substrates. The semiconductor substrate 11 has an opposite upper surface 11' and a lower surface 11" in a longitudinal direction (in the direction of the dashed arrow in the figure). The deep well region 38 has a first conductivity type and is formed in the drift well region in the longitudinal direction. 22 is below the body region 24 formed in the subsequent steps, and is connected up and down with the drift well region 22, and the deep well region 38 is connected with a plurality of buried pillars 39 formed in the subsequent steps. The drift well region 22 has the second conductivity type, Formed in the semiconductor substrate 11, and located below and connected to the upper surface 11' in the longitudinal direction, to form the drift well region 22 and the deep well region 38, for example, but not limited to, an ion implantation process step formed.

Next, as shown in the schematic top view FIG. 11C and the schematic cross-sectional view FIG. 11D ( FIG. 11D corresponds to the section line AA' of the top view FIG. 11C ), an insulating oxide region 13 and a field oxide region 13 ′ are formed on the upper surface 11 ′ ( The upper surface 11' is indicated by the thick black dashed line in Fig. 11D). The insulating oxide region 13 is used to define the operating region 13a of the high-voltage MOS device 1100, wherein the operating region 13a refers to the main range of applied voltage and current in conducting and non-conducting operations. In the gate electrode 25 formed in the subsequent steps, a portion of the gate electrode 25 is stacked and connected to a portion directly above the field oxide region 13'.

Next, as shown in the schematic top view FIG. 11E and the schematic cross-sectional view FIG. 11F ( FIG. 11F corresponds to the section line AA′ of the top view FIG. 11E ), a plurality of buried columns 49 are formed to be preset below the upper surface 11 ′ Below the distance d, without contacting the upper surface 11 ′, the buried pillars 49 have the first conductivity type, and the drift well region 22 surrounds at least a part of each buried pillar 49 , so that a plurality of buried pillars 49 and the drift well region 22 are staggered arrangement. In a preferred embodiment, the buried pillar 49 is electrically connected to the deep well region 38 , or the buried pillar 49 is biased by the deep well region 38 . In a preferred embodiment, the predetermined distance d is greater than 0.1 micrometer (μm). In a preferred embodiment, the plurality of buried pillars 49 and the drift well region 22 between the body region 24 and the drain 16' are fully depleted during non-conducting operation. The methods for forming the buried pillars 49, such as, but not limited to, the lithography process, the ion implantation process, and the thermal process are well known to those skilled in the art and will not be described here. It should be noted that, in the method of forming the buried pillar 49, for example, in the ion implantation process step, the implantation depth can be set to control the preset distance d; it can also be implanted with another ion in the subsequent steps. In the process step, in the range from the upper surface 11' to the predetermined distance d below the upper surface 11', the second conductivity type impurities are implanted, so that the range from the upper surface 11' to the predetermined distance d below the upper surface 11' is in the drift well. Within the range of the region 22, a region of the second conductivity type is formed to prevent the region from having the first conductivity type. It should be noted that the plurality of buried pillars 49 in this embodiment are arranged in parallel along the width direction, and the buried pillars 49 are connected to the deep well region 38 .

Next, as shown in the schematic top view FIG. 11G and the schematic cross-sectional view FIG. 11H ( FIG. 11H corresponds to the section line AA′ of the top view FIG. 11G ), a body region 24 is formed, which has the first conductivity type and is located on the top in the longitudinal direction. Below the surface 11' and connected to the upper surface 11', and the body region 24 is completely located on the drift well region 22, and in the lateral direction (in the direction of the solid arrow in FIG. 11H, the same below), the drift well region 22 and the body Zone 24 is connected.

Next, as shown in the schematic top view FIG. 11I and the schematic cross-sectional view FIG. 11J ( FIG. 11J corresponds to the section line AA′ of the top view FIG. 11I ), the gate 25 is formed on the upper surface 11 ′, and in the longitudinal direction, part of the gate is formed The electrode 25 is stacked and in contact with a part of the body region 24 directly above, and another part of the gate 25 is stacked directly above a part of the drift well region 22; it should be noted that the vertical projection of the gate 25 only overlaps with the body region 24. where is the channel region of the high voltage MOS element 1100 . The gate 25 includes a dielectric layer, a conductor layer, and a spacer layer, which are well known to those skilled in the art, and will not be repeated here.

Next, as shown in the schematic top view FIG. 11K and the schematic cross-sectional view FIG. 11L ( FIG. 11L corresponds to the section line A-A' of the top view FIG. 11K ), the source electrode 16 , the drain electrode 16 ′ and the body electrode 27 are formed. The source electrode 16 has the second conductivity type, is formed below the upper surface 11 ′ in the longitudinal direction and is in contact with the upper surface 11 ′, and is adjacent to the body region 24 in the lateral direction, and the source electrode 16 is connected to the first electrode of the gate electrode 25 . Below the side S1. The drain 16 ′ has the second conductivity type, is formed vertically below the upper surface 11 ′ and is in contact with the upper surface 11 ′, and is adjacent to the drift well region 22 in the lateral direction, and the source 16 is separated from the body region 24 and the drift region 22 . The well regions 22 are separated, and the drain electrode 16 ′ is located outside the second side S2 of the gate electrode 25 in the lateral direction, and the source electrode 16 is located on a different side of the gate electrode 25 . The body pole 27 has the first conductivity type, and is formed below the upper surface 11' and connected to the upper surface 11' in the longitudinal direction, and is connected to the body region 24 to serve as an electrical contact of the body region 24. The method for forming the source electrode 16 , the drain electrode 16 ′ and the body electrode 27 , such as but not limited to forming by photolithography process, ion implantation process, and thermal process, is well known to those skilled in the art, and will not be discussed here. Repeat.

The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The described embodiments are not limited to be applied individually, but can also be applied in combination. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, other process steps or structures, such as threshold voltage adjustment regions, can be added without affecting the main characteristics of the device. , high-voltage well region, or buried layer, etc.; another example, lithography technology is not limited to mask technology, but also includes electron beam lithography technology; another example, the form of buried columns is mainly in the form of long plates, and the arrangement is also It is mainly arranged in parallel, and can also have different shapes. As long as the buried column and the well region or the drift well region are reverse biased, a super junction is formed, which can improve the breakdown protection voltage; and the upper edge of the buried column and the semiconductor The upper surface of the substrate has a preset distance, so that when the high-voltage MOS element is turned on, the buried column does not significantly affect the current of the on-current on the upper surface. The scope of the present invention should cover the above and all other equivalent changes. The present invention has been described above with respect to the preferred embodiments, and the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes will occur to those skilled in the art.

Claims (6)

1. A high voltage metal oxide semiconductor device formed on a semiconductor substrate, wherein the semiconductor substrate has an upper surface and a lower surface opposite to each other in a longitudinal direction, the high voltage metal oxide semiconductor device comprising:

a well region of a first conductivity type formed below and connected to the upper surface in the longitudinal direction;

a drift region of a second conductivity type formed below and connected to the upper surface in the longitudinal direction, the drift region being completely located on the well region and connected to the well region in a lateral direction;

a gate formed on the upper surface in the longitudinal direction, wherein a portion of the gate is stacked and connected over a portion of the well region, and another portion of the gate is stacked and connected over a portion of the drift region;

a source electrode of the second conductivity type formed below and contacting the upper surface in the longitudinal direction and adjacent to the well region in the lateral direction, the source electrode being connected below a first side of the gate electrode;

a drain of the second conductivity type formed below and contacting the upper surface in the longitudinal direction and laterally adjacent to the drift region, separated from the source by the well region and the drift region, the drain being outside a second side of the gate and laterally opposite the source;

a plurality of buried pillars of the first conductivity type formed in the longitudinal direction a predetermined distance below the upper surface without contacting the upper surface, and the drift region surrounding at least a portion of each buried pillar such that the plurality of buried pillars and the drift region are staggered; and

a deep well region of the first conductivity type formed in the longitudinal direction under the well region and the drift region, the deep well region being connected to the plurality of buried pillars.

2. The MOS device of claim 1, wherein two adjacent buried pillars and the drift region in the gap therebetween are fully depleted in a non-conducting operation.

3. The MOS device of claim 1, wherein the predetermined distance d is greater than 0.1 μm.

4. A method for fabricating a high voltage MOS device, comprising:

providing a semiconductor substrate, which is provided with an upper surface and a lower surface opposite to each other in a longitudinal direction;

forming a well region under the upper surface and connected to the upper surface, the well region having a first conductivity type;

forming a drift region under the upper surface and connected to the upper surface, the drift region being completely over the well region, the drift region having a second conductivity type and being connected to the well region in a lateral direction;

forming a gate on the upper surface, wherein a part of the gate is stacked and connected to a part of the well region, and another part of the gate is stacked and connected to a part of the drift region;

forming a source electrode under and contacting the upper surface, the source electrode having the second conductivity type and being laterally adjacent to the well region, the source electrode being connected under the first side of the gate electrode;

forming a drain of the second conductivity type laterally adjacent to the drift region and separated from the source by the well region and the drift region, the drain being outside a second side of the gate and on a different side of the gate than the source in the lateral direction;

forming a plurality of buried pillars under a predetermined distance below the upper surface without contacting the upper surface, the buried pillars having the first conductivity type, and the drift region surrounding at least a portion of each buried pillar, such that the plurality of buried pillars and the drift region are staggered; and

forming a deep well region under the well region and the drift region, the deep well region having the first conductivity type and being connected to the plurality of buried pillars.

5. The method of claim 4, wherein two adjacent buried pillars and the drift region in the space between the two adjacent buried pillars are fully depleted during a non-conducting operation.

6. The method of claim 4, wherein the predetermined distance is greater than 0.1 μm.

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