CN109742151A - Thin film transistor and its manufacturing method, array substrate and display panel - Google Patents
Thin film transistor and its manufacturing method, array substrate and display panel Download PDFInfo
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- CN109742151A CN109742151A CN201811635291.6A CN201811635291A CN109742151A CN 109742151 A CN109742151 A CN 109742151A CN 201811635291 A CN201811635291 A CN 201811635291A CN 109742151 A CN109742151 A CN 109742151A
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- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 94
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 94
- 229910052738 indium Inorganic materials 0.000 claims abstract description 87
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 87
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims abstract description 70
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 70
- 239000011701 zinc Substances 0.000 claims abstract description 70
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000011787 zinc oxide Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 384
- 238000001039 wet etching Methods 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 8
- 239000012528 membrane Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 34
- 238000000034 method Methods 0.000 description 23
- 230000006378 damage Effects 0.000 description 21
- 208000027418 Wounds and injury Diseases 0.000 description 15
- 208000014674 injury Diseases 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000010408 film Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 229910052758 niobium Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
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- 239000000463 material Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000005229 chemical vapour deposition Methods 0.000 description 1
- QNDQILQPPKQROV-UHFFFAOYSA-N dizinc Chemical compound [Zn]=[Zn] QNDQILQPPKQROV-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
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Landscapes
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of thin film transistor and its manufacturing method, array substrate and display panel, thin film transistor (TFT) includes substrate, grid, gate insulating layer, active layer, source electrode and drain electrode, grid is arranged over the substrate, gate insulating layer is arranged in grid and substrate, active layer covering part gate insulating layer, source electrode and drain electrode is arranged on active layer and gate insulating layer, active layer includes the first active layer and the second active layer being stacked, second active layer is contacted with gate insulating layer, first active layer and the second active layer are indium gallium zinc oxide layer, and first indium in active layer, the element ratio of gallium and zinc is unequal, indium in first active layer, indium in the element ratio and the second active layer of gallium and zinc, gallium is different with the element ratio of zinc.The present invention can be improved the reliability of device.
Description
Technical field
The present invention relates to microelectronics technology more particularly to a kind of thin film transistor and its manufacturing methods, array substrate
And display panel.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) is the main drive in current liquid crystal display device
Dynamic element, is directly related to the developing direction of high performance flat display device.In order to realize that high-resolution is shown, TFT device ruler
It is very little to need to realize " miniaturization ", and realize that back channel etching (Back Channel Etching, abbreviation BCE) structure is TFT device
The key of part size " miniaturization ".In addition, the manufacture craft of BCE-TFT is simple, cost is relatively low.Importantly, its ditch track forces
Very little definition precision is high, " miniaturization " of device size easy to accomplish.
In the manufacturing process of existing BCE type thin film transistor (TFT), oxide semiconductor constitute active layer on and grid
Deposited metal film layer on the insulating layer of pole, after carrying out patterned etching to the metal film layer using dry etch process,
Source electrode, drain electrode and the channel between source electrode and drain electrode are obtained, i.e., oxide semiconductor is removed by dry etch process
The metallic diaphragm of layer upside, to produce channel structure.In the source electrode and the etching process of drain electrode, with etching into
Row, active layer are gradually exposed and directly directly contact with etch media.
In above-mentioned manufacturing process, since the oxide semiconductor surface layer under metallic diaphragm is directly contacted with etch media, because
This is easy to be damaged and generate by-product, unstable so as to cause oxide semiconductor reliability, so as to cause film crystal
Pipe reliability is low.
Summary of the invention
The present invention provides a kind of thin film transistor and its manufacturing method, array substrate and display panel, can be improved film
The reliability of transistor.
In a first aspect, the present invention provides a kind of thin film transistor (TFT), including substrate, grid, gate insulating layer, active layer, source
Pole and drain electrode, grid are arranged over the substrate, and gate insulating layer is arranged in grid and substrate, active layer covering part
Gate insulating layer, source electrode and drain electrode are arranged on active layer and gate insulating layer, and active layer includes first be stacked
Active layer and the second active layer, the second active layer are contacted with gate insulating layer, and the first active layer and the second active layer are indium gallium
Zinc oxide layer, and in the first active layer indium, gallium and zinc element ratio it is unequal, the member of indium, gallium and zinc in the first active layer
Plain ratio and indium, gallium in the second active layer are different with the element ratio of zinc.
Second aspect, the present invention provide a kind of array substrate, including above-mentioned thin film transistor (TFT).
The third aspect, the present invention provide a kind of display panel, including color membrane substrates, liquid crystal layer and above-mentioned array substrate,
Liquid crystal layer is folded between color membrane substrates and array substrate.
Fourth aspect, the present invention provide a kind of production method of thin film transistor (TFT), comprising: are sequentially depositing grid on substrate
And gate insulating layer；The second active layer and the first active layer are sequentially formed on gate insulating layer, the first active layer and second have
Active layer is indium gallium zinc oxide layer, and the first active layer and the second active layer collectively constitute active layer, wherein the first active layer
The element ratio of middle indium, gallium and zinc differs, indium, gallium in indium, the element ratio of gallium and zinc and the second active layer in the first active layer
It is different with the element ratio of zinc；Source electrode and drain electrode is formed on active layer and gate insulating layer.
Thin film transistor and its manufacturing method, array substrate and display panel of the invention, thin film transistor (TFT) include substrate,
Grid, gate insulating layer, active layer, source electrode and drain electrode, grid be arranged over the substrate, gate insulating layer setting grid with
And substrate, active layer covering part gate insulating layer, source electrode and drain electrode are arranged on active layer and gate insulating layer,
Active layer includes the first active layer and the second active layer being stacked, and the second active layer is contacted with gate insulating layer, and first has
Active layer and the second active layer are indium gallium zinc oxide layer, and in the first active layer indium, gallium and zinc element ratio it is unequal,
Indium, gallium are different with the element ratio of zinc in indium, gallium and the element ratio and the second active layer of zinc in one active layer.In this way,
Active layer is divided into the first active layer for bearing etching injury and below the first active layer, be not subject to the of etching injury
Two active layers.In this way, effective protection of second active layer by the first active layer, it is thus possible to improve thin film transistor (TFT)
Reliability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to make simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the structural schematic diagram for the thin film transistor (TFT) that the embodiment of the present invention one provides；
Fig. 2 is the bias test result schematic diagram for the thin film transistor (TFT) that the embodiment of the present invention one provides；
Fig. 3 is the flow diagram of the production method of thin film transistor (TFT) provided by Embodiment 2 of the present invention；
Fig. 4 a to Fig. 4 g is the detailed process schematic diagram of the production method of thin film transistor (TFT) provided by Embodiment 2 of the present invention.
Description of symbols:
10-thin film transistor (TFT)s；
20-substrates；
30-grids；
40-gate insulating layers；
50-active layers；
51-the first active layer；
52-the second active layer；
60-source electrodes；
70-drain electrodes；
80-passivation layers；
90-pixel electrodes；
91-through holes.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Embodiment one
Fig. 1 is the structural schematic diagram for the thin film transistor (TFT) that the embodiment of the present invention one provides.As shown in Figure 1, the present embodiment
Thin film transistor (TFT) 10 includes substrate 20, grid 30, gate insulating layer 40, active layer 50, source electrode 60 and drain electrode 70, and grid 30 is arranged
On substrate 20, gate insulating layer 40 is arranged on grid 30 and substrate 20,50 covering part gate insulating layer of active layer
40, source electrode 60 and drain electrode 70 are arranged on active layer 50 and gate insulating layer 40, and active layer 50 includes the be stacked
One active layer 51 and the second active layer 52, the second active layer 52 are contacted with gate insulating layer 40, and the first active layer 51 and second has
Active layer 52 is indium gallium zinc oxide layer, and in the first active layer 51 indium, gallium and zinc element ratio it is unequal, the first active layer
Indium, gallium are different with the element ratio of zinc in indium, gallium and the element ratio and the second active layer 52 of zinc in 51.
In the above technical solution, the active portion 50 between source electrode 60 and drain electrode 70 constitutes thin film transistor (TFT) 10
Groove.In addition, optional, 50 covering part gate insulating layer 40 of active layer refers specifically to active layer 50 and is located at and the grid 30
Corresponding position.
By setting this two layers of the first active layer 51 and the second active layer 52 for active layer 50, in the first active layer 51
The element ratio of indium, gallium and zinc is unequal, and indium, the element ratio of gallium and zinc and the second active layer 52 in the first active layer 51
Middle indium, gallium are different with the element ratio of zinc, active layer 50 can be divided to bear the first active layer 51 of etching injury and position
In 51 lower section of the first active layer, it is not subject to etch the second active layer 52 of injury.In this way, which the second active layer 52 is by first
The effective protection of active layer 51, it is thus possible to improve the reliability of thin film transistor (TFT).
Specifically, active layer in the prior art is indium gallium zinc oxide layer, indium gallium zinc oxide is as novel display
The features such as with material, with carrier mobility height, turn-off characteristic is good, easy to industrialized production, but with dry etching work
While skill makes source electrode and drain electrode, etch media inevitably influences the characteristic of indium gallium zinc oxide layer superficial layer,
The characteristic of indium gallium zinc oxide layer is set to change, so as to cause the bad stability of array substrate.
And in the present embodiment, the first active layer 51 is passing through etching removal first close to 70 setting of source electrode 60 and drain electrode
Metal above active layer 51 (groove above) and during forming source electrode 60 and drain electrode 70, due in the first active layer 51
The element ratio of indium, gallium and zinc is unequal, and the first active layer 51 being thusly-formed can resist the etch media in etching process
Erosion, to be formed as the protective layer of active layer 50, therefore in source electrode 60 and the etching process of drain electrode 70, active layer 50 is not
It will receive damage, guarantee that the performance of active layer 50 is stablized with this, to enough improve the reliability of thin film transistor (TFT).
Each layer of active layer 50 is advanced optimized, the element ratio of indium, gallium and zinc in the second active layer 52 can be made equal
Equal, i.e. the element ratio of indium, gallium and zinc is 1:1:1 in the second active layer 52, can guarantee the property of the second active layer 52 in this way
It can stablize.
In addition, optional, the element ratio of indium (Indium), gallium (Gallium) and zinc (Zinc) in the first active layer 51
For 1:(2~5): (2~8).That is, when the ratio of indium is set as 1, the composition of gallium and zinc meets: 2≤gallium≤5,2≤zinc≤
8.The erosion of the etch media in etching process can be effective against using the first active layer 51 of above-mentioned ratio of components, it is thus possible to
Damage of the etch media to active portion 50 is reduced, so as to promote the stability of thin film transistor (TFT) 10.
In addition, in this application, indium, element ratio, that is, indium of gallium and zinc, gallium and zinc atomic ratio or atomic molar ratio.Tool
Body, the element ratio of indium, gallium and zinc refers to the molar ratio of phosphide element, gallium element and Zn-ef ficiency, or refers to phosphide element, gallium member
The ratio of element and the Zn-ef ficiency respective shared mass percent in the first active layer or the second active layer.For example, first has
The element ratio of indium, gallium and zinc is 1:(2~5 in active layer 51): (2~8) refer specifically to phosphide element, gallium in the first active layer 51 of generation
The molar ratio of element and Zn-ef ficiency is 1:(2~5): (2~8), or reference phosphide element, gallium element and Zn-ef ficiency are active first
The ratio of mass percent respectively shared is 1:(2~5 in layer): (2~8).And in the second active layer 52 indium, gallium and zinc member
Plain ratio is 1:1:1, and the molar ratio for referring specifically to phosphide element, gallium element and Zn-ef ficiency in the second active layer 52 of generation is 1:1:1, or
The ratio for referring to phosphide element, gallium element and Zn-ef ficiency mass percent respectively shared in the second active layer 52 is 1:1:1.
In addition, as shown in Figure 1, the first active layer 51 is identical with the overlay area of the second active layer 52.In other words, it views from above
It goes the first active layer 51 identical with the shape size of the second active layer 52, can guarantee that the first active layer 51 covers all in this way
Two active layers 52 preferably protect the second active layer 52.Certainly, the invention is not limited thereto, and it is active to be also possible to first
The overlay area of layer 51 is greater than the overlay area of the second active layer 52, as long as the first active layer 51 can be played to the second active layer
52 protective effect.
In addition, optionally, above-mentioned substrate 20 can be glass substrate, also, grid 30, source electrode 60 and drain electrode 70 by
Metal is formed, grid 30, source electrode 60 and drain electrode 70 used in metal can in Cu, Al, Mo, Ti, Nb, Ag at least one
Kind.Certainly, for formed grid layer, source electrode, drain electrode metal, can be one of Cu, Al, Mo, Ti, Nb, Ag, can also be with
It is the combination of two or more in Cu, Al, Mo, Ti, Nb, Ag.In addition, the gate insulating layer 40 is silica
(SiOx) layer, silicon nitride (SiNx) layer or the composite layer formed is superimposed with silicon nitride layer by silicon oxide layer.
In order to be further reduced etching process to injury caused by active layer 50, can choose keeps source electrode 60 and drain electrode 70 logical
It crosses wet etching and is formed.The etching agent of dry etching is plasma, is reacted using plasma and active layer surface, shape
At volatile materials, or directly bombardment active layer surface is allowed to the technique being corroded, but in etching process, etch media holds
Easily the surface layer of active layer is caused to damage；Wet etching is will by the chemical reaction between chemical etching liquid and active layer surface
The lithographic method that the substance that is etched strips down, this method is adaptable, and surface uniformity is good, especially to active layer surface
It damages smaller.Thus will also it be done while being provided with protective layer of first active layer 51 as active layer 50 in the present embodiment
Method etching is changed to wet etching, can further decrease to damage caused by active layer 50.
Further, since source wiring, drain electrode distribution and source electrode 60 and drain electrode 70 are etched in same procedure and are formed, thus
Source wiring, drain electrode distribution are formed also by wet etching.
In addition, as shown in Figure 1, optionally, being also set up in gate insulating layer 40, active layer 50, source electrode 60 and drain electrode 70
There are passivation layer 80 and pixel electrode 90.Specifically, being formed in gate insulating layer 40, active layer 50, source electrode 60 and drain electrode 70 blunt
Change layer 80, corresponds at the position of drain electrode 70 on passivation layer 80 and be also formed with through hole 91, in addition, being formed on passivation layer 80
Pixel electrode 90, pixel electrode 90 are connect via through hole 91 with drain electrode 70.
Below in the present embodiment, the element ratio of indium, gallium and zinc is 1:(2~5 in the first active layer 51): (2~8),
The thin film transistor (TFT) 10 that the element ratio of indium, gallium and zinc is 1:1:1 in second active layer 52 carries out bias test.
Fig. 2 is the bias test result schematic diagram for the thin film transistor (TFT) that the embodiment of the present invention one provides, and table 1 is active layer point
It is not constituted by single layer in the prior art and by the first active layer 51 of above-mentioned specific composition ratio and the second active layer 52 (bilayer)
When threshold voltage shift numerical value.In Fig. 2, the longitudinal axis represents the threshold voltage shift amount (unit: V) of thin film transistor (TFT), has
The pattern of shade represents threshold voltage drift positive in positive bias humid test (Positive Bias Temperature, PBT)
It moves, and hollow pattern represents negative sense in negative temperature bias test (Light Negative Bias Temperature, PBT)
Threshold voltage shift.
Table one:
| Single layer threshold voltage shift (V) | The double-deck threshold voltage shift (V) | |
| Positive bias humid test | 2.48 | 1.26 |
| Negative temperature bias test | -6.46 | -3.31 |
When active layer 50 is become from single layer by the first active of above-mentioned specific composition ratio it can be seen from Fig. 2 and table one
When the bilayer that layer 51 and the second active layer 52 are constituted, threshold voltage shift has been reduced to 1.26V by 2.48V in forward direction, in negative sense,
The absolute value of threshold voltage shift has been reduced to 3.31V by 6.46V, it will thus be seen that when active layer 50 from single layer become by
When the bilayer that the first active layer 51 of above-mentioned specific composition ratio and the second active layer 52 are constituted, the threshold voltage drift of thin film transistor (TFT)
Shifting is obviously reduced, and the characteristic of the device being thus made of thin film transistor (TFT), such as liquid crystal display panel etc. can also obtain
To being obviously improved.
In addition, idea of the invention is that in the structure of BCE type thin film transistor (TFT), by the way that source electrode and drain electrode will be constituted
Between groove oxide semiconductor it is double-skinned, be respectively formed the first different active layer of element ratio of components and second active
Layer, the element ratio that the present embodiment enumerates indium, gallium and zinc in the first active layer is 1:(2~5): (2~8), in the second active layer
The element ratio of indium, gallium and zinc is illustrated for being 1:1:1, however, the present invention is not limited thereto, as long as indium in the first active layer,
Gallium and indium, gallium in the element ratio and the second active layer of zinc difference can reach the purpose of the application with the element ratio of zinc, i.e.,
Active layer is divided into the purpose born the first active layer of etching injury and be not subject to the second active layer of etching injury.
In the present embodiment, thin film transistor (TFT) includes substrate, grid, gate insulating layer, active layer, source electrode and drain electrode, grid
On substrate, gate insulating layer setting is in grid and substrate, active layer covering part gate insulating layer for setting, source electrode and
Drain electrode is arranged on active layer and gate insulating layer, and active layer includes that the first active layer being stacked and second are active
Layer, the second active layer contacts with gate insulating layer, and the first active layer and the second active layer are indium gallium zinc oxide layer, and first
The element ratio of indium, gallium and zinc is unequal in active layer, indium, the element ratio of gallium and zinc and the second active layer in the first active layer
Middle indium, gallium are different with the element ratio of zinc.In the present embodiment, by setting the first active layer and the second active layer for active layer
This two layers, the element ratio of indium, gallium and zinc is unequal in the first active layer, and in the first active layer indium, gallium and zinc element
Ratio and indium, gallium in the second active layer are different with the element ratio of zinc, active layer can be divided into and bear the first of etching injury
Active layer and below the first active layer, be not subject to the second active layer of etching injury.In this way, the second active layer by
To the effective protection of the first active layer, it is thus possible to improve the reliability of thin film transistor (TFT).
Embodiment two
The production method of thin film transistor (TFT) provided in this embodiment can be used to make film crystal described in embodiment one
Pipe 10.Wherein, the specific structure of thin film transistor (TFT) 10 and function have been described in detail in previous embodiment one, this
Place repeats no more.Fig. 3 is the flow diagram of the production method of thin film transistor (TFT) provided by Embodiment 2 of the present invention.Such as Fig. 3 institute
Show, the production method of thin film transistor (TFT) provided in this embodiment can specifically include following steps:
S11, it is sequentially depositing grid and gate insulating layer on substrate；
S12, the second active layer and the first active layer are sequentially formed on gate insulating layer；Wherein, the first active layer and
Two active layers are indium gallium zinc oxide layer, and the first active layer and the second active layer collectively constitute active layer, wherein first has
The element ratio of indium, gallium and zinc differs in active layer, in the first active layer in indium, the element ratio of gallium and zinc and the second active layer
Indium, gallium are different with the element ratio of zinc.
S13, source electrode and drain electrode is formed on active layer and gate insulating layer.
As previously described, because the first active layer is arranged close to source electrode and drain electrode, passing through the first active layer position of etching removal
Metal above groove and the element ratio of indium, gallium and zinc is not during forming source electrode and drain electrode, in the first active layer
It is equal, thus the erosion of the etch media in etching process can be resisted, therefore in the etching process of source electrode and drain electrode, it is active
Layer will not be damaged, and can guarantee that the performance of active layer is stablized, to enough improve the reliability of thin film transistor (TFT).
Optionally, source electrode and drain electrode is formed on active layer and gate insulating layer, specifically included: had using wet etching
Source electrode and drain electrode is formed on active layer and gate insulating layer.Compared with dry etching, wet etching can be further reduced etched
Journey is injured caused by active layer, therefore selection forms source electrode and drain electrode by wet etching.Due to source wiring, drain electrode
Wiring and source electrode and drain electrode etch formation in same procedure, thus source wiring, drain electrode distribution also by wet etching and
It is formed.
Enumerate a specific example below to illustrate the manufacturing process of the thin film transistor (TFT) of the present embodiment, Fig. 4 a to Fig. 4 g
For the detailed process schematic diagram of the production method of thin film transistor (TFT) provided by Embodiment 2 of the present invention.The production method includes such as
Lower step:
A) as shown in fig. 4 a, substrate 20 is provided, forms grid 30 on substrate 20.
Specifically, one layer of first metallic film is first deposited on substrate 20, using wet etching to first metal foil
After film is patterned processing, grid 30 is obtained.
B) as shown in Figure 4 b, gate insulating layer 40 is formed on substrate 20 and grid 30.
Specifically, gate insulating layer 40 is formed using chemical vapor deposition.
C) as illustrated in fig. 4 c, the second active layer 52 is formed on gate insulating layer 40；Wherein, the second active layer 52 is indium gallium
Zinc oxide layer, and the element ratio of indium, gallium and zinc is 1:1:1 in the second active layer 52.
D) as shown in figure 4d, the first active layer 51 is formed on the second active layer 52；Wherein, the first active layer 51 is also indium
Gallium zinc oxide layer, and the element ratio of indium, gallium and zinc is 1:(2~5 in the first active layer 51): (2~8).First active layer
51 and second active layer 52 collectively form active layer 50.
E) as shown in fig 4e, source electrode 60 and drain electrode are formed on active layer 50 (the first active layer 51) and gate insulating layer 40
70。
Specifically, one layer of second metallic film is deposited on first active layer 51 and gate insulating layer 40 in active layer 50,
After performing etching second metallic film using wet etching, obtain being located at the upper of active layer 50 and gate insulating layer 40
Source electrode 60 and drain electrode 70, while source electrode 60 and drain electrode 70 between active layer 50 be formed as groove.
F) as shown in fig. 4f, passivation layer 80 is formed on gate insulating layer 40, source electrode 60, drain electrode 70 and active layer 50, and
Position corresponding with drain electrode 70 forms through hole 91 on the passivation layer 80.
G) as shown in figure 4g, on passivation layer 80 formed pixel electrode 90, and pixel electrode 90 via through hole 91 with
70 connection of drain electrode.Specifically, the material of pixel electrode 90 can be tin indium oxide.
The element ratio of indium, gallium and zinc is 1:1:1 in second active layer 52, can guarantee the property of the second active layer 52 in this way
It can stablize.In addition, the element ratio of indium, gallium and zinc is 1:(2~5 in the first active layer 51): (2~8).Using above-mentioned ratio of components
The first active layer 51 can be effective against the erosion of the etch media in etching process, it is thus possible to reduce etch media to having
The damage in source portion 50, so as to promote the character constancy of thin film transistor (TFT) 10.
In the present embodiment, the element ratio for enumerating indium, gallium and zinc in the first active layer is 1:(2~5): (2~8),
The element ratio of indium, gallium and zinc is illustrated for being 1:1:1 in second active layer, however, the present invention is not limited thereto, as long as the
The element ratio of indium, gallium and zinc difference can reach originally in indium, gallium and the element ratio and the second active layer of zinc in one active layer
Active layer is divided into the first active layer for bearing etching injury and the second active layer for being not subject to etching injury by the purpose of application
Purpose.
In addition, optionally, above-mentioned substrate 20 can be glass substrate, also, grid 30, source electrode 60 and drain electrode 70 by
Metal is formed, grid 30, source electrode 60 and drain electrode 70 used in metal can in Cu, Al, Mo, Ti, Nb, Ag at least one
Kind.Certainly, for formed grid layer, source electrode, drain electrode metal, can be one of Cu, Al, Mo, Ti, Nb, Ag, can also be with
It is the combination of two or more in Cu, Al, Mo, Ti, Nb, Ag.In addition, the gate insulating layer 40 is silica
(SiOx) layer, silicon nitride (SiNx) layer or the composite layer formed is superimposed with silicon nitride layer by silicon oxide layer.
In the present embodiment, the production method of thin film transistor (TFT) includes: to be sequentially depositing grid and gate insulator on substrate
Layer；The second active layer and the first active layer are sequentially formed on gate insulating layer, the first active layer and the second active layer are indium
Gallium zinc oxide layer, and the first active layer and the second active layer collectively constitute active layer, wherein indium in the first active layer, gallium and
The element ratio of zinc differs, in the first active layer in indium, the element ratio of gallium and zinc and the second active layer indium, gallium and zinc element
Ratio is different；Source electrode and drain electrode is formed on active layer and the gate insulating layer.Since the first active layer is close to source electrode and leakage
Pole setting, during removing the first active layer by etching and being located at the metal above groove and form source electrode and drain electrode,
The element ratio of indium, gallium and zinc is unequal in first active layer, thus can resist the erosion of the etch media in etching process,
Therefore in the etching process of source electrode and drain electrode, active layer will not be damaged, and can guarantee that the performance of active layer is stablized, thus
Enough improve the reliability of thin film transistor (TFT).
Embodiment three
On the one hand the present embodiment provides a kind of array substrate comprising thin film transistor (TFT) 10 described in embodiment one, wherein
The specific structure and function of thin film transistor (TFT) 10 have been described in detail in previous embodiment one, thus herein no longer
It repeats.Also, the method that the production method of the array substrate is referred to embodiment two, which is not described herein again.
Array substrate provided in this embodiment is as setting for active layer in the thin film transistor (TFT) included by them
This two layers of one active layer and the second active layer, the element ratio of indium, gallium and zinc is unequal in the first active layer, and first is active
Indium, gallium and indium, gallium in the element ratio and the second active layer of zinc are different with the element ratio of zinc in layer, active layer can be divided into
Be able to bear the first active layer of etching injury and below the first active layer, be not subject to the second active of etching injury
Layer.In this way, effective protection of second active layer by the first active layer, it is thus possible to improve the reliable of thin film transistor (TFT)
Property, thus the reliability of array substrate provided by the present embodiment is higher.
Example IV
The present embodiment provides a kind of display panels, including array substrate described in embodiment three, wherein display panel can be with
For OLED display panel, or liquid crystal display panel, wherein when display panel is OLED display panel, array substrate
On also set up organic light-emitting units, when display panel is liquid crystal display panel, display panel further includes color membrane substrates, and array
Liquid crystal layer is set between substrate and color membrane substrates.
The another aspect of the present embodiment also provides a kind of display device, including above-mentioned display panel, and display device can be
Flexible display apparatus, wherein in the present embodiment, display device can be Electronic Paper, tablet computer, liquid crystal display, liquid crystal electricity
Depending on, any component having a display function such as Digital Frame, mobile phone.
Display panel provided in this embodiment and display device, as will have in the thin film transistor (TFT) included by them
Active layer is set as this two layers of the first active layer and the second active layer, and the element ratio of indium, gallium and zinc is unequal in the first active layer,
And the element ratio of indium in indium, gallium and the element ratio and the second active layer of zinc, gallium and zinc is different in the first active layer, can be with
Active layer is divided into the first active layer for being able to bear etching injury and below the first active layer, be not subject to etching injury
The second active layer.In this way, effective protection of second active layer by the first active layer, it is thus possible to improve film crystal
The reliability of pipe, thus the reliability of display panel and display device provided by the present embodiment is higher.
In the description of the present invention, it is to be understood that, term " on ", "lower", "front", "rear", "left", "right", " perpendicular
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "top", "bottom", "inner", "outside" is orientation based on the figure or position
Relationship is set, is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning are necessary
It with specific orientation, is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.
In addition, in the present invention unless specifically defined or limited otherwise, term " connection ", " connected ", " fixation ", " peace
Dress " etc. shall be understood in a broad sense, such as can be mechanical connection, be also possible to be electrically connected；It can be and be directly connected to, can also pass through
Intermediary is indirectly connected, and can be the connection inside two elements or the interaction relationship of two elements, unless otherwise bright
True restriction, for the ordinary skill in the art, can understand as the case may be above-mentioned term in the present invention
Concrete meaning.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of thin film transistor (TFT), which is characterized in that including substrate, grid, gate insulating layer, active layer, source electrode and drain electrode, institute
State grid setting over the substrate, gate insulating layer setting is described active in the grid and the substrate
Gate insulating layer described in layer covering part, the source electrode and the drain electrode are arranged at the active layer and the gate insulating layer
On, the active layer includes the first active layer and the second active layer being stacked, second active layer and the grid
Insulating layer contact, first active layer and second active layer are indium gallium zinc oxide layer, and first active layer
The element ratio of middle indium, gallium and zinc is unequal, indium in first active layer, the element ratio of gallium and zinc and described second active
Indium, gallium are different with the element ratio of zinc in layer.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the member of indium, gallium and zinc in second active layer
Plain ratio is equal.
3. thin film transistor (TFT) according to claim 1, which is characterized in that first active layer and second active layer
Overlay area it is identical.
4. thin film transistor (TFT) according to claim 1-3, which is characterized in that indium, gallium in first active layer
Element ratio with zinc is 1:(2~5): (2~8).
5. thin film transistor (TFT) according to claim 1-3, which is characterized in that the source electrode and the drain electrode pass through
Wet etching and formed.
6. thin film transistor (TFT) according to claim 1-3, which is characterized in that the gate insulating layer described has
Passivation layer and pixel electrode are additionally provided in active layer, the source electrode and the drain electrode.
7. a kind of array substrate, which is characterized in that including thin film transistor (TFT) described in any one of claims 1-6.
8. a kind of display panel, which is characterized in that including color membrane substrates, liquid crystal layer and array substrate as claimed in claim 7, institute
Liquid crystal layer is stated to be folded between the color membrane substrates and the array substrate.
9. a kind of production method of thin film transistor (TFT) characterized by comprising
It is sequentially depositing grid and gate insulating layer on substrate；
The second active layer and the first active layer, first active layer and described second are sequentially formed on the gate insulating layer
Active layer is indium gallium zinc oxide layer, and first active layer and second active layer collectively constitute active layer, wherein
The element ratio of indium, gallium and zinc differs in first active layer, indium in first active layer, gallium and zinc element ratio and
Indium, gallium are different with the element ratio of zinc in second active layer；
Source electrode and drain electrode is formed on the active layer and the gate insulating layer.
10. the production method of thin film transistor (TFT) according to claim 9, which is characterized in that it is described in the active layer and
Source electrode and drain electrode is formed on the gate insulating layer, is specifically included:
The source electrode and the drain electrode are formed on the active layer and the gate insulating layer using wet etching.
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| CN112802904A (en) * | 2020-12-29 | 2021-05-14 | 重庆先进光电显示技术研究院 | Manufacturing method of thin film transistor device, thin film transistor device and display device |
| CN112864231A (en) * | 2021-01-28 | 2021-05-28 | 合肥维信诺科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display panel |
| CN113764282A (en) * | 2021-09-03 | 2021-12-07 | 深圳市华星光电半导体显示技术有限公司 | A back channel etched thin film transistor and method of making the same |
| CN113838759A (en) * | 2021-07-29 | 2021-12-24 | 信利半导体有限公司 | Manufacturing method of thin film transistor, thin film transistor and electronic equipment |
| WO2023087347A1 (en) * | 2021-11-17 | 2023-05-25 | 惠州华星光电显示有限公司 | Display panel and manufacturing method therefor |
| WO2024244751A1 (en) * | 2023-05-31 | 2024-12-05 | 京东方科技集团股份有限公司 | Thin-film transistor and display substrate and fabrication methods therefor, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112802904A (en) * | 2020-12-29 | 2021-05-14 | 重庆先进光电显示技术研究院 | Manufacturing method of thin film transistor device, thin film transistor device and display device |
| CN112864231A (en) * | 2021-01-28 | 2021-05-28 | 合肥维信诺科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display panel |
| CN113838759A (en) * | 2021-07-29 | 2021-12-24 | 信利半导体有限公司 | Manufacturing method of thin film transistor, thin film transistor and electronic equipment |
| CN113764282A (en) * | 2021-09-03 | 2021-12-07 | 深圳市华星光电半导体显示技术有限公司 | A back channel etched thin film transistor and method of making the same |
| CN113764282B (en) * | 2021-09-03 | 2023-09-05 | 深圳市华星光电半导体显示技术有限公司 | A kind of back channel etching type thin film transistor and its manufacturing method |
| WO2023087347A1 (en) * | 2021-11-17 | 2023-05-25 | 惠州华星光电显示有限公司 | Display panel and manufacturing method therefor |
| WO2024244751A1 (en) * | 2023-05-31 | 2024-12-05 | 京东方科技集团股份有限公司 | Thin-film transistor and display substrate and fabrication methods therefor, and display device |
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| CN109742151B (en) | 2020-03-06 |
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