CN109727877A - A kind of method for packaging semiconductor and semiconductor packing device - Google Patents
A kind of method for packaging semiconductor and semiconductor packing device Download PDFInfo
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- CN109727877A CN109727877A CN201811565049.6A CN201811565049A CN109727877A CN 109727877 A CN109727877 A CN 109727877A CN 201811565049 A CN201811565049 A CN 201811565049A CN 109727877 A CN109727877 A CN 109727877A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000012856 packing Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000002390 adhesive tape Substances 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 4
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 2
- ZUPBPXNOBDEWQT-UHFFFAOYSA-N [Si].[Ni].[Cu] Chemical compound [Si].[Ni].[Cu] ZUPBPXNOBDEWQT-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- IYRDVAUFQZOLSB-UHFFFAOYSA-N copper iron Chemical compound [Fe].[Cu] IYRDVAUFQZOLSB-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 239000004484 Briquette Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229940114081 cinnamate Drugs 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- WBYWAXJHAXSJNI-VOTSOKGWSA-M trans-cinnamate Chemical compound [O-]C(=O)\C=C\C1=CC=CC=C1 WBYWAXJHAXSJNI-VOTSOKGWSA-M 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
This application discloses a kind of method for packaging semiconductor and semiconductor packing device, the method for packaging semiconductor includes: to form the first insulating layer in substrate/frame first surface, and form the first opening on the first insulating layer；Conducting connecting part is formed in first opening；Second insulating layer is formed far from the side of the substrate/frame in first insulating layer, and the second opening is formed in the position that the second insulating layer corresponds to first opening, and the height of the conducting connecting part is less than the sum of the depth of first opening with second opening；The metalwork of the front setting of chip is placed in second opening, and the front of the chip is bonded with the second insulating layer, the metalwork is electrically connected with the conducting connecting part.By the above-mentioned means, the application can keep chip surface exposed without grinding chip or in chip surface setting adhesive tape.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging device.
Background
Semiconductor packaging refers to the process of forming a chip, a substrate/frame, and a molding compound into packages of different shapes. In the packaging process, the chip is firstly fixed to the first surface of the substrate/frame, and then the first surface of the substrate/frame is covered with the molding compound and the chip is wrapped. In general, one side of a chip, which is far away from a substrate/frame, needs to be exposed from a molding compound, and in order to realize the exposure of the chip, a first mode is adopted, wherein before the molding compound is covered, an adhesive tape is arranged on one side of the chip, which is far away from the substrate/frame, in advance, and the exposure of the chip is realized by removing the adhesive tape at the later stage; the second way is to grind the side of the chip far from the substrate/frame after the molding compound is molded to realize the exposure of the chip.
In the long-term research process, the inventor of the present application finds that the first mode easily causes the plastic package material to overflow to the surface of the chip, and the second mode easily causes the over-grinding, so that the thickness of the chip is ground to be too thin.
Disclosure of Invention
The present application provides a semiconductor packaging method and a semiconductor packaging device, which can expose a chip surface without grinding the chip or disposing an adhesive tape on the chip surface.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor packaging method including: forming a first insulating layer on a first surface of a substrate/frame, and forming a first opening on the first insulating layer; forming a conductive connecting piece in the first opening; forming a second insulating layer on one side of the first insulating layer, which is far away from the substrate/frame, forming a second opening at the position, corresponding to the first opening, of the second insulating layer, wherein the height of the conductive connecting piece is smaller than the sum of the depths of the first opening and the second opening; and arranging a metal piece arranged on the front surface of the chip in the second opening, bonding the front surface of the chip with the second insulating layer, and electrically connecting the metal piece with the conductive connecting piece.
Wherein the forming of the conductive connection within the first opening comprises: and forming the conductive connecting piece in the first opening by utilizing an electroplating process, wherein the height of the conductive connecting piece is more than or equal to the depth of the first opening.
Wherein the semiconductor packaging method further comprises: and carrying out reflow treatment on the conductive connecting piece so that the conductive connecting piece is fixed with the substrate/frame, and an arc-shaped surface is formed on one side of the conductive connecting piece, which is far away from the substrate/frame.
Wherein the forming a first insulating layer on the first surface of the substrate/frame and forming a first opening on the first insulating layer comprises: forming a photoresist layer on the first surface of the substrate/frame; and exposing and developing the photoresist layer by using a photomask to form the first opening.
Wherein, the forming a second insulating layer on one side of the first insulating layer far away from the substrate/frame, and forming a second opening on the second insulating layer corresponding to the first opening, includes: forming a welding-proof ink layer on one side of the first insulating layer, which is far away from the substrate/frame; and corroding the welding-proof ink layer to form the second opening at the position corresponding to the first opening.
Wherein, the metalwork that sets up the front of chip is placed in the second opening, includes: placing the metal piece of the chip in the second opening, wherein the front surface of the chip is in contact with the second insulating layer, and a first distance is formed between the metal piece and the conductive connecting piece and is greater than or equal to 0; or the metal piece of the chip is placed in the second opening, the metal piece is in contact with the conductive connecting piece, a second distance is formed between the front surface of the chip and the second insulating layer, and the second distance is larger than or equal to 0.
After the metal piece arranged on the front surface of the chip is placed in the second opening, the method further comprises the following steps: the back of the chip is provided with a pressing block, the chip and the substrate/frame are subjected to backflow treatment, the first insulating layer and/or the second insulating layer deform under the action of the pressing block and the temperature, so that the front of the chip is bonded with the second insulating layer, and the metal piece is electrically connected with the conductive connecting piece.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a semiconductor package device including: a substrate/frame; the first insulating layer is positioned on the first surface of the substrate/frame and is provided with a plurality of first openings; the second insulating layer is positioned on one side, away from the substrate/frame, of the first insulating layer, and a second opening is formed in the position, corresponding to the first opening, of the second insulating layer; the conductive connecting piece is positioned in the first opening, and the height of the conductive connecting piece is smaller than the sum of the depths of the first opening and the second opening; the chip comprises a front surface and a back surface, the front surface of the chip is bonded with the second insulating layer, a metal piece is arranged on the front surface of the chip, and the metal piece is electrically connected with the conductive connecting piece.
Wherein the height of the conductive connecting piece is greater than or equal to the depth of the first opening.
Wherein the first insulating layer is a photoresist layer; or, the second insulating layer is a solder mask ink layer.
The beneficial effect of this application is: in contrast to the prior art, the semiconductor packaging method provided by the present application includes: the first surface of the substrate/frame is provided with a first opening, the second surface of the substrate/frame is provided with a second opening corresponding to the first opening, the conductive connecting piece is formed in the first opening and does not protrude out of the second opening, the metal piece arranged on the front surface of the chip is arranged in the second opening, the front surface of the chip is bonded with the second insulating layer, and the metal piece is electrically connected with the conductive connecting piece. In the application, the first insulating layer and the second insulating layer are equivalent to plastic package layers and are formed before the chip and the first surface of the substrate/frame are fixed, so that the purpose of exposing the chip without arranging an adhesive tape on the back surface of the chip or grinding the back surface of the chip can be realized, and the semiconductor packaging method provided by the application is simpler and easier to implement.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a semiconductor packaging method according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to steps S101-S104 in FIG. 1;
FIG. 3 is a schematic flowchart illustrating an embodiment of step S101 in FIG. 1;
FIG. 4 is a schematic structural diagram of an embodiment corresponding to steps S201 to S202 in FIG. 3;
FIG. 5 is a schematic flow chart illustrating an embodiment of step S103 in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment corresponding to steps S301 to S302 in FIG. 5;
FIG. 7 is a schematic structural diagram of another embodiment corresponding to step S104 in FIG. 1;
FIG. 8 is a schematic structural diagram of another embodiment corresponding to step S104 in FIG. 1;
fig. 9 is a schematic structural diagram of an embodiment of a semiconductor package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1-2, fig. 1 is a schematic flow chart diagram illustrating an embodiment of a semiconductor packaging method of the present application, and fig. 2 is a schematic structural diagram illustrating an embodiment corresponding to steps S101-S104 in fig. 1, where the semiconductor packaging method includes:
s101: a first insulating layer 12 is formed on the first surface 100 of the substrate/frame 10, and a first opening 120 is formed on the first insulating layer 12.
Specifically, referring to fig. 2a, the substrate/frame 10 may be any type known in the art, such as a Printed Circuit Board (PCB), an organic substrate, an inorganic substrate, a glass substrate, a flexible substrate, a copper-iron-based frame, a copper-nickel-silicon-based frame, and the like. In this embodiment, the first surface 100 of the substrate/frame 10 is further provided with a plurality of leads 102, and the plurality of leads 102 are used for electrically connecting with other components.
In one embodiment, the first insulating layer 12 is a photoresist layer, please refer to fig. 3-4, fig. 3 is a flowchart illustrating an embodiment of step S101 in fig. 1, and fig. 4 is a structural diagram illustrating an embodiment corresponding to step S201-step S202 in fig. 3. The step S101 specifically includes:
s201: a photoresist layer is formed on the first surface 100 of the substrate/frame 10.
Specifically, as shown in fig. 4a, a photoresist layer may be formed on the first surface 100 of the substrate/frame 10 by printing, using a device including a screen 14 and a doctor blade 16; in the embodiment, the photoresist layer is formed by printing, so that the efficiency is high. Of course, in other embodiments, other coating methods may be used to form the photoresist layer.
S202: the photoresist layer is exposed and developed by using the mask 18 to form a first opening 120.
Specifically, in one embodiment, as shown in fig. 4b, a mask 18 may be first placed on the photoresist layer 12, the mask 18 may also be referred to as a photomask, and the like, a plurality of third openings are pre-formed in the mask 18, and the photoresist layer corresponding to the third openings or the photoresist layer covered by the mask 18 except for the third openings is removed by exposure and development. For example, when the material of the photoresist layer is a positive photoresist (e.g., an o-azidoquinone type photoresist, etc.), the positive photoresist corresponding to the third opening is removed by exposure and development, and the other positive photoresist covered by the mask 18 remains; when the material of the photoresist layer is a negative photoresist (e.g., a photoresist of the cinnamate type, etc.), the negative photoresist corresponding to the third opening remains after exposure and development, and the other negative photoresist covered by the mask 18 is removed.
S102: the conductive connection member 11 is formed within the first opening 120.
Specifically, as shown in fig. 2b, the conductive connection member 11 may be formed in the first opening 120 by using an electroplating process, and the height of the conductive connection member 11 is greater than or equal to the depth of the first opening 120, and the conductive connection member 11 may be made of copper-tin-silver alloy or the like. In addition, in the embodiment, before the conductive connection member 11 is formed, a metal layer may be sputtered in the first opening 120, so that it is easier to form the conductive connection member 11 by subsequent electroplating.
In addition, in this embodiment, in order to make the connection between the conductive connecting member 11 and the substrate/frame 10 more tight, the semiconductor packaging method provided in this application further includes: the conductive connection member 11 is subjected to a reflow process so that the conductive connection member 11 is fixed with the substrate/frame 10 and the side of the conductive connection member 11 away from the substrate/frame 10 forms an arc-shaped surface (as shown in fig. 2 b).
S103: the second insulating layer 13 is formed on the side of the first insulating layer 12 away from the substrate/frame 10, the second opening 130 is formed at a position of the second insulating layer 13 corresponding to the first opening 120, and the height d1 of the conductive connecting member 11 is smaller than the sum d2 of the depths of the first opening 120 and the second opening 130.
In particular, as shown in fig. 2 c. In one embodiment, the second insulating layer 13 may be a photoresist layer similar to the first insulating layer 12, and may be formed in a manner similar to the first insulating layer 12, for example, a photoresist layer may be formed on the first insulating layer 12 by printing; the photoresist layer is then exposed and developed by using a photomask to form the second opening 130. Specifically, similar to the above steps S201 to S202, the description is omitted here.
In another embodiment, the second insulating layer 13 may also be a solder resist ink layer, the solder resist ink layer may be made of green paint ink, and the solder resist ink layer is softer and is more easily compressed and deformed by heat than the photoresist. Referring to fig. 5 and fig. 6, fig. 5 is a schematic flowchart illustrating an embodiment of step S103 in fig. 1, fig. 6 is a schematic structural diagram illustrating an embodiment corresponding to steps S301 to S302 in fig. 5, where the step S103 specifically includes:
s301: a solder mask ink layer is formed on the side of the first insulating layer 12 away from the substrate/frame 10.
Specifically, as shown in fig. 6a, a solder mask ink layer may be formed on the side of the first insulating layer 12 away from the substrate/frame 10 by printing, and the device used includes a screen 14 and a scraper 16; of course, in other embodiments, other coating methods may be used to form the solder resist ink layer.
S302: the solder resist layer is etched to form a second opening 130 at a position corresponding to the first opening 120. Specifically, as shown in fig. 6b, a glue film 15 may be attached on the solder mask ink layer, and a fourth opening 150 is exposed on the glue film 15 corresponding to the first opening 120; then, corroding the position corresponding to the fourth opening 150 by using corrosive liquid to corrode the anti-welding ink layer corresponding to the fourth opening 150; finally, the adhesive film 15 is removed.
S104: the metal member 172 disposed on the front surface 170 of the chip 17 is disposed in the second opening 130, and the front surface 170 of the chip 17 is bonded to the second insulating layer 13, and the metal member 172 is electrically connected to the conductive connecting member 11.
Specifically, as shown in fig. 2d, before the step S104, the method provided by the present application further includes: a metal member 172 is disposed at a position where a pad (not shown) is disposed on the front surface 170 of the chip 17, the metal member 172 may be a metal bump, and the metal bump may be made of gold, tin, or the like, and has a thickness smaller than 30um and larger than 10um, for example, a thickness of 25um, 20um, 15um, or the like. When the metal member 172 disposed on the front surface 170 of the chip 17 is disposed in the second opening 130, as shown in fig. 2d, the front surface 170 of the chip 17 contacts the second insulating layer 13, and the metal member 172 contacts the conductive connection member 11, and the first distance between the metal member 172 and the conductive connection member 11 is 0, that is, the sum of the height d3 of the metal member 172 of the chip 17 and the height d1 of the conductive connection member 11 is equal to the sum d2 of the depths of the first opening 120 and the second opening 130.
As shown in fig. 2e, after the metal member 172 disposed on the front surface 170 of the chip 17 is disposed in the second opening 130, in order to bond the front surface 170 of the chip 17 to the second insulating layer 13 and ensure that there is no gap between the front surface 170 of the chip 17 and the second insulating layer 13, the method provided in the present application further includes: a pressing block 19 is arranged on the back surface 174 of the chip 17, the chip 17 and the substrate/frame 10 are subjected to reflow treatment, the first insulating layer 12 and/or the second insulating layer 13 are deformed under the action of the pressing block 19 and temperature, so that the front surface 170 of the chip 17 is bonded with the second insulating layer 13, and the metal piece 172 is electrically connected with the conductive connecting piece 11. Further, in the present embodiment, before the briquette 19 is provided, the chip 17 may be integrally preheated with the substrate/frame 10 to preliminarily fix the chip 17 with the substrate/frame 10.
In another embodiment, as shown in fig. 7, fig. 7 is a schematic structural diagram of another embodiment corresponding to step S104 in fig. 1; the metal member 172a of the chip 17a is placed in the second opening (not labeled), the front surface 170a of the chip 17a contacts the second insulating layer 13a, and a first distance is formed between the metal member 172a and the conductive connecting member 11a, and the first distance is greater than 0. In order to make the metal member 172a contact with the conductive connecting member 11a, as shown in the above embodiment, a pressing block is introduced, the first insulating layer 12a and the second insulating layer 13a are subjected to compression deformation under the action of the pressing block and temperature, the chip 17a moves towards the substrate 10a, and the metal member 172a of the chip 17a is electrically connected with the conductive connecting member 11 a.
In another embodiment, as shown in fig. 8, fig. 8 is a schematic structural diagram of another embodiment corresponding to step S104 in fig. 1; the metal member 172b of the chip 17b is placed in the second opening (not labeled), the metal member 172b contacts the conductive connecting member 11b, and the front surface 170b of the chip 17b has a second distance with the second insulating layer 13b, and the second distance is greater than 0. In order to avoid a gap between the front surface 170b of the chip 17b and the second insulating layer 13b, a pressing block may be introduced as shown in the above embodiment, and the first insulating layer 12b, the second insulating layer 13b, and the conductive connecting member 11b are compressively deformed under the temperature and pressure, so that the chip 17b moves toward the substrate/frame 10b, and the front surface 170b of the chip 17b is in contact with the second insulating layer 13 b.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a semiconductor package device of the present application, the semiconductor package device 1 provided by the present application includes:
a substrate/frame 10; in the present embodiment, the substrate/frame 10 may be any type of the related art, for example, a Printed Circuit Board (PCB), an organic substrate, an inorganic substrate, a glass substrate, a flexible substrate, a copper-iron-based frame, a copper-nickel-silicon-based frame, and the like. In addition, in the present embodiment, the first surface 100 of the substrate/frame 10 is further provided with a plurality of pins 102, and the plurality of pins 102 are used for electrically connecting with other components. .
A first insulating layer 12 disposed on the first surface 100 of the substrate/frame 10, wherein the first insulating layer 12 is provided with a plurality of first openings (not shown); in this embodiment, the first insulating layer 12 is a photoresist layer, and the material of the photoresist layer may be a positive photoresist or a negative photoresist, which is not limited in this application.
A second insulating layer 13, located on a side of the first insulating layer 12 away from the substrate/frame 10, and a second opening (not labeled) is disposed at a position of the second insulating layer 13 corresponding to the first opening; in this embodiment, the second insulating layer 13 may be a photoresist layer, and the material of the photoresist layer may be a positive photoresist or a negative photoresist; of course, the second insulating layer 13 may also be a solder mask ink layer, and the solder mask ink layer may be made of green paint ink or the like.
The conductive connecting piece 11 is positioned in the first opening, and the height d1 of the conductive connecting piece 11 is less than the sum d2 of the depths of the first opening and the second opening; the conductive connecting member 11 may be made of copper-tin-silver alloy.
The chip 17 comprises a front surface 170 and a back surface 174, the front surface 170 of the chip 17 is adhered to the second insulating layer 13, the front surface 170 of the chip 17 is provided with a metal piece 172, and the metal piece 172 is electrically connected with the conductive connecting member 11. The metal member 172 may be a metal bump, and the material of the metal bump may be gold, tin, or the like.
In summary, unlike the state of the art, the semiconductor packaging method provided by the present application includes: the first surface of the substrate/frame is provided with a first opening, the second surface of the substrate/frame is provided with a second opening corresponding to the first opening, the conductive connecting piece is formed in the first opening and does not protrude out of the second opening, the metal piece arranged on the front surface of the chip is arranged in the second opening, the front surface of the chip is bonded with the second insulating layer, and the metal piece is electrically connected with the conductive connecting piece. In the application, the first insulating layer and the second insulating layer are equivalent to plastic package layers and are formed before the chip and the first surface of the substrate/frame are fixed, so that the purpose of exposing the chip without arranging an adhesive tape on the back surface of the chip or grinding the back surface of the chip can be realized, and the semiconductor packaging method provided by the application is simpler and easier to implement.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:
forming a first insulating layer on a first surface of a substrate/frame, and forming a first opening on the first insulating layer;
forming a conductive connecting piece in the first opening;
forming a second insulating layer on one side of the first insulating layer, which is far away from the substrate/frame, forming a second opening at the position, corresponding to the first opening, of the second insulating layer, wherein the height of the conductive connecting piece is smaller than the sum of the depths of the first opening and the second opening;
and arranging a metal piece arranged on the front surface of the chip in the second opening, bonding the front surface of the chip with the second insulating layer, and electrically connecting the metal piece with the conductive connecting piece.
2. The semiconductor packaging method of claim 1, wherein the forming of the conductive connection within the first opening comprises:
and forming the conductive connecting piece in the first opening by utilizing an electroplating process, wherein the height of the conductive connecting piece is more than or equal to the depth of the first opening.
3. The semiconductor packaging method according to claim 2, further comprising:
and carrying out reflow treatment on the conductive connecting piece so that the conductive connecting piece is fixed with the substrate/frame, and an arc-shaped surface is formed on one side of the conductive connecting piece, which is far away from the substrate/frame.
4. The semiconductor packaging method of claim 1, wherein the forming a first insulating layer on the first surface of the substrate/frame and forming a first opening on the first insulating layer comprises:
forming a photoresist layer on the first surface of the substrate/frame;
and exposing and developing the photoresist layer by using a photomask to form the first opening.
5. The semiconductor packaging method according to claim 1, wherein the forming a second insulating layer on a side of the first insulating layer away from the substrate/frame and forming a second opening in a position of the second insulating layer corresponding to the first opening comprises:
forming a welding-proof ink layer on one side of the first insulating layer, which is far away from the substrate/frame;
and corroding the welding-proof ink layer to form the second opening at the position corresponding to the first opening.
6. The semiconductor packaging method according to claim 1, wherein the placing of the metal piece disposed on the front surface of the chip in the second opening comprises:
placing the metal piece of the chip in the second opening, wherein the front surface of the chip is in contact with the second insulating layer, and a first distance is formed between the metal piece and the conductive connecting piece and is greater than or equal to 0; or,
and placing the metal piece of the chip in the second opening, wherein the metal piece is contacted with the conductive connecting piece, a second distance is formed between the front surface of the chip and the second insulating layer, and the second distance is greater than or equal to 0.
7. The semiconductor packaging method according to claim 6, wherein after the metal piece disposed on the front surface of the chip is placed in the second opening, the method further comprises:
the back of the chip is provided with a pressing block, the chip and the substrate/frame are subjected to backflow treatment, the first insulating layer and/or the second insulating layer deform under the action of the pressing block and the temperature, so that the front of the chip is bonded with the second insulating layer, and the metal piece is electrically connected with the conductive connecting piece.
8. A semiconductor package device, comprising:
a substrate/frame;
the first insulating layer is positioned on the first surface of the substrate/frame and is provided with a plurality of first openings;
the second insulating layer is positioned on one side, away from the substrate/frame, of the first insulating layer, and a second opening is formed in the position, corresponding to the first opening, of the second insulating layer;
the conductive connecting piece is positioned in the first opening, and the height of the conductive connecting piece is smaller than the sum of the depths of the first opening and the second opening;
the chip comprises a front surface and a back surface, the front surface of the chip is bonded with the second insulating layer, a metal piece is arranged on the front surface of the chip, and the metal piece is electrically connected with the conductive connecting piece.
9. The semiconductor package device of claim 8, wherein a height of the conductive connection is equal to or greater than a depth of the first opening.
10. The semiconductor package device of claim 8,
the first insulating layer is a photoresist layer; or, the second insulating layer is a solder mask ink layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565049.6A CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565049.6A CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
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| CN109727877A true CN109727877A (en) | 2019-05-07 |
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| CN201811565049.6A Pending CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499589A (en) * | 2002-11-04 | 2004-05-26 | 矽统科技股份有限公司 | Flip chip package process and device thereof |
| CN102136434A (en) * | 2010-01-27 | 2011-07-27 | 马维尔国际贸易有限公司 | Method of stacking flip-chip on wire-bonded chip |
| CN103972197A (en) * | 2013-01-24 | 2014-08-06 | 富士通半导体股份有限公司 | Semiconductor device, method for fabricating the same, lead and method for producing the same |
| CN108198794A (en) * | 2017-12-29 | 2018-06-22 | 通富微电子股份有限公司 | A kind of chip packing-body and preparation method thereof |
-
2018
- 2018-12-20 CN CN201811565049.6A patent/CN109727877A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499589A (en) * | 2002-11-04 | 2004-05-26 | 矽统科技股份有限公司 | Flip chip package process and device thereof |
| CN102136434A (en) * | 2010-01-27 | 2011-07-27 | 马维尔国际贸易有限公司 | Method of stacking flip-chip on wire-bonded chip |
| CN103972197A (en) * | 2013-01-24 | 2014-08-06 | 富士通半导体股份有限公司 | Semiconductor device, method for fabricating the same, lead and method for producing the same |
| CN108198794A (en) * | 2017-12-29 | 2018-06-22 | 通富微电子股份有限公司 | A kind of chip packing-body and preparation method thereof |
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Application publication date: 20190507 |