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CN109673079B - Silicon controlled rectifier dimming active bleeder control circuit - Google Patents

Silicon controlled rectifier dimming active bleeder control circuit Download PDF

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CN109673079B
CN109673079B CN201811557333.9A CN201811557333A CN109673079B CN 109673079 B CN109673079 B CN 109673079B CN 201811557333 A CN201811557333 A CN 201811557333A CN 109673079 B CN109673079 B CN 109673079B
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conversion circuit
resistor
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CN109673079A (en
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陶冬毅
刘明龙
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Ningbo Corelead Optoelectronics Technology Co ltd
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Ningbo Corelead Optoelectronics Technology Co ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30Driver circuits
    • H05B45/37Converter circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00Circuit arrangements for operating light-emitting diodes [LED]

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  • Circuit Arrangement For Electric Light Sources In General (AREA)

Abstract

The invention discloses a silicon controlled rectifier dimming active bleeder control circuit which comprises an edge detection circuit unit, a shaping and analog-digital conversion circuit unit, a digital control circuit unit, a digital-analog conversion circuit unit, a digital-to-analog conversion circuit unit, a V-I conversion and active bleeder circuit unit, wherein the edge detection circuit unit is used for detecting the upper/lower edges of bus voltage when the silicon controlled rectifier is conducted to output differential signals, the shaping and analog-digital conversion circuit unit is used for converting the differential signals into digital signals, the digital control circuit unit is used for generating time and amplitude control signals required by a corresponding bleeder circuit according to the digital signals, the digital-analog conversion circuit unit is used for selecting corresponding control level signals at corresponding time according to the time and the amplitude control signals, the V-I conversion and active bleeder circuit unit is used for outputting active bleeder current signals controlled by the control level signals, and the edge detection circuit unit, the V-I conversion and the active bleeder circuit unit are all connected with a bus port after rectification. The invention realizes the time and amplitude control of the bleeder current by using the digital-analog hybrid circuit, does not need the locking current and the locking transition time generated by the RC edge detection circuit, and improves the integration degree of the system.

Description

一种可控硅调光主动泄放控制电路A thyristor dimming active discharge control circuit

技术领域Technical Field

本发明涉及可控硅调光技术领域,特别涉及一种可控硅调光主动泄放控制电路。The present invention relates to the technical field of thyristor dimming, and in particular to a thyristor dimming active discharge control circuit.

背景技术Background technique

LED作为一种高效的新光源,由于具有寿命长,能耗低,节能环保,正广泛应用于各领域照明。LED的可调光技术随之发展得日益成熟,而可控硅调光是目前最常用的调光技术,其调光成本低,与现有线路兼容,无需重新布线。当灯具需要通过可控硅信号来调光时,电路中输入电压的波形因可控硅导通角度变化而偏离正弦波,也就改变了输入电压的有效值,从而实现调光。As a new and efficient light source, LED is widely used in lighting in various fields due to its long life, low energy consumption, energy saving and environmental protection. LED dimmable technology has become increasingly mature, and thyristor dimming is the most commonly used dimming technology at present. Its dimming cost is low, it is compatible with existing lines, and no rewiring is required. When the lamp needs to be dimmed by thyristor signal, the waveform of the input voltage in the circuit deviates from the sine wave due to the change of the thyristor conduction angle, which changes the effective value of the input voltage, thereby achieving dimming.

但是可控硅调光破坏了电压正弦波的波形,从而降低了功率因素值,非正弦波形加大了谐波系数,还会产生严重的干扰信号。尤其是在低负载时调光线路非常不稳定,因此需要对可控硅调光的泄放电流进行控制。However, thyristor dimming destroys the waveform of the voltage sine wave, thereby reducing the power factor value. The non-sinusoidal waveform increases the harmonic coefficient and also generates serious interference signals. Especially at low load, the dimming circuit is very unstable, so it is necessary to control the discharge current of thyristor dimming.

现有技术如图1所示,利用独立的RC线路产生可控硅导通锁定及过渡电流,用独立的恒流电路产生可控硅保持电流,但是由于锁定电流需求较大,锁定时间及过渡时间又较长,因此,对外置的RC线路的大电阻值和大电容值都提出了较高的要求,使得外置RC线路体积较大的同时成本较高,无法系统集成,不利于驱动器的小型化发展。As shown in FIG. 1 , the prior art utilizes an independent RC circuit to generate the thyristor conduction locking and transition current, and utilizes an independent constant current circuit to generate the thyristor holding current. However, due to the large locking current requirement, the locking time and transition time are relatively long, and therefore, high requirements are placed on the large resistance and capacitance values of the external RC circuit, which makes the external RC circuit larger in size and more expensive, making it impossible to integrate the system, which is not conducive to the miniaturization of the driver.

发明内容Summary of the invention

为了克服现有技术存在的不足,本发明提供了一种可控硅调光主动泄放控制电路,不需要RC边沿检测电路产生锁定电流和锁定过渡时间,有利于系统集成,降低整体解决方案的体积和成本,所述技术方案如下:In order to overcome the shortcomings of the prior art, the present invention provides a thyristor dimming active discharge control circuit, which does not require an RC edge detection circuit to generate a locking current and a locking transition time, is conducive to system integration, and reduces the volume and cost of the overall solution. The technical solution is as follows:

本发明提供了一种可控硅调光主动泄放控制电路,包括边沿检测电路单元、整形及模数转换电路单元、数字控制电路单元、数模转换电路单元及V-I转换及主动泄放电路单元,所述边沿检测电路单元、V-I转换及主动泄放电路单元均与整流后的母线电压端口连接;The present invention provides a thyristor dimming active discharge control circuit, comprising an edge detection circuit unit, a shaping and analog-to-digital conversion circuit unit, a digital control circuit unit, a digital-to-analog conversion circuit unit, and a V-I conversion and active discharge circuit unit, wherein the edge detection circuit unit, the V-I conversion and active discharge circuit unit are all connected to a rectified bus voltage port;

所述边沿检测电路单元用于检测可控硅导通时母线电压的上升沿或下降沿,以输出微分信号,所述边沿检测电路单元的输出端与整形及模数转换电路单元的输入端连接;The edge detection circuit unit is used to detect the rising edge or falling edge of the bus voltage when the thyristor is turned on to output a differential signal, and the output end of the edge detection circuit unit is connected to the input end of the shaping and analog-to-digital conversion circuit unit;

所述整形及模数转换电路单元将所述微分信号转换为数字信号,所述整形及模数转换电路单元的输出端与数字控制电路单元的输入端连接;The shaping and analog-to-digital conversion circuit unit converts the differential signal into a digital signal, and the output end of the shaping and analog-to-digital conversion circuit unit is connected to the input end of the digital control circuit unit;

所述数字控制电路单元根据所述数字信号产生相应泄放电路所需时序和幅度控制信号,所述数字控制电路单元的输出端与数模转换电路单元的输入端连接;The digital control circuit unit generates a timing and amplitude control signal required by a corresponding discharge circuit according to the digital signal, and the output end of the digital control circuit unit is connected to the input end of the digital-to-analog conversion circuit unit;

所述数模转换电路单元根据所述时序和幅度控制信号在相应的时间选择相应的控制电平信号,所述数模转换电路单元的输出端与V-I转换及主动泄放电路单元的输入端连接;The digital-to-analog conversion circuit unit selects a corresponding control level signal at a corresponding time according to the timing and amplitude control signal, and the output end of the digital-to-analog conversion circuit unit is connected to the input end of the V-I conversion and active discharge circuit unit;

所述V-I转换及主动泄放电路单元输出受所述控制电平信号控制的主动泄放电流信号。The V-I conversion and active discharge circuit unit outputs an active discharge current signal controlled by the control level signal.

优选地,所述V-I转换及主动泄放电路单元包括放大器、第一功率晶体管和泄放电阻,所述放大器的同向输入端与所述数模转换电路单元的输出端连接,所述放大器的输出端与所述第一功率晶体管的栅极连接,所述第一功率晶体管的漏极与所述整流后的母线电压端口连接,所述放大器的反向输入端、第一功率晶体管的源极均与所述泄放电阻的一端连接,所述泄放电阻的另一端接地。Preferably, the V-I conversion and active discharge circuit unit includes an amplifier, a first power transistor and a discharge resistor, the same-direction input terminal of the amplifier is connected to the output terminal of the digital-to-analog conversion circuit unit, the output terminal of the amplifier is connected to the gate of the first power transistor, the drain of the first power transistor is connected to the rectified bus voltage port, the reverse input terminal of the amplifier and the source of the first power transistor are both connected to one end of the discharge resistor, and the other end of the discharge resistor is grounded.

可选地,所述V-I转换及主动泄放电路单元包括第二功率晶体管,所述第二功率晶体管的栅极与所述数模转换电路单元的输出端连接,所述第二功率晶体管的漏极与所述整流后的母线电压端口连接,所述第二功率晶体管的源极接地。Optionally, the V-I conversion and active discharge circuit unit includes a second power transistor, a gate of the second power transistor is connected to the output end of the digital-to-analog conversion circuit unit, a drain of the second power transistor is connected to the rectified bus voltage port, and a source of the second power transistor is grounded.

优选地,所述边沿检测电路单元包括JFET晶体管、第一电容、第一电阻和第二电阻,所述JFET晶体管的栅极接地,所述JFET晶体管的漏极与所述整流后的母线电压端口连接,所述JFET晶体管的源极与第一电容、第一电阻顺序连接,所述第一电阻的下端接地;所述第二电阻的上端接入偏置电压,所述第二电阻的下端同时与第一电容、第一电阻之间的连接点及所述整形及模数转换电路单元的输入端连接。Preferably, the edge detection circuit unit includes a JFET transistor, a first capacitor, a first resistor and a second resistor, the gate of the JFET transistor is grounded, the drain of the JFET transistor is connected to the rectified bus voltage port, the source of the JFET transistor is connected to the first capacitor and the first resistor in sequence, and the lower end of the first resistor is grounded; the upper end of the second resistor is connected to the bias voltage, and the lower end of the second resistor is simultaneously connected to the connection point between the first capacitor and the first resistor and the input end of the shaping and analog-to-digital conversion circuit unit.

可选地,所述边沿检测电路单元包括第二电容和第三电阻,所述第二电容的一端与所述整流后的母线电压端口连接,另一端分别与第三电阻的上端和整形及模数转换电路单元的输入端连接,所述第三电阻的下端接地。Optionally, the edge detection circuit unit includes a second capacitor and a third resistor, one end of the second capacitor is connected to the rectified bus voltage port, and the other end is respectively connected to the upper end of the third resistor and the input end of the shaping and analog-to-digital conversion circuit unit, and the lower end of the third resistor is grounded.

优选地,所述整形及模数转换电路单元包括第一比较器,所述第一比较器的正向输入端与所述第二电阻的下端连接,所述第一比较器的反向输入端接入第一基准电压,所述第一比较器的输出端与所述数字控制电路单元的输入端连接。Preferably, the shaping and analog-to-digital conversion circuit unit includes a first comparator, the positive input terminal of the first comparator is connected to the lower end of the second resistor, the reverse input terminal of the first comparator is connected to a first reference voltage, and the output terminal of the first comparator is connected to the input terminal of the digital control circuit unit.

可选地,所述整形及模数转换电路单元包括第二比较器,所述第二比较器的反向输入端与所述第三电阻的上端连接,所述第二比较器的正向输入端接入第二基准电压,所述第二比较器的输出端与所述数字控制电路单元的输入端连接。Optionally, the shaping and analog-to-digital conversion circuit unit includes a second comparator, the inverting input terminal of the second comparator is connected to the upper end of the third resistor, the positive input terminal of the second comparator is connected to a second reference voltage, and the output terminal of the second comparator is connected to the input terminal of the digital control circuit unit.

优选地,所述数字控制电路单元具有循环的初始状态、锁定状态、过渡状态和保持状态,对应不同的状态,所述数字控制电路单元输出不同的幅度控制信号。Preferably, the digital control circuit unit has a cyclic initial state, a locking state, a transition state and a holding state, and corresponding to different states, the digital control circuit unit outputs different amplitude control signals.

可选地,所述数字控制电路单元具有循环的初始状态、锁定状态和保持状态,对应不同的状态,所述数字控制电路单元输出不同的幅度控制信号。Optionally, the digital control circuit unit has a cyclic initial state, a locking state and a holding state, and corresponding to different states, the digital control circuit unit outputs different amplitude control signals.

进一步地,所述数模转换电路单元包括基准电源、多个串联的分压电阻及多个选择开关,所述数模转换电路单元根据所述数字控制电路单元输出的幅度控制信号控制相应的选择开关断开或闭合,以使所述数模转换电路单元输出与时序状态对应的电平信号。Furthermore, the digital-to-analog conversion circuit unit includes a reference power supply, a plurality of voltage-dividing resistors connected in series, and a plurality of selection switches. The digital-to-analog conversion circuit unit controls the corresponding selection switches to open or close according to the amplitude control signal output by the digital control circuit unit, so that the digital-to-analog conversion circuit unit outputs a level signal corresponding to the timing state.

本发明提供的技术方案带来的有益效果如下:The beneficial effects brought by the technical solution provided by the present invention are as follows:

1)可控硅锁定电流及保持电流由V-I转换及主动泄放电路产生,时间及幅值控制利用数模混合电路实现,因此不需要RC边沿检测线路产生锁定电流和锁定过渡时间,因此随着RC值大大降低,体积大大缩小以有利于系统集成,实现驱动器的小型化;1) The thyristor locking current and holding current are generated by V-I conversion and active discharge circuit, and the time and amplitude control are realized by digital-analog hybrid circuit, so there is no need for RC edge detection circuit to generate locking current and locking transition time. Therefore, as the RC value is greatly reduced, the volume is greatly reduced, which is conducive to system integration and realizes the miniaturization of the driver;

2)利用数字控制电路引入过渡状态,降低电磁干扰,降低解决方案的整体成本;2) Use digital control circuits to introduce transition states, reduce electromagnetic interference, and reduce the overall cost of the solution;

3)利用V-I转换及主动泄放电路实现对泄放电流的精确控制。3) Use V-I conversion and active discharge circuit to achieve precise control of discharge current.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

图1是现有技术中利用外置RC线路产生可控硅导通锁定及过渡电流的解决方案线路图;FIG1 is a circuit diagram of a solution for generating a thyristor conduction lock and transition current by using an external RC circuit in the prior art;

图2是本发明实施例提供的可控硅调光主动泄放控制电路总拓扑结构框图;2 is a block diagram of the overall topology structure of a thyristor dimming active discharge control circuit provided by an embodiment of the present invention;

图3是本发明实施例提供的第一种可控硅调光主动泄放控制电路优选线路图;FIG3 is a preferred circuit diagram of a first thyristor dimming active discharge control circuit provided by an embodiment of the present invention;

图4是本发明实施例提供的第二种可控硅调光主动泄放控制电路可选线路图;4 is an optional circuit diagram of a second thyristor dimming active discharge control circuit provided by an embodiment of the present invention;

图5是本发明实施例提供的典型时序波形图。FIG. 5 is a typical timing waveform diagram provided by an embodiment of the present invention.

其中,附图标记包括:1-边沿检测电路单元,11-JFET晶体管,12-第一电容,13-第一电阻,14-第二电阻,15-第二电容,16-第三电阻,2-整形及模数转换电路单元,21-第一比较器,22-第二比较器,3-数字控制电路单元,4-数模转换电路单元,41-基准电源,42-分压电阻,43-选择开关,5-V-I转换及主动泄放电路单元,51-放大器,52-第一功率晶体管,53-泄放电阻,54-第二功率晶体管,6-母线电压端口6。Among them, the figure marks include: 1-edge detection circuit unit, 11-JFET transistor, 12-first capacitor, 13-first resistor, 14-second resistor, 15-second capacitor, 16-third resistor, 2-shaping and analog-to-digital conversion circuit unit, 21-first comparator, 22-second comparator, 3-digital control circuit unit, 4-digital-to-analog conversion circuit unit, 41-reference power supply, 42-voltage divider resistor, 43-selection switch, 5-V-I conversion and active discharge circuit unit, 51-amplifier, 52-first power transistor, 53-discharge resistor, 54-second power transistor, 6-bus voltage port 6.

具体实施方式Detailed ways

为了使本技术领域的人员更好地理解本发明方案,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分的实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本发明保护的范围。In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

需要说明的是,本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含。It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

在本发明的一个实施例中,提供了一种可控硅调光主动泄放控制电路的总拓扑图,参见图2,所述泄放控制电路包括边沿检测电路单元1、整形及模数转换电路单元2、数字控制电路单元3、数模转换电路单元4及V-I转换及主动泄放电路单元5,所述边沿检测电路单元1、V-I转换及主动泄放电路单元5均与整流后的母线电压端口6连接;In one embodiment of the present invention, a general topology diagram of a thyristor dimming active discharge control circuit is provided, referring to FIG2 , wherein the discharge control circuit comprises an edge detection circuit unit 1, a shaping and analog-to-digital conversion circuit unit 2, a digital control circuit unit 3, a digital-to-analog conversion circuit unit 4, and a V-I conversion and active discharge circuit unit 5, wherein the edge detection circuit unit 1, the V-I conversion and active discharge circuit unit 5 are all connected to a rectified bus voltage port 6;

所述边沿检测电路单元1用于检测可控硅导通时母线电压的上升沿或下降沿,以输出微分信号V_edge,所述边沿检测电路单元1的输出端与整形及模数转换电路单元2的输入端连接,以将所述微分信号V_edge输入所述整形及模数转换电路单元2;The edge detection circuit unit 1 is used to detect the rising edge or falling edge of the bus voltage when the thyristor is turned on, so as to output a differential signal V_edge. The output end of the edge detection circuit unit 1 is connected to the input end of the shaping and analog-to-digital conversion circuit unit 2, so as to input the differential signal V_edge into the shaping and analog-to-digital conversion circuit unit 2;

所述整形及模数转换电路单元2将所述微分信号V_edge转换为数字信号D_shape,所述整形及模数转换电路单元2的输出端与数字控制电路单元3的输入端连接,以将所述数字信号D_shape输入所述数字控制电路单元3;The shaping and analog-to-digital conversion circuit unit 2 converts the differential signal V_edge into a digital signal D_shape, and the output end of the shaping and analog-to-digital conversion circuit unit 2 is connected to the input end of the digital control circuit unit 3 to input the digital signal D_shape into the digital control circuit unit 3;

所述数字控制电路单元3根据所述数字信号D_shape产生相应泄放电路所需时序和幅度控制信号D_ctrl,所述数字控制电路单元3的输出端与数模转换电路单元4的输入端连接,以将所述时序和幅度控制信号D_ctrl输入所述数模转换电路单元4;The digital control circuit unit 3 generates a timing and amplitude control signal D_ctrl required by the corresponding discharge circuit according to the digital signal D_shape, and the output end of the digital control circuit unit 3 is connected to the input end of the digital-to-analog conversion circuit unit 4 to input the timing and amplitude control signal D_ctrl into the digital-to-analog conversion circuit unit 4;

所述数模转换电路单元4根据所述时序和幅度控制信号D_ctrl在相应的时间选择相应的控制电平信号V_ctrl,所述数模转换电路单元4的输出端与V-I转换及主动泄放电路单元5的输入端连接,以将所述控制电平信号V_ctrl输入所述V-I转换及主动泄放电路单元5;The digital-to-analog conversion circuit unit 4 selects a corresponding control level signal V_ctrl at a corresponding time according to the timing and amplitude control signal D_ctrl, and the output end of the digital-to-analog conversion circuit unit 4 is connected to the input end of the V-I conversion and active discharge circuit unit 5 to input the control level signal V_ctrl into the V-I conversion and active discharge circuit unit 5;

所述V-I转换及主动泄放电路单元5输出受所述控制电平信号V_ctrl控制的主动泄放电流信号I_bleed。The V-I conversion and active bleeding circuit unit 5 outputs an active bleeding current signal I_bleed controlled by the control level signal V_ctrl.

具体地,边沿检测输出信号V_edge、整形后的数字信号D_shape、数字控制信号D_ctrl、时序主动泄放信号转模拟控制信号V_ctrl、主动泄放电流信号I_bleed的典型时序波形如图5所示,可以看出,在经过整流的母线电压端口输出偏离正弦波形的电压时,数字控制电路和数模转换电路控制产生锁定时间、过渡时间、保持时间对应的电压,进而由所述V-I转换及主动泄放电路单元5转换得到相应的锁定电流、过渡电流和保持电流,精确控制泄放电流。Specifically, typical timing waveforms of the edge detection output signal V_edge, the shaped digital signal D_shape, the digital control signal D_ctrl, the timing active discharge signal converted to the analog control signal V_ctrl, and the active discharge current signal I_bleed are shown in FIG5 . It can be seen that when the rectified bus voltage port outputs a voltage that deviates from the sinusoidal waveform, the digital control circuit and the digital-to-analog conversion circuit control the generation of voltages corresponding to the locking time, transition time, and holding time, and then the V-I conversion and active discharge circuit unit 5 convert the corresponding locking current, transition current, and holding current to accurately control the discharge current.

针对图2的可控硅调光主动泄放控制电路的总拓扑图,具体有至少以下两种可实施方式,无论采用何种方式,其工作原理与上述的总拓扑图的工作原理和过程相同,只是具体披露了边沿检测电路单元1、整形及模数转换电路单元2、数字控制电路单元3、数模转换电路单元4及V-I转换及主动泄放电路单元5的具体线路,以下分别对两种可实施方式作出具体说明:With respect to the general topology of the thyristor dimming active discharge control circuit of FIG2 , there are at least the following two possible implementation modes. Regardless of the method adopted, the working principle is the same as the working principle and process of the above-mentioned general topology, except that the specific circuits of the edge detection circuit unit 1, the shaping and analog-to-digital conversion circuit unit 2, the digital control circuit unit 3, the digital-to-analog conversion circuit unit 4 and the V-I conversion and active discharge circuit unit 5 are specifically disclosed. The two possible implementation modes are specifically described below:

实施例1Example 1

在第一种优选实施方式中,参见图3,所述边沿检测电路单元1包括JFET晶体管11、第一电容12、第一电阻13和第二电阻14,所述JFET晶体管11的栅极接地,所述JFET晶体管11的漏极与所述整流后的母线电压端口6连接,所述JFET晶体管11的源极与第一电容12、第一电阻13顺序连接,所述第一电阻13的下端接地;所述第二电阻14的上端接入偏置电压,所述第二电阻14的下端同时与第一电容12、第一电阻13之间的连接点及所述整形及模数转换电路单元2的输入端连接。其中,所述整形及模数转换电路单元2结构如下:In the first preferred embodiment, referring to FIG3 , the edge detection circuit unit 1 includes a JFET transistor 11, a first capacitor 12, a first resistor 13, and a second resistor 14. The gate of the JFET transistor 11 is grounded, the drain of the JFET transistor 11 is connected to the rectified bus voltage port 6, the source of the JFET transistor 11 is sequentially connected to the first capacitor 12 and the first resistor 13, and the lower end of the first resistor 13 is grounded; the upper end of the second resistor 14 is connected to a bias voltage, and the lower end of the second resistor 14 is simultaneously connected to the connection point between the first capacitor 12 and the first resistor 13 and the input end of the shaping and analog-to-digital conversion circuit unit 2. The structure of the shaping and analog-to-digital conversion circuit unit 2 is as follows:

所述整形及模数转换电路单元2包括第一比较器21,所述第一比较器21的正向输入端与所述第二电阻14的下端连接,所述第一比较器21的反向输入端接入第一基准电压V_ref1,所述第一比较器21的输出端与所述数字控制电路单元3的输入端连接。其中,所述数字控制电路单元3结构如下:The shaping and analog-to-digital conversion circuit unit 2 includes a first comparator 21, a positive input terminal of the first comparator 21 is connected to the lower end of the second resistor 14, a negative input terminal of the first comparator 21 is connected to a first reference voltage V_ref1, and an output terminal of the first comparator 21 is connected to an input terminal of the digital control circuit unit 3. The structure of the digital control circuit unit 3 is as follows:

所述数字控制电路单元3具有循环的初始状态、锁定状态、过渡状态和保持状态,对应不同的状态,所述数字控制电路单元3输出不同的幅度控制信号。The digital control circuit unit 3 has a cyclic initial state, a locking state, a transition state and a holding state. Corresponding to different states, the digital control circuit unit 3 outputs different amplitude control signals.

与数字控制电路单元3输出对应的是数模转换电路单元4,具体包括基准电源41、多个串联的分压电阻42及多个选择开关43,所述数模转换电路单元4根据所述数字控制电路单元3输出的幅度控制信号控制相应的选择开关43断开或闭合,以使所述数模转换电路单元4输出与时序状态对应的电平信号,包括对应于锁定时间的锁定电平、对应于过渡时间的过渡电平、对应于保持时间的保持电平。Corresponding to the output of the digital control circuit unit 3 is the digital-to-analog conversion circuit unit 4, which specifically includes a reference power supply 41, multiple voltage-dividing resistors 42 connected in series, and multiple selection switches 43. The digital-to-analog conversion circuit unit 4 controls the corresponding selection switch 43 to open or close according to the amplitude control signal output by the digital control circuit unit 3, so that the digital-to-analog conversion circuit unit 4 outputs a level signal corresponding to the timing state, including a lock level corresponding to the lock time, a transition level corresponding to the transition time, and a hold level corresponding to the hold time.

参见图3,所述V-I转换及主动泄放电路单元5包括放大器51、第一功率晶体管52和泄放电阻53,所述放大器51的同向输入端与所述数模转换电路单元4的输出端连接(得到对应时序状态的电平信号),所述放大器51的输出端与所述第一功率晶体管52的栅极连接,所述第一功率晶体管52的漏极与所述整流后的母线电压端口6连接,所述放大器51的反向输入端、第一功率晶体管52的源极均与所述泄放电阻53的一端连接,所述泄放电阻53的另一端接地,在此情况下,所述泄放电流通过以下公式计算得到:Referring to FIG3 , the V-I conversion and active discharge circuit unit 5 includes an amplifier 51, a first power transistor 52 and a discharge resistor 53. The non-inverting input terminal of the amplifier 51 is connected to the output terminal of the digital-to-analog conversion circuit unit 4 (to obtain a level signal corresponding to the timing state), the output terminal of the amplifier 51 is connected to the gate of the first power transistor 52, the drain of the first power transistor 52 is connected to the rectified bus voltage port 6, the reverse input terminal of the amplifier 51 and the source of the first power transistor 52 are both connected to one end of the discharge resistor 53, and the other end of the discharge resistor 53 is grounded. In this case, the discharge current is calculated by the following formula:

I_bleed=V_ctrlRs,其中,I_bleed为受控的主动泄放电流,V_ctrl为数模转换电路单元4输出的电压,Rs为泄放电阻53阻值,其中V_ctrl随着初始状态、锁定状态、过渡状态和保持状态的时序变化而输出不同的电压值。I_bleed=V_ctrlR s , where I_bleed is the controlled active bleeding current, V_ctrl is the voltage output by the digital-to-analog conversion circuit unit 4 , and R s is the resistance of the bleeding resistor 53 , wherein V_ctrl outputs different voltage values as the timing of the initial state, the locking state, the transition state, and the holding state changes.

以上为可控硅调光主动泄放控制电路的优选实施方式,其优点在于可以双边检测以适应上升沿和下降沿两种可控硅调光器,过渡状态的引入能够大大降低电磁干扰(EMI),精确控制泄放电流。The above is a preferred implementation of the thyristor dimming active discharge control circuit, which has the advantage of enabling bilateral detection to adapt to both rising edge and falling edge thyristor dimmers, and the introduction of the transition state can greatly reduce electromagnetic interference (EMI) and accurately control the discharge current.

实施例2Example 2

在第一种可选实施方式中,与实施例1不同的是,本实施例中的边沿检测电路单元1不包括JFET晶体管11和接入偏置电压的第二电阻14,参见图4,所述边沿检测电路单元1包括第二电容15和第三电阻16,所述第二电容15的一端与所述整流后的母线电压端口6连接,另一端分别与第三电阻16的上端和整形及模数转换电路单元2的输入端连接,所述第三电阻16的下端接地,本实施例中的边沿检测电路单元1只能适应上升沿可控硅调光器。其中,所述整形及模数转换电路单元2结构如下:In the first optional implementation, different from Example 1, the edge detection circuit unit 1 in this embodiment does not include the JFET transistor 11 and the second resistor 14 connected to the bias voltage. Referring to FIG4 , the edge detection circuit unit 1 includes a second capacitor 15 and a third resistor 16. One end of the second capacitor 15 is connected to the rectified bus voltage port 6, and the other end is respectively connected to the upper end of the third resistor 16 and the input end of the shaping and analog-to-digital conversion circuit unit 2. The lower end of the third resistor 16 is grounded. The edge detection circuit unit 1 in this embodiment can only adapt to the rising edge thyristor dimmer. Among them, the shaping and analog-to-digital conversion circuit unit 2 has the following structure:

与实施例1不同的是,本实施例中整形及模数转换电路单元2的第二比较器22的反向输入端与所述第三电阻16的上端连接,所述第二比较器22的正向输入端接入第二基准电压V_ref2,所述第二比较器22的输出端与所述数字控制电路单元3的输入端连接。其中,所述数字控制电路单元3结构如下:Different from the embodiment 1, in this embodiment, the inverting input terminal of the second comparator 22 of the shaping and analog-to-digital conversion circuit unit 2 is connected to the upper end of the third resistor 16, the positive input terminal of the second comparator 22 is connected to the second reference voltage V_ref2, and the output terminal of the second comparator 22 is connected to the input terminal of the digital control circuit unit 3. The structure of the digital control circuit unit 3 is as follows:

所述数字控制电路单元3具有循环的初始状态、锁定状态和保持状态,对应不同的状态,所述数字控制电路单元3输出不同的幅度控制信号。可以看出,与实施例1不同的是,本实施例中的数字控制电路单元3只输出三种状态,即少了过渡状态,因此,缺少过渡时间控制以无法产生过渡电流,EMI较高。The digital control circuit unit 3 has a cyclic initial state, a locking state and a holding state, and the digital control circuit unit 3 outputs different amplitude control signals corresponding to different states. It can be seen that, unlike the embodiment 1, the digital control circuit unit 3 in this embodiment only outputs three states, that is, the transition state is missing, so there is no transition time control and the transition current cannot be generated, and the EMI is high.

与所述数字控制电路单元3的输出对应的数模转换电路单元4与实施例1的结构相同,但是由于所述数字控制电路单元3输出三种时序状态,因此本实施例中的数模转换电路单元4输出锁定电平和保持电平,而无过渡电平。The digital-to-analog conversion circuit unit 4 corresponding to the output of the digital control circuit unit 3 has the same structure as that of Example 1, but since the digital control circuit unit 3 outputs three timing states, the digital-to-analog conversion circuit unit 4 in this embodiment outputs a lock level and a hold level without a transition level.

与实施例1不同的是,在本实施例中,所述V-I转换及主动泄放电路单元5不包括放大器51和泄放电阻53,如图4所示,所述V-I转换及主动泄放电路单元5包括第二功率晶体管54,所述第二功率晶体管54的栅极与所述数模转换电路单元4的输出端连接,所述第二功率晶体管54的漏极与所述整流后的母线电压端口6连接,所述第二功率晶体管54的源极接地。在此情况下,所述泄放电流通过以下公式计算得到:Different from the embodiment 1, in this embodiment, the V-I conversion and active discharge circuit unit 5 does not include the amplifier 51 and the discharge resistor 53. As shown in FIG4 , the V-I conversion and active discharge circuit unit 5 includes a second power transistor 54, the gate of the second power transistor 54 is connected to the output end of the digital-to-analog conversion circuit unit 4, the drain of the second power transistor 54 is connected to the rectified bus voltage port 6, and the source of the second power transistor 54 is grounded. In this case, the discharge current is calculated by the following formula:

I_bleed=Beta*(V_ctl-VTH)2,其中,I_bleed为受控的主动泄放电流,Beta为第二功率晶体管54的导电因子,V_ctrl为数模转换电路单元4输出的电压,VTH为第二功率晶体管54的阈值电压,其中V_ctrl随着初始状态、锁定状态和保持状态的时序变化而输出不同的电压值。通过计算公式可以看出,本实施例的泄放电流是通过经典公式计算得到,且缺乏过度状态控制的情况下,主动泄放电流控制不精确。但是较实施例1而言,本实施例2的成本较低,实现方法简单。I_bleed=Beta*(V_ctl-V TH ) 2 , where I_bleed is the controlled active bleeding current, Beta is the conductivity factor of the second power transistor 54, V_ctrl is the voltage output by the digital-to-analog conversion circuit unit 4, and V TH is the threshold voltage of the second power transistor 54, where V_ctrl outputs different voltage values as the timing of the initial state, the locked state, and the hold state changes. It can be seen from the calculation formula that the bleeding current of this embodiment is calculated by the classical formula, and in the absence of transition state control, the active bleeding current control is not accurate. However, compared with embodiment 1, the cost of embodiment 2 is lower and the implementation method is simple.

本发明仅需要利用RC线路检测可控硅导通时母线电压上升沿或下降沿,可控硅锁定电流及保持电流由V-I转换及主动泄放电路单元产生,而时间和幅度控制均由RC线路后续的数模混合电路实现,不需要RC边沿检测线路产生锁定电流和锁定过渡时间,降低了整体解决方案的体积和成本,提高系统集成化程度。The present invention only needs to use the RC circuit to detect the rising edge or falling edge of the bus voltage when the thyristor is turned on. The thyristor locking current and holding current are generated by the V-I conversion and active discharge circuit unit, and the time and amplitude control are both realized by the subsequent digital-analog hybrid circuit of the RC circuit. The RC edge detection circuit is not required to generate the locking current and the locking transition time, which reduces the volume and cost of the overall solution and improves the degree of system integration.

以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (3)

1. The silicon controlled rectifier dimming active bleeder control circuit is characterized by comprising an edge detection circuit unit (1), a shaping and analog-to-digital conversion circuit unit (2), a digital control circuit unit (3), a digital-to-analog conversion circuit unit (4) and a V-I conversion and active bleeder circuit unit (5), wherein the edge detection circuit unit (1), the V-I conversion and active bleeder circuit unit (5) are connected with a rectified bus voltage port (6);
the edge detection circuit unit (1) is used for detecting the rising edge or the falling edge of the bus voltage when the controllable silicon is conducted so as to output differential signals, and the output end of the edge detection circuit unit (1) is connected with the input end of the shaping and analog-to-digital conversion circuit unit (2);
The shaping and analog-to-digital conversion circuit unit (2) converts the differential signal into a digital signal, and the output end of the shaping and analog-to-digital conversion circuit unit (2) is connected with the input end of the digital control circuit unit (3);
The digital control circuit unit (3) generates time sequence and amplitude control signals required by the corresponding bleeder circuit according to the digital signals, and the output end of the digital control circuit unit (3) is connected with the input end of the digital-to-analog conversion circuit unit (4);
the digital-to-analog conversion circuit unit (4) selects corresponding control level signals at corresponding time according to the time sequence and the amplitude control signals, and the output end of the digital-to-analog conversion circuit unit (4) is connected with the input end of the V-I conversion and active bleeder circuit unit (5);
The V-I conversion and active bleeder circuit unit (5) outputs an active bleeder current signal controlled by the control level signal;
The V-I conversion and active bleeder circuit unit (5) comprises an amplifier (51), a first power transistor (52) and a bleeder resistor (53), wherein the homodromous input end of the amplifier (51) is connected with the output end of the digital-to-analog conversion circuit unit (4), the output end of the amplifier (51) is connected with the grid electrode of the first power transistor (52), the drain electrode of the first power transistor (52) is connected with the rectified bus voltage port (6), the reverse input end of the amplifier (51) and the source electrode of the first power transistor (52) are connected with one end of the bleeder resistor (53), and the other end of the bleeder resistor (53) is grounded;
The edge detection circuit unit (1) comprises a JFET transistor (11), a first capacitor (12), a first resistor (13) and a second resistor (14), wherein the grid electrode of the JFET transistor (11) is grounded, the drain electrode of the JFET transistor (11) is connected with the rectified bus voltage port (6), the source electrode of the JFET transistor (11) is sequentially connected with the first capacitor (12) and the first resistor (13), and the lower end of the first resistor (13) is grounded; the upper end of the second resistor (14) is connected with bias voltage, and the lower end of the second resistor (14) is connected with the first capacitor (12), the connection point between the first resistors (13) and the input end of the shaping and analog-to-digital conversion circuit unit (2) at the same time;
The shaping and analog-to-digital conversion circuit unit (2) comprises a first comparator (21), wherein the forward input end of the first comparator (21) is connected with the lower end of the second resistor (14), the reverse input end of the first comparator (21) is connected with a first reference voltage, and the output end of the first comparator (21) is connected with the input end of the digital control circuit unit (3);
The digital control circuit unit (3) is provided with a cyclic initial state, a locking state, a transition state and a holding state, and corresponds to different states, and the digital control circuit unit (3) outputs different amplitude control signals;
the bleed current is calculated by the following formula: i_blank=v_ctrl×r s, where i_blank is a controlled active bleed current, v_ctrl is a voltage output by the digital-to-analog conversion circuit unit (4), and R s is a resistance value of the bleed resistor (53), where v_ctrl outputs different voltage values with time sequence changes of an initial state, a lock state, a transition state, and a hold state.
2. The silicon controlled rectifier dimming active bleeder control circuit is characterized by comprising an edge detection circuit unit (1), a shaping and analog-to-digital conversion circuit unit (2), a digital control circuit unit (3), a digital-to-analog conversion circuit unit (4) and a V-I conversion and active bleeder circuit unit (5), wherein the edge detection circuit unit (1), the V-I conversion and active bleeder circuit unit (5) are connected with a rectified bus voltage port (6);
the edge detection circuit unit (1) is used for detecting the rising edge or the falling edge of the bus voltage when the controllable silicon is conducted so as to output differential signals, and the output end of the edge detection circuit unit (1) is connected with the input end of the shaping and analog-to-digital conversion circuit unit (2);
The shaping and analog-to-digital conversion circuit unit (2) converts the differential signal into a digital signal, and the output end of the shaping and analog-to-digital conversion circuit unit (2) is connected with the input end of the digital control circuit unit (3);
The digital control circuit unit (3) generates time sequence and amplitude control signals required by the corresponding bleeder circuit according to the digital signals, and the output end of the digital control circuit unit (3) is connected with the input end of the digital-to-analog conversion circuit unit (4);
the digital-to-analog conversion circuit unit (4) selects corresponding control level signals at corresponding time according to the time sequence and the amplitude control signals, and the output end of the digital-to-analog conversion circuit unit (4) is connected with the input end of the V-I conversion and active bleeder circuit unit (5);
The V-I conversion and active bleeder circuit unit (5) outputs an active bleeder current signal controlled by the control level signal;
The V-I conversion and active bleeder circuit unit (5) comprises a second power transistor (54), wherein the grid electrode of the second power transistor (54) is connected with the output end of the digital-to-analog conversion circuit unit (4), the drain electrode of the second power transistor (54) is connected with the rectified bus voltage port (6), and the source electrode of the second power transistor (54) is grounded;
The edge detection circuit unit (1) comprises a second capacitor (15) and a third resistor (16), one end of the second capacitor (15) is connected with the rectified bus voltage port (6), the other end of the second capacitor is respectively connected with the upper end of the third resistor (16) and the input end of the shaping and analog-to-digital conversion circuit unit (2), and the lower end of the third resistor (16) is grounded;
the shaping and analog-to-digital conversion circuit unit (2) comprises a second comparator (22), wherein the reverse input end of the second comparator (22) is connected with the upper end of the third resistor (16), the positive input end of the second comparator (22) is connected with a second reference voltage, and the output end of the second comparator (22) is connected with the input end of the digital control circuit unit (3);
The digital control circuit unit (3) is provided with a cyclic initial state, a locking state and a holding state, and corresponds to different states, and the digital control circuit unit (3) outputs different amplitude control signals;
the bleed current is calculated by the following formula: i_block=beta× (v_ctrl-V TH)2, where i_block is a controlled active bleed current, beta is a conduction factor of the second power transistor (54), v_ctrl is a voltage output by the digital-to-analog conversion circuit unit (4), and V TH is a threshold voltage of the second power transistor (54), where v_ctrl outputs different voltage values with time sequence changes of an initial state, a lock state, and a hold state.
3. The active bleeder control circuit according to claim 1 or 2, wherein the digital-to-analog conversion circuit unit (4) comprises a reference power supply (41), a plurality of series voltage dividing resistors (42) and a plurality of selection switches (43), and the digital-to-analog conversion circuit unit (4) controls the opening or closing of the corresponding selection switches (43) according to the amplitude control signal output by the digital control circuit unit (3) so that the digital-to-analog conversion circuit unit (4) outputs a level signal corresponding to a time sequence state.
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DE102020213249A1 (en) * 2020-10-20 2022-04-21 Volkswagen Aktiengesellschaft Device and method for actively discharging an intermediate circuit capacitor
CN117458848B (en) * 2023-12-26 2024-10-01 西安荣耀终端有限公司 Power bus bleeder circuit, display device and power adapter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107846756A (en) * 2017-11-29 2018-03-27 深圳音浮光电股份有限公司 LED light modulating devices
CN108463030A (en) * 2018-04-18 2018-08-28 矽力杰半导体技术(杭州)有限公司 LED drive circuit, circuit module with controllable silicon dimmer and control method
CN209462665U (en) * 2018-12-19 2019-10-01 苏州菲达旭微电子有限公司 A kind of controllable silicon light modulation is actively released control circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102238774B (en) * 2010-04-30 2016-06-01 奥斯兰姆有限公司 Angle of flow acquisition methods and device, and LED driving method and device
KR20120080908A (en) * 2011-01-10 2012-07-18 페어차일드코리아반도체 주식회사 Apparatus for controlling bleed switch, power supply, and method for driving power supply
EP2590477B1 (en) * 2011-11-07 2018-04-25 Silergy Corp. A method of controlling a ballast, a ballast, a lighting controller, and a digital signal processor
US9408261B2 (en) * 2013-05-07 2016-08-02 Power Integrations, Inc. Dimmer detector for bleeder circuit activation
CN205051938U (en) * 2015-10-22 2016-02-24 成都绿洲电子有限公司 Active offset voltage type LED drive circuit who adjusts of phase place
CN205040078U (en) * 2015-10-22 2016-02-17 成都绿洲电子有限公司 Anti EMI's offset -type LED drive circuit
CN205029943U (en) * 2015-10-22 2016-02-10 成都绿洲电子有限公司 LED driver based on damping circuit
CN106793352B (en) * 2017-04-06 2018-11-13 矽力杰半导体技术(杭州)有限公司 LED drive circuit, circuit module with controllable silicon dimmer and control method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107846756A (en) * 2017-11-29 2018-03-27 深圳音浮光电股份有限公司 LED light modulating devices
CN108463030A (en) * 2018-04-18 2018-08-28 矽力杰半导体技术(杭州)有限公司 LED drive circuit, circuit module with controllable silicon dimmer and control method
CN209462665U (en) * 2018-12-19 2019-10-01 苏州菲达旭微电子有限公司 A kind of controllable silicon light modulation is actively released control circuit

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