CN109658968B

CN109658968B - Operation method of nonvolatile memory device

Info

Publication number: CN109658968B
Application number: CN201710947609.3A
Authority: CN
Inventors: 金完东
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-10-12
Filing date: 2017-10-12
Publication date: 2024-07-30
Anticipated expiration: 2037-10-12
Also published as: CN109658968A

Abstract

Embodiments in accordance with the inventive concept relate to a method of operating a nonvolatile memory device. The method comprises the following steps: performing a first programming operation on the first dummy memory cell; performing a verify operation on the first dummy memory cell using the verify voltage; determining whether the first threshold voltage is higher than the verify voltage; a second programming operation is performed on the first dummy memory cell to reduce the threshold voltage of the first dummy memory cell from the first threshold voltage if the first threshold voltage is determined to be higher than the verify voltage.

Description

Operation method of nonvolatile memory device

Technical Field

The present inventive concept relates to a semiconductor memory, and more particularly, to a nonvolatile memory device and a method of operating the same.

Background

The storage device may store data in response to control of a host device (such as a computer, smart phone, smart tablet, etc.). The storage device may include a Hard Disk Drive (HDD) that stores data on a magnetic disk, or a semiconductor memory that stores data in a nonvolatile memory. The semiconductor memory may be a Solid State Drive (SSD) or a memory card.

The nonvolatile memory may include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.

Disclosure of Invention

Embodiments in accordance with the inventive concept relate to a method of operating a nonvolatile memory device. The nonvolatile memory device includes a plurality of strings, each string including at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed. The method comprises the following steps: performing a first programming operation on a first dummy memory cell in the plurality of cell strings, the first dummy memory cell having a first threshold voltage after the first programming operation; performing a verify operation on the first dummy memory cell using a verify voltage, the verify voltage being an upper limit of a target threshold voltage of the first dummy memory cell after the first program operation; determining whether the first threshold voltage is higher than a verify voltage; in the case where the first threshold voltage is determined to be higher than the verify voltage, a second programming operation is performed on the first dummy memory cell to lower the threshold voltage of the first dummy memory cell from the first threshold voltage, the first dummy memory cell having a second threshold voltage after the second programming operation. The second threshold voltage is lower than the first threshold voltage.

Another embodiment in accordance with the inventive concept relates to a method of operating a nonvolatile memory device. The nonvolatile memory device includes a plurality of strings, each string including at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed. The method comprises the following steps: determining whether the check condition is satisfied; performing a verify-read operation on a first ground select transistor in the plurality of cell strings using a first verify voltage if it is determined that the check condition is satisfied; determining whether a first threshold voltage of the first ground select transistor is higher than a first verify voltage; in the case that it is determined that the first threshold voltage of the first ground selection transistor is higher than the first verification voltage, a first program operation is performed on the first ground selection transistor to lower the first threshold voltage of the first ground selection transistor.

Yet another embodiment in accordance with the inventive concept relates to a method of operating a nonvolatile memory device. The nonvolatile memory device includes a plurality of strings, each string including at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed. The method comprises the following steps: performing a first program operation on memory cells in the plurality of cell strings to raise a first threshold voltage of the memory cells, the programmed memory cells having one of an erased state and a plurality of programmed states according to the programmed first threshold voltage; performing a second programming operation on at least one of the ground select transistor, the string select transistor, and the dummy memory cell to lower the at least one second threshold voltage of the at least one of the ground select transistor, the string select transistor, and the dummy memory cell when the at least one second threshold voltage of the at least one of the ground select transistor, the string select transistor, and the dummy memory cell is higher than the first verify voltage; when the at least one second threshold voltage is lower than the second verifying voltage, a third programming operation is performed on the at least one of the ground select transistor, the string select transistor, and the dummy memory cell to raise the at least one second threshold voltage.

Drawings

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a nonvolatile memory according to an exemplary embodiment of the inventive concept.

Fig. 2 is a circuit diagram illustrating a memory block according to an exemplary embodiment of the inventive concept.

Fig. 3 is a flowchart illustrating an operation method of a nonvolatile memory according to an exemplary embodiment of the inventive concept.

Fig. 4 illustrates a change in threshold voltage of a cell transistor in the operating method of fig. 3 according to an exemplary embodiment of the inventive concept.

Fig. 5 is a flowchart illustrating a first program operation according to an exemplary embodiment of the inventive concept.

Fig. 6 is a table illustrating voltages supplied to a memory block in a first program operation according to an exemplary embodiment of the inventive concept.

Fig. 7 is a table illustrating voltages supplied to a memory block in a first program operation according to an exemplary embodiment of the inventive concept.

Fig. 8 is a flowchart illustrating a second programming operation according to an exemplary embodiment of the inventive concept.

Fig. 9 is a table illustrating voltages supplied to a memory block in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 10 illustrates voltages applied to a selected cell string in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 11 illustrates voltages applied to unselected cell strings in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 12 illustrates voltages applied to unselected cell strings in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 13 illustrates voltages applied to unselected cell strings in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 14 is a table illustrating voltages supplied to a memory block in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 15 illustrates voltages applied to a selected cell string in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 16 is a flowchart illustrating a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 17 is a timing diagram illustrating control of a level of a pass voltage in a second program operation according to an exemplary embodiment of the inventive concept.

Fig. 18 is a flowchart illustrating an operation method of a nonvolatile memory according to an exemplary embodiment of the inventive concept.

Fig. 19 is a flowchart illustrating an operation method of a nonvolatile memory according to an exemplary embodiment of the inventive concept.

Fig. 20 illustrates a change in threshold voltage of a cell transistor in the operation method of fig. 19 according to an exemplary embodiment of the inventive concept.

Fig. 21 is a block diagram illustrating a storage device according to an exemplary embodiment of the inventive concept.

Fig. 22 is a block diagram illustrating a memory controller according to an exemplary embodiment of the inventive concept.

Fig. 23 is a block diagram illustrating a computing device according to an exemplary embodiment of the inventive concept.

Fig. 24 illustrates a perspective view showing a structure of a memory block according to an embodiment of the inventive concept.

Fig. 25 is a cross-sectional view illustrating a structure of a memory block according to an embodiment of the inventive concept.

Fig. 26 shows an example in which a cell transistor corresponding to a connection portion is used as a dummy memory cell.

Fig. 27 illustrates a change in threshold voltage of a memory cell when a program operation and an erase operation are performed on the memory cell.

FIG. 28 is a flowchart illustrating a method of performing a program operation on a memory cell.

Fig. 29 is a flowchart illustrating a method of performing an erase operation on a memory cell.

Fig. 30 illustrates a variation in threshold voltage of a dummy memory cell, a ground select transistor, or a string select transistor when a first program operation is performed.

Fig. 31 is a flowchart illustrating a method of a nonvolatile memory checking a threshold voltage of a dummy memory cell, a ground select transistor, or a string select transistor and performing a first program operation.

Fig. 32 shows an example of a voltage to be applied to a memory block.

Fig. 33 illustrates a variation in threshold voltage of the dummy memory cell, the ground select transistor, or the string select transistor when the second program operation is performed.

Fig. 34 is a flowchart illustrating a method of the nonvolatile memory checking a threshold voltage of a dummy memory cell, a ground select transistor, or a string select transistor and performing a second program operation.

Fig. 35 shows an example of a voltage to be applied to a memory block.

Fig. 36 illustrates an example of inspection conditions according to an embodiment of the inventive concept.

Fig. 37 shows an application example of the memory block of fig. 26.

Detailed Description

The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout the drawings and the written description.

Fig. 1 is a block diagram illustrating a nonvolatile memory 110 according to an exemplary embodiment of the inventive concept. Referring to fig. 1, the nonvolatile memory 110 includes a memory cell array 111, an Address (ADDR) decoder circuit 113, a page buffer circuit 115, a data input/output (I/O) circuit 117, and a control logic circuit 119.

The memory cell array 111 includes a plurality of memory blocks BLK1-BLKz, each of the plurality of memory blocks BLK1-BLKz having a plurality of memory cells. Each memory block may be connected to the address decoder circuit 113 through at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL. Each memory block may be connected to the page buffer circuit 115 through a plurality of bit lines BL. Memory blocks BLK1-BLKz may be commonly connected to bit line BL. The memory cells of the memory blocks BLK1-BLKz may have the same structure. Each of the memory blocks BLK1-BLKz may be an erase operation unit. Memory cells in the memory cell array 111 may be erased in units of one memory block. Memory cells belonging to the same memory block may be erased in one go. In an exemplary embodiment of the inventive concept, each memory block may be divided into a plurality of sub-blocks. Each sub-block may be an erase operation unit.

The address decoder circuit 113 is connected to the memory cell array 111 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The address decoder circuit 113 operates according to the control of the control logic circuit 119. The address decoder circuit 113 is capable of receiving a first address ADDR1 from the memory controller. The address decoder circuit 113 decodes the received first address ADDR1 and controls a voltage applied to the word line WL according to the decoded address.

For example, in a programming operation, the address decoder circuit 113 may apply a programming voltage VPGM to a selected word line of a selected memory block indicated by the first address ADDR1 and a pass voltage VPASS to unselected word lines of the selected memory block. In a read operation, the address decoder circuit 113 may apply a select read voltage VRD to a selected word line of a selected memory block indicated by the first address ADDR1 and apply a non-select voltage VREAD to unselected word lines of the selected memory block. In the erase operation, the address decoder circuit 113 may apply an erase voltage (e.g., a ground voltage or a low voltage having a level similar to the ground voltage) to the selected word line of the selected memory block indicated by the first address ADDR 1.

The page buffer circuit 115 is connected to the memory cell array 111 through a plurality of bit lines BL. The page buffer circuit 115 is connected to the data input/output circuit 117 through a plurality of data lines DL. The page buffer circuit 115 operates according to the control of the control logic circuit 119.

The page buffer circuit 115 can store data to be programmed in the memory cells of the memory cell array 111 or data read from the memory cells of the memory cell array 111. In a programming operation, the page buffer circuit 115 can store data to be programmed in the memory cells. The page buffer circuit 115 can bias the bit line BL based on the stored data. In a programming operation, the page buffer circuit 115 can be used as a write driver. In a read operation, the page buffer circuit 115 is capable of sensing a voltage of the bit line BL and storing a sensing result. In a read operation, the page buffer circuit 115 can function as a sense amplifier.

The data input/output circuit 117 is connected to the page buffer circuit 115 through a plurality of data lines DL. The DATA input/output circuit 117 is capable of exchanging the first DATA1 with the memory controller.

The DATA input/output circuit 117 can temporarily store the first DATA1 received from the memory controller. The DATA input/output circuit 117 can transfer the stored first DATA1 to the memory controller. The data input/output circuit 117 can function as a buffer memory.

The control logic 119 receives a first command CMD1 and a control signal CTRL from the memory controller. The control logic 119 decodes the received first command CMD1 and is capable of controlling the overall operation of the nonvolatile memory 110 according to the decoded command.

In a read operation, the logic control circuit 119 is able to generate a data strobe signal DQS from a read enable signal/RE in the received control signal CTRL and output the data strobe signal DQS. In a write operation, the control logic 119 is able to receive the data strobe signal DQS included in the control signal CTRL.

The control logic circuit 119 includes a program control circuit PC. The program control circuit PC can control a program operation of the nonvolatile memory 110 by controlling the address decoder circuit 113 and the page buffer circuit 115. For example, the program control circuit PC can control the address decoder circuit 113 and the page buffer circuit 115 so that programming is performed according to a programming method according to an exemplary embodiment of the inventive concept.

Fig. 2 is a circuit diagram illustrating a memory block BLKa according to an exemplary embodiment of the inventive concept. Referring to fig. 2, the memory block BLKa includes a plurality of cell strings CS11-CS21 and CS12-CS22. The cell strings CS11-CS21 and CS12-CS22 may be arranged in a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 arranged in the row direction may form a first row, and the cell strings CS21 and CS22 arranged in the row direction may form a second row. The cell strings CS11 and CS21 arranged in the column direction may form a first column, and the cell strings CS12 and CS22 arranged in the column direction may form a second column.

Each cell string CS11-CS21 and CS12-CS22 may include a plurality of cell transistors. The cell transistors include ground select transistors GSTa and GSTb, memory cells MC1-MC6, and string select transistors SSTa and SSTb. The ground selection transistors GSTa and GSTb, the memory cells MC1 to MC6, and the string selection transistors SSTa and SSTb of each cell string may be stacked in a direction perpendicular to a plane (e.g., a plane corresponding to a surface of the substrate on which the memory block BLKa is formed) on which the cell strings CS11 to CS21 and CS12 to CS22 are arranged along rows and columns. For example, transistors of the cell strings may be stacked in the height direction.

The cell transistor may be a charge trapping transistor having a threshold voltage that varies according to the amount of charge trapped by the insulating layer.

The sources of the lowermost ground selection transistors GSTa may be commonly connected to the common source line CSL.

The control gates of the ground select transistors GSTa and GSTb of cell strings CS11-CS21 and CS12-CS22 may be connected to ground select lines GSLa and GSLb, respectively. The same height (or sequence) of ground selection transistors may be connected to the same ground selection line, and different heights (or sequence) of ground selection transistors may be connected to different ground selection lines. For example, the ground selection transistors GSTa of the first height are commonly connected to the ground selection line GSLa, and the ground selection transistors GSTb of the second height are commonly connected to the ground selection line GSLb.

The ground selection transistors of the same row may be connected to the same ground selection line, and the ground selection transistors of different rows may be connected to different ground selection lines. For example, the ground selection transistors GSTa and GSTb of the cell strings CS11 and CS12 of the first row are connected to a first ground selection line, and the ground selection transistors GSTa and GSTb of the cell strings CS21 and CS22 of the second row are connected to a second ground selection line.

The control gates of memory cells located at the same height (or order) from the substrate (or ground selection transistor GST) may be commonly connected to the same word line, and the control gates of memory cells located at different heights (or orders) from the substrate may be connected to different word lines WL1-WL6, respectively. For example, the memory cells MC1 are commonly connected to the word line WL1. Memory cell MC2 is commonly connected to word line WL2. Memory cell MC3 is commonly connected to word line WL3. Memory cell MC4 is commonly connected to word line WL4. Memory cell MC5 is commonly connected to word line WL5. Memory cell MC6 is commonly connected to word line WL6.

At the same height (or sequence) of the first string selection transistors SSTa of the cell strings CS11-CS21 and CS12-CS22, the control gates of the first string selection transistors SSTa of different rows are connected to different string selection lines SSL1a-SSL2a, respectively. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 are commonly connected to the string selection line SSL1a. The first string selection transistors SSTa of the cell strings CS21 and CS22 are commonly connected to a string selection line SSL2a.

At the same height (or sequence) of the second string selection transistors SSTb of the cell strings CS11-CS21 and CS12-CS22, the control gates of the second string selection transistors SSTb of different rows are connected to different string selection lines SSL1b-SSL2b, respectively. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 are commonly connected to the string selection line SSL1b. The second string selection transistors SSTb of the cell strings CS21 and CS22 are commonly connected to a string selection line SSL2b.

Cell strings of different rows are connected to different string select lines. String selection transistors of the same height (or order) of cell strings of the same row are connected to the same string selection line. String selection transistors of different heights (or sequences) of cell strings of the same row are connected to different string selection lines.

String selection transistors of cell strings of the same row may be commonly connected to one string selection line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 of the first row may be commonly connected to one string selection line. For example, the string selection transistors SSTa may be commonly connected to the string selection line SSL1a, and the string selection transistors SSTb may be commonly connected to the string selection line SSL1b. The string selection transistors SSTa and SSTb of the cell strings CS21 and CS22 of the second row may be commonly connected to one string selection line. For example, the string selection transistors SSTa may be commonly connected to the string selection line SSL2a, and the string selection transistors SSTb may be commonly connected to the string selection line SSL2b.

The columns of cell strings CS11-CS21 and CS12-CS22 are connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SSTb of the cell strings CS11 and CS21 of the first column are commonly connected to the bit line BL1. The string selection transistors SSTb of the cell strings CS12 and CS22 of the second column are commonly connected to the bit line BL2.

The cell strings CS11 and CS12 may form a first plane. The cell strings CS21 and CS22 may form a second plane.

In the memory block BLKa, each height of memory cells of each plane may form a physical page. The physical page may be a read cell and a write cell of the memory cells MC1-MC 6. For example, one plane of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2 b. When the on voltage is supplied to the string selection lines SSL1a and SSL1b and the off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11 and CS12 of the first plane are connected to the bit lines BL1 and BL2, respectively. In other words, the first plane is selected. When the on voltage is supplied to the string selection lines SSL2a and SSL2b and the off voltage is supplied to the string selection lines SSL1a and SSL1b, the cell strings CS21 and CS22 of the second plane are connected to the bit lines BL1 and BL2, respectively. In other words, the second plane is selected. In the selected plane, a row of memory cells MC may be selected by word lines WL1-WL 6. In the selected row, a select voltage may be applied to the second word line WL2, and a non-select voltage may be applied to the remaining word lines WL1 and WL3-WL6. In other words, a physical page corresponding to the second word line WL2 of the second plane may be selected by controlling the string selection lines SSL1a, SSL1b, SSL2a and SSL2b and the word lines WL1 to WL6. In the memory cell MC2 of the selected physical page, a write or read operation may be performed.

In the memory block BLKa, the erase operation of the memory cells MC1 to MC6 may be performed in memory block units or sub-block units. When the erase operation is performed in terms of memory block cells, the memory cells MC of the memory block BLKa may be erased all at once according to an erase request (e.g., an erase request from an external memory controller). When the erase operation is performed in sub-block units, a portion of the memory cells MC1 to MC6 of the memory block BLKa may be erased in one time according to an erase request (e.g., an erase request from an external memory controller), and the remaining portion may be inhibited from being erased. A low voltage (e.g., a ground voltage or a voltage having a similar level to the ground voltage) may be supplied to the word line connected to the memory cell being erased, and the word line connected to the memory cell that is inhibited from being erased may be floated.

The memory block BLKa shown in fig. 2 is exemplary. The inventive concept is not limited to the memory block BLKa shown in fig. 2. For example, the number of rows of cell strings may be increased or decreased. As the number of rows of cell strings changes, the number of string selection lines or ground selection lines connected to the rows of cell strings and the number of cell strings connected to one bit line may also change.

The number of columns of cell strings may be increased or decreased. As the number of columns of cell strings changes, the number of bit lines connected to the columns of cell strings and the number of cell strings connected to one string selection line may also change.

The height of the cell strings may be increased or decreased. For example, the number of ground selection transistors, memory cells, or string selection transistors included in each cell string may be increased or decreased.

The memory cells MC belonging to one physical page can correspond to at least three logical pages. For example, k (k is an integer greater than 2) bits can be programmed in one memory cell MC. In the memory cells MC belonging to one physical page, k bits programmed in each memory cell MC can form k logical pages, respectively.

In exemplary embodiments of the inventive concept, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed with an array of memory cells of one or more physical levels having an active region disposed above a silicon substrate and circuitry associated with operation of the memory cells. Such associated circuitry may be located over or within such a substrate. The term "monolithic" may refer to the layers of each level array deposited directly on the layers of each underlying array.

In exemplary embodiments of the inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. Each vertical NAND string also includes at least one select transistor over the memory cell, the at least one select transistor having the same structure as the memory cell and monolithically formed in common with the memory cell.

The following patent documents are incorporated herein by reference in their entirety: U.S. patent nos. US7,679,133, US8,553,466, US8,654,587, US8,559,235, and U.S. patent publication No. US 2011/023648 describe configurations of three-dimensional memory arrays for use in accordance with exemplary embodiments of the inventive concepts. In the foregoing patent documents, the three-dimensional memory array is constructed in multiple stages, with word lines and/or bit lines shared between the stages.

Fig. 3 is a flowchart illustrating an operation method of a nonvolatile memory according to an exemplary embodiment of the inventive concept. Referring to fig. 1 to 3, in step S110, a first program operation is performed so that a threshold voltage of a cell transistor is increased. For example, the threshold voltages of the cell transistors (e.g., all cell transistors) selected as the programming target may be increased. The program control circuit PC can control the voltage applied to the memory cell array 111 so that the threshold voltage of the cell transistor increases.

In step S120, a second program operation is performed so that the threshold voltage of the cell transistor having a higher threshold voltage than the verify voltage VFYu may be lowered. For example, cell transistors having a threshold voltage higher than the verify voltage VFYu among the cell transistors on which the first program operation is performed may be programmed such that their threshold voltages are lowered by the second program operation. Verify voltage VFYu may be the upper end of the target threshold voltage range of the cell transistor. The program control circuit PC can control the voltage applied to the memory cell array 111 such that the threshold voltage of the cell transistor having a threshold voltage higher than the verify voltage VFYu is lowered.

Fig. 4 illustrates a change in threshold voltage of a cell transistor in the operating method of fig. 3 according to an exemplary embodiment of the inventive concept. In fig. 4, the horizontal axis represents the threshold voltage of the cell transistor, and the vertical axis represents the number of cell transistors. In other words, fig. 4 shows the threshold voltage distribution of the cell transistor.

Referring to fig. 1 to 4, an initial threshold voltage distribution of the cell transistor may be represented by a first line L1.

If the first program operation of step S110 is performed, the threshold voltage of the cell transistor is increased. For example, the threshold voltage distribution of the cell transistor may be changed from the first line L1 to the second line L2 through the first program operation.

If the second programming operation of step S120 is performed, the threshold voltage of the cell transistor, which is higher than the verify voltage VFYu, is lowered. For example, the threshold voltage of the cell transistor higher than the verify voltage VFYu may become lower than the verify voltage VFYu. In other words, the threshold voltage distribution of the cell transistor may be changed from the second line L2 to the third line L3 through the second program operation.

As described above, if the first and second program operations are performed, the threshold voltage distribution of the cell transistor is narrowed and the threshold voltage distribution of the cell transistor is limited to only a lower level than the verify voltage VFYu. For example, the width of the threshold voltage distribution denoted by L3 is smaller than the width of the threshold voltage distribution denoted by L2. Since the threshold voltage of the cell transistor is controlled within the target range, the reliability of the nonvolatile memory including the cell transistor is improved.

Fig. 5 is a flowchart illustrating a first program operation according to an exemplary embodiment of the inventive concept. Referring to fig. 1,2 and 5, in step S210, a low voltage is supplied to a channel of a cell transistor. For example, a ground voltage or a low voltage having a level similar to the ground voltage may be supplied to a channel of a cell transistor selected as a programming target.

In step S220, a high voltage is supplied to the control gate of the cell transistor. For example, a high voltage having a level capable of causing Fowler-Nordheim (F-N) tunneling may be supplied to the control gate of a cell transistor selected as a programming target.

F-N tunneling occurs in the cell transistor due to a voltage difference between a low voltage supplied to a channel of the cell transistor and a high voltage supplied to a control gate of the cell transistor. Thus, electrons are trapped in the cell transistor, and the threshold voltage of the cell transistor can be increased.

In a first programming operation, the cell transistor may be programmed through a word line. For example, in a first programming operation, the threshold voltages of memory cells belonging to a physical page connected to the same word line may be increased.

Fig. 6 is a table illustrating voltages supplied to the memory block BLKa in a first program operation according to an exemplary embodiment of the inventive concept. An example of voltages when the memory cell MC is selected as a programming target is shown in fig. 6.

Referring to fig. 2 and 6, a first bit line voltage VBL1 is applied to bit lines BL1 and BL2. The first bit line voltage VBL1 may be a ground voltage or a low voltage having a level similar to the ground voltage.

The first string selection line voltage VSSL1 is applied to the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. The first string selection line voltage VSSL1 may be a voltage that turns on the string selection transistors SST1a, SST1b, SST2a, and SST 2b. SST1a and SST1b correspond to string selection transistors connected to string selection lines SSL1a and SSL1b, and SST2a and SST2b correspond to string selection transistors connected to string selection lines SSL2a and SSL2b. The first string selection line voltage VSSL1 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The first pass voltage VPASS1 is applied to unselected word lines. The first pass voltage VPASS1 may be a voltage that turns on memory cells connected to unselected word lines. The first pass voltage VPASS1 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The first program voltage VPGM1 is applied to the selected word line. The first program voltage VPGM1 may be a high voltage higher than the first pass voltage VPASS 1.

The first ground select line voltage VGSL1 is applied to the ground select lines GSLa and GSLb. The first ground select line voltage VGSL1 may be the voltage of the turn-on ground select transistors GSTa and GSTb. The first ground selection line voltage VGSL1 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The first common source line voltage VCSL1 is applied to the common source line CSL. The first common source line voltage VCSL1 may be a ground voltage or a low voltage having a similar level to the ground voltage.

In this case, the memory cell MC3 connected to the third word line WL3 is selected as a program target of the first program operation. Since the first pass voltage VPASS1 is applied to the first, second, and fourth to sixth word lines WL1, WL2, and WL4 to WL6, the first, second, and fourth to sixth memory cells MC1, MC2, and MC4 to MC6 are turned on. Since the first string selection line voltage VSSL1 is applied to the string selection lines SSL1a, SSL1b, SSL2a and SSL2b, the string selection transistors SST1a, SST1b, SST2a and SST2b are turned on. Since the first ground selection line voltage VGSL1 is applied to the ground selection lines GSLa and GSLb, the ground selection transistors GSTa and GSTb are turned on. Since the first program voltage VPGM1 is applied to the third word line WL3, the memory cell MC3 is turned on.

Since the first bit line voltage VBL1 is supplied to the bit lines BL1 and BL2, a low voltage is supplied to the drain of the third memory cell MC3 through the string selection transistors SST1a, SST1b, SST2a and SST2b and the fourth to sixth memory cells MC4 to MC 6. Further, the first common source line voltage VCSL1 supplied to the common source line CSL is supplied to the source of the third memory cell MC3 through the ground selection transistors GSTa and GSTb and the first and second memory cells MC1 and MC 2.

As described with reference to fig. 5, a low voltage is supplied to the channel of the third memory cell MC3 selected as the target of the first programming operation, and a high voltage is supplied to the control gate of the third memory cell MC 3. Accordingly, the threshold voltage of the third memory cell MC3 increases.

Fig. 7 is a table illustrating voltages supplied to the memory block BLKa in a first program operation according to an exemplary embodiment of the inventive concept. An example of the voltage when the local select transistor GSTa is selected as the programming target is shown in fig. 7.

Referring to fig. 2 and 7, the second bit line voltage VBL2 is applied to the bit lines BL1 and BL2. The second bit line voltage VBL2 may be a ground voltage or a low voltage having a level similar to the ground voltage.

The second string selection line voltage VSSL2 is supplied to the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. The second string selection line voltage VSSL2 may be a voltage that turns on the string selection transistors SST1a, SST1b, SST2a, and SST 2b. The second string selection line voltage VSSL2 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The second pass voltage VPASS2 is applied to the word lines WL1-WL6. The second pass voltage VPASS2 may be a voltage that turns on memory cells connected to word lines WL1-WL6. The second pass voltage VPASS2 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The second ground select line voltage VGSL2 is applied to the unselected ground select lines. The second ground selection line voltage VGSL2 may be a voltage of the ground selection transistor GST. The second ground selection line voltage VGSL2 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The second program voltage VPGM2 is applied to the selected ground select line. The second program voltage VPGM2 may be a high voltage higher than the second pass voltage VPASS 2.

The second common source line voltage VCSL2 is applied to the common source line CSL. The second common source line voltage VCSL2 may be a ground voltage or a low voltage having a similar level to the ground voltage.

In this case, the ground selection transistor GSTa connected to the ground selection line GSLa is selected as a program target of the first program operation. Since the second pass voltage VPASS2 is applied to the first to sixth word lines WL1 to WL6, the first to sixth memory cells MC1 to MC6 are turned on. Since the second ground selection line voltage VGSL2 is applied to the ground selection line GSLb, the ground selection transistor GSTb is turned on. Since the second program voltage VPGM2 is applied to the ground select line GSLa, the ground select transistor GSTa is turned on.

Since the second bit line voltage VBL2 is supplied to the bit lines BL1 and BL2, a low voltage is supplied to the drain of the ground selection transistor GSTb through the string selection transistors SST1a, SST1b, SST2a, and SST2b and the first to sixth memory cells MC1 to MC6, and is supplied to the drain of the ground selection transistor GSTa through the ground selection transistor GSTb. In addition, the second common source line voltage VCSL2 supplied to the common source line CSL is directly supplied to the source of the ground selection transistor GSTa.

As described with reference to fig. 5, a low voltage is supplied to the channel of the ground selection transistor GSTa selected as the target of the first programming operation, and a high voltage is supplied to the control gate of the ground selection transistor GSTa. Accordingly, F-N tunneling occurs in the ground select transistor GSTa, and the threshold voltage of the ground select transistor GSTa increases.

The ground select transistor GSTb is programmed in a similar manner. For example, the low voltage supplied to the bit lines BL1 and BL2 is transferred to the drain of the ground selection transistor GSTb through the cell transistors on the drain side of the ground selection transistor GSTb (in other words, the string selection transistors SST1a, SST1b, SST2a and SST2b and the memory cells MC1-MC 6). The low voltage supplied to the common source line CSL is supplied to the source of the ground selection transistor GSTb through the cell transistor on the source side of the ground selection transistor GSTb (in other words, the ground selection transistor GSTa). If a high voltage is supplied to the control gate of the ground selection transistor GSTb, the threshold voltage of the ground selection transistor GSTb increases.

Fig. 8 is a flowchart illustrating a second programming operation according to an exemplary embodiment of the inventive concept. Referring to fig. 1 to 3 and 8, in step S310, a verification operation is performed using a verification voltage VFYu. For example, a verifying operation may be performed on the cell transistor on which the first program operation is performed. The verifying operation may be performed in a physical page of the cell transistor on which the first program operation is performed. If the verifying operation is performed, a first cell transistor having a threshold voltage lower than the verifying voltage VFYu and a second cell transistor having a threshold voltage higher than the verifying voltage VFYu among the cell transistors on which the first program operation is performed may be distinguished from each other.

In step S320, it is determined whether the authentication operation has been passed. For example, in the case where there is no second cell transistor or the number of second cell transistors having a threshold voltage higher than the verification voltage VFYu is less than a predetermined value, it may be determined that the verification operation has been passed.

If the verify operation is passed, the second programming operation may be completed. If the verification operation is not passed, step S330 is performed.

In step S330, programming of the first cell transistor having a threshold voltage lower than the verify voltage VFYu is inhibited. In step S340, the second transistor having a threshold voltage higher than the verify voltage VFYu is allowed to be programmed. For example, programming may be inhibited or allowed by differentially controlling the voltage supplied to the first transistor and the voltage supplied to the second transistor. After that, in step S350, a program voltage is supplied to the control gates of the first cell transistor and the second cell transistor. For example, the program voltage may be a voltage that causes hot hole injection in the second cell transistor.

Steps S310 and S320 may form a verification step. Steps S330 to S350 may form a programming step. The verifying step and the programming step may be repeatedly performed until the result of the verifying operation of step S310 is determined to have passed. In other words, the verifying step and the programming step may be repeatedly performed until the threshold voltage of the cell transistor is equal to or less than the verifying voltage VFYu.

When the verifying step and the programming step are repeatedly performed, the level of the voltages applied to the cell strings CS11, CS12, CS21, and CS22 of the memory block BLKa may be changed.

Fig. 9 is a table illustrating voltages supplied to a memory block in a second program operation according to an exemplary embodiment of the inventive concept. An example when the second programming is performed on the memory cell MC is shown in fig. 9.

Referring to fig. 2 and 9, the third bit line voltage VBL3 is applied to the selected bit line. The third bit line voltage VBL3 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage. The fourth bit line voltage VBL4 is applied to the unselected bit lines. The fourth bit line voltage VBL4 may be a ground voltage or a low voltage having a level similar to the ground voltage.

The third string selection line voltage VSSL3 is applied to the selected string selection line. The third string selection line voltage VSSL3 may be a voltage that turns on the string selection transistor. The third string selection line voltage VSSL3 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage. The third string selection line voltage VSSL3 may have substantially the same level as the third bit line voltage VBL 3. The fourth string selection line voltage VSSL4 is applied to the unselected string selection lines. The fourth string selection line voltage VSSL4 may be a power supply voltage or a high voltage higher than the third string selection line voltage VSSL 3. The fourth string select line voltage VSSL4 may be a high voltage. These high voltages can prevent boosting (boosting).

The third program voltage VPGM3 is applied to the selected word line. The third program voltage VPGM3 may have a level that causes hot hole injection in memory cells that allow programming of memory cells connected to the selected word line. The third program voltage VPGM3 may have a lower level than the third common source line voltage VCSL 3. The third program voltage VPGM3 may have a level sufficient to turn off the third memory cell MC 3.

The third pass voltage VPASS3 is applied to unselected word lines. The third pass voltage VPASS3 may be a voltage that turns on the memory cell. The third pass voltage VPASS3 may be a supply voltage or to a high voltage higher than the third string selection line voltage VSSL 3.

The third ground select line voltage VGSL3 is applied to the ground select lines GSLa and GSLb. The third ground select line voltage VGSL3 may be a voltage that turns on the ground select transistors GSTa and GSTb. The third ground selection line voltage VGSL3 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The third common source line voltage VCSL3 is applied to the common source line CSL. The third common source line voltage VCSL3 may be a ground voltage or a low voltage having a similar level to the ground voltage.

As described with reference to fig. 6, the first program operation is performed on the memory cell MC3 connected to the third word line WL 3. In addition, among the third memory cells MC3, the threshold voltage of the third memory cell MC3 belonging to the cell string CS11 is higher than the verify voltage VFYu, and the threshold voltages of the third memory cells MC3 belonging to the remaining cell strings CS12, CS21, and CS22 are lower than the verify voltage VFYu. In other words, the string selection lines SSL1a and SSL1b and the bit line BL1 corresponding to the cell string CS11 are selected, and the string selection lines SSL2a and SSL2b and the bit line BL2 not corresponding to the cell string CS11 are not selected.

Fig. 10 illustrates voltages applied to a selected cell string CS11 in a second program operation according to an exemplary embodiment of the inventive concept. In fig. 10, the cell string CS11 is shown on the right side, and a graph of the voltage (or potential) of the channel of the cell transistor of the cell string CS11 is shown on the left side. In the voltage (or potential) graph, the horizontal axis represents the channel voltage Vch, and the vertical axis represents the location (position) of the cell transistor.

Referring to fig. 2, 9 and 10, a third program voltage VPGM3 is applied to the selected third word line WL3. Therefore, the third memory cell MC3 is turned off. For example, the channel of the third memory cell MC3 has the first type (e.g., p-type). Due to the coupling between the control gate and the channel of the third memory cell MC3, the voltage (or potential) of the channel of the third memory cell MC3 may be reduced.

The third string selection line voltage VSSL3 is applied to the selected string selection lines SSL1a and SSL1b. In an initial state where the third string selection line voltage VSSL3 is applied, the selected string selection lines SSL1a and SSL1b may be turned on.

The third bit line voltage VBL3 is supplied to the selected first bit line BL1. The third bit line voltage VBL3 may be transmitted to the drain of the memory cell MC6 through the channels of the turned-on selected string selection transistors SST1a and SST 1b.

If the third pass voltage VPASS3 is applied to the fourth to sixth word lines WL4 to WL6, the fourth to sixth memory cells MC4 to MC6 are turned on. For example, the channels of the fourth to sixth memory cells MC4 to MC6 have the second type (e.g., n-type). Since the third memory cell MC3 is turned off, the voltage transferred from the selected bit line BL1 to the drain of the sixth memory cell MC6 is transferred to the channels of the fourth to sixth memory cells MC4 to MC 6.

After the fourth to sixth memory cells MC4 to MC6 are turned on, as the voltages of the control gates of the fourth to sixth memory cells MC4 to MC6 rise to the target level of the third pass voltage VPASS3, coupling occurs between the control gates and the channels of the fourth to sixth memory cells MC4 to MC 6. Due to this coupling, the voltages (or potentials) of the channels of the fourth to sixth memory cells MC4 to MC6 may be higher than the voltages supplied from the selected first bit line BL1 to the drain of the sixth memory cell MC 6. At this time, the string selection transistors SST1a and SST1b are turned off. In other words, the channels of the fourth to sixth memory cells MC4 to MC6 are isolated from the first bit line BL1 and float between the turned-off memory cell MC3 and the turned-off string selection transistors SST1a and SST1 b.

For example, the third string selection line voltage VSSL3 and the third bit line voltage VBL3 may have substantially the same level. At this time, the voltage transmitted to the drain of the memory cell MC6 may have a level obtained by subtracting the threshold voltages of the string selection transistors SST1a and SST1b from the third string selection line voltage VSSL3 or the third bit line voltage VBL 3. In this case, if the drain voltage of the sixth memory cell MC6 increases, the on condition of the string selection transistors SST1a and SST1b is not satisfied, so that the string selection transistors SST1a and SST1b are turned off.

After the string selection transistors SST1a and SST1b are turned off, the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 further increase due to the coupling effect. In other words, the channels of the fourth to sixth memory cells MC4 to MC6 are floated, and the voltage (or potential) of the floated channels is raised. For example, the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 may be increased to the boosting voltage VBOOST. In other words, the boosting voltage VBOOST is supplied to the drain of the selected third memory cell MC 3.

Since the third pass voltage VPASS3 is supplied to the first and second word lines WL1 and WL2, the third ground select line voltage VGSL3 is supplied to the ground select lines GSLa and GSLb, and thus the ground select transistors GSTa and GSTb and the first and second memory cells MC1 and MC2 are turned on. Accordingly, the third common source line voltage VCSL supplied to the common source line CSL is transmitted to the source of the selected third memory cell MC3 through the ground selection transistors GSTa and GSTb and the first and second memory cells MC1 and MC 2.

Due to a voltage difference between the boost voltage VBOOST supplied to the drain of the third memory cell MC3 and the third common line voltage VCSL3 supplied to the source of the third memory cell MC3, hot holes occur around/in the third memory cell MC 3. In an embodiment, the third program voltage VPGM3 may have a level that causes hot holes in the third memory cell MC 3. For example, the third program voltage VPGM3 may have a lower level than the boosting voltage VBOOST and the third common line voltage VCSL 3. The third program voltage VPGM3 may be a negative voltage. Since the third program voltage VPGM3 is applied to the control gate of the third memory cell MC3, hot holes are injected into the third memory cell MC 3. In other words, the threshold voltage of the third memory cell MC3 decreases.

When the verifying step and the programming step of fig. 8 are repeatedly performed, the level of the third programming voltage VPGM3 may be gradually increased or decreased. When the verifying step and the programming step of fig. 8 are repeatedly performed, the level of the third pass voltage VPASS3 gradually increases or decreases, so that the level of the boosting voltage VBOOST may gradually increase or decrease.

Fig. 11 to 13 illustrate voltages applied to unselected cell strings CS12, CS21, and CS22 in a second program operation according to an exemplary embodiment of the inventive concept. In fig. 11 to 13, the cell strings CS12, CS21, and CS22 are shown on the right side, and voltage (or potential) graphs of the channels of the cell transistors of the cell strings CS12, CS21, and CS22 are shown on the left side. In each voltage (or potential) graph, the horizontal axis represents the voltage Vch of the channel and the vertical axis represents the location (position) of the cell transistor.

Referring to fig. 2, 9 and 11, in the unselected cell string CS12, the third program voltage VPGM3 is applied to the selected third word line WL3. Therefore, the third memory cell MC3 is turned off.

The third string selection line voltage VSSL3 is applied to the selected string selection lines SSL1a and SSL1b. Accordingly, the string selection transistors SST1a and SST1b are turned on. The third pass voltage VPASS3 is supplied to the fourth to sixth word lines WL4 to WL6. Accordingly, the fourth to sixth memory cells MC4-MC6 are turned on.

The fourth bit line voltage VBL4 is supplied to the unselected second bit line BL2. The fourth bit line voltage VBL4 is supplied to channels of the fourth to sixth memory cells MC4 to MC6 through the string selection transistors SSTa and SSTb. Since the fourth bit line voltage VBL4 is a low voltage, if coupling occurs in the control gates of the fourth through sixth memory cells MC4-MC6, the voltages of the channels of the fourth through sixth memory cells MC4-MC6 do not increase to turn off the string selection transistors SSTa and SSTb. Therefore, the boosting described with reference to fig. 10 does not occur, and the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 become the fourth bit line voltage VBL4.

Since the third pass voltage VPASS3 is supplied to the first and second word lines WL1 and WL2 and the third ground select line voltage VGSL3 is applied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb and the first and second memory cells MC1 and MC2 are turned on. Accordingly, the third common source line voltage VCSL3 supplied to the common source line CSL is transmitted to the source of the selected third memory cell MC3 through the ground selection transistors GSTa and GSTb and the first and second memory cells MC1 and MC 2.

The voltage difference between the fourth bit line voltage VBL4 supplied to the drain of the third memory cell MC3 and the third common source line voltage VCSL3 supplied to the source of the third memory cell MC3 does not cause hot holes. In other words, in the unselected cell string CS12, the programming of the third memory cell MC3 is inhibited by preventing the boosting of the drain voltage of the third memory cell MC 3.

Referring to fig. 2, 9 and 12, in the unselected cell string CS21, the third program voltage VPGM3 is applied to the selected third word line WL3. Therefore, the third memory cell MC3 is turned off.

The fourth string selection line voltage VSSL4 is applied to the unselected string selection lines SSL2a and SSL2b. Thus, the string select transistors SSTa and SSTb are turned on. The third pass voltage VPASS3 is supplied to the fourth to sixth word lines WL4 to WL6. Accordingly, the fourth to sixth memory cells MC4-MC6 are turned on.

The third bit line voltage VBL3 is supplied to the selected first bit line BL1. The third bit line voltage VBL3 is supplied to channels of the fourth to sixth memory cells MC4 to MC6 through the string selection transistors SSTa and SSTb. The fourth string selection line voltage VSSL4 is a high voltage higher than the third string selection line voltage VSSL 3. For example, the fourth string selection line voltage VSSL4 may be set high enough so that the string selection transistors SSTa and SSTb are not turned off when the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 are increased due to coupling from the control gates. Therefore, boosting described with reference to fig. 10 does not occur, and the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 become the third bit line voltage VBL3.

Since the third pass voltage VPASS3 is supplied to the first and second word lines WL1 and WL2, the third ground select line voltage VGSL3 is applied to the ground select lines GSLa and GSLb, and thus the ground select transistors GSTa and GSTb and the first and second memory cells MC1 and MC2 are turned on. Accordingly, the third common source line voltage VCSL3 supplied to the common source line CSL is transmitted to the source of the selected third memory cell MC3 through the ground selection transistors GSTa and GSTb and the first and second memory cells MC1 and MC 2.

The voltage difference between the third bit line voltage VBL3 supplied to the drain of the third memory cell MC3 and the third common source line voltage VCSL3 supplied to the source of the third memory cell MC3 is insufficient to cause hot holes. In other words, in the unselected cell string CS21, the programming of the third memory cell MC3 is inhibited by preventing the boosting of the drain voltage of the third memory cell MC 3.

Referring to fig. 2, 9 and 13, in the unselected cell string CS22, the third program voltage VPGM3 is applied to the selected third word line WL3. Therefore, the third memory cell MC3 is turned off.

The fourth bit line voltage VBL4 is supplied to the unselected second bit line BL2. The fourth bit line voltage VBL4 is supplied to channels of the fourth to sixth memory cells MC4 to MC6 through the string selection transistors SSTa and SSTb. The fourth string selection line voltage VSSL4 is a high voltage higher than the third string selection line voltage VSSL3, and the fourth bit line voltage VBL4 is a low voltage lower than the third bit line voltage VBL 3. Therefore, when the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 are increased due to coupling from their control gates, the string selection transistors SSTa and SSTb are not turned off. Therefore, boosting described with reference to fig. 10 does not occur, and the voltages of the channels of the fourth to sixth memory cells MC4 to MC6 become the fourth bit line voltage VBL4.

The voltage difference between the fourth bit line voltage VBL4 supplied to the drain of the third memory cell MC3 and the third common source line voltage VCSL3 supplied to the source of the third memory cell MC3 does not cause hot holes. In other words, in the unselected cell string CS22, the programming of the third memory cell MC3 is inhibited by preventing the boosting of the drain voltage of the third memory cell MC 3.

Fig. 14 is a table illustrating voltages supplied to a memory block in a second program operation according to an exemplary embodiment of the inventive concept. Fig. 14 shows an example of voltages when the second programming is performed in the local selection transistors GSTa and GSTb.

Referring to fig. 2 and 14, the fifth bit line voltage VBL5 is applied to the selected bit line. The fifth bit line voltage VBL5 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage. The sixth bit line voltage VBL6 is applied to the unselected bit lines. The sixth bit line voltage VBL6 may be a ground voltage or a low voltage having a level similar to the ground voltage.

The fifth string selection line voltage VSSL5 is applied to the selected string selection line. The fifth string selection line voltage VSSL5 may be a voltage that turns on the string selection transistor. The fifth string selection line voltage VSSL5 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage. The fifth string selection line voltage VSSL5 may have substantially the same level as the fifth bit line voltage VBL 5. The sixth string selection line voltage VSSL6 is applied to the unselected string selection lines. The sixth string selection line voltage VSSL6 may be a voltage that turns on the string selection transistor. The sixth string selection line voltage VSSL6 may be a power supply voltage or a high voltage having a higher level than the fifth string selection line voltage VSSL 5. The sixth string selection line voltage VSSL6 may be a high voltage that prevents boosting.

The fourth over-voltage VPASS4 is applied to the word lines WL1-WL6. The fourth over-voltage VPASS4 may be a voltage that turns on the first through sixth memory cells MC1 through MC 6. The fourth over-voltage VPASS4 may be a supply voltage or to a high voltage higher than the fifth string selection line voltage VSSL 5.

The fourth program voltage VPGM4 is applied to the selected ground select line. The fourth program voltage VPGM4 may have a level that causes hot hole injection in the ground select transistor, which is one of the ground select transistors GSTa connected to the selected ground select line that allows programming thereof. The fourth program voltage VPGM4 may have a lower level than the third common source line voltage VCSL 3. The fourth program voltage VPGM4 may have a level sufficient to turn off the ground select transistor GSTa.

The fourth ground select line voltage VGSL4 is applied to the unselected ground select lines. The fourth ground selection line voltage VGSL4 may be a voltage that turns on the ground selection transistor. The fourth ground selection line voltage VGSL4 may be a supply voltage or a high voltage having a level similar to or higher than the supply voltage.

The common source line voltage VCSL4 is applied to the common source line CSL. The common source line voltage VCSL4 may be a ground voltage or a low voltage having a level similar to the ground voltage.

As described with reference to fig. 7, the first program operation is performed in the ground selection transistor GSTa connected to the ground selection line GSLa. Further, in the ground selection transistor GSTa, the threshold voltage of the ground selection transistor GSTa belonging to the cell string CS11 is higher than the verify voltage VFYu, and the threshold voltages of the ground selection transistors GSTa belonging to the remaining cell strings CS12, CS21, and CS22 are lower than the verify voltage VFYu. In other words, the string selection lines SSL1a and SSL1b and the bit line BL1 corresponding to the cell string CS11 are selected, and the string selection lines SSL2a and SSL2b and the bit line BL2 not corresponding to the cell string CS11 are not selected.

Fig. 15 illustrates voltages applied to a selected cell string in a second program operation according to an exemplary embodiment of the inventive concept. In fig. 15, the cell string CS11 is shown on the right side, and a voltage (or potential) graph of the channel of the cell transistor of the cell string CS11 is shown on the left side. In the voltage (or potential) graph, the horizontal axis represents the voltage Vch of the channel, and the vertical axis represents the positioning (position) of the cell transistor.

Referring to fig. 2, 14 and 15, a fourth program voltage VPGM4, which is a negative voltage, is applied to the selected ground select line GSLa. Thus, the ground select transistor GSTa is turned off. For example, the channel of the ground select transistor GSTa has a first type (e.g., p-type). The voltage of the channel of ground select transistor GSTa may decrease due to the coupling between the control gate and the channel of ground select transistor GSTa.

The fifth string selection line voltage VSSL5 is applied to the selected string selection lines SSL1a and SSL1b. In an initial state where the fifth string selection line voltage VSSL5 is applied, the string selection transistors SST1a and SST1b may be turned on.

The fifth bit line voltage VBL5 is supplied to the selected first bit line BL1. The fifth bit line voltage VBL5 may be transmitted to the memory cell MC6 through the channels of the turned-on string selection transistors SSTa and SSTb.

If the fourth over-voltage VPASS4 is applied to the first to sixth word lines WL1 to WL6, the first to sixth memory cells MC1 to MC6 are turned on. For example, the channels of the first to sixth memory cells MC1 to MC6 have a second type (e.g., n-type). If the fourth ground selection line voltage VGSL4 is applied to the ground selection line GSLb, the ground selection transistor GSTb is turned on. For example, the channel of the ground select transistor GSTb has the second type. Since the ground selection transistor GSTa is turned off, the voltage transferred from the selected bit line BL1 to the drain of the sixth memory cell MC6 is transferred to the first to sixth memory cells MC1 to MC6 and the channel of the ground selection transistor GSTb.

After the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb are turned on, since the voltages of the control gates of the first to sixth memory cells MC1 to MC6 are raised to the target level of the fourth over-voltage VPASS4 and the voltage of the control gate of the ground selection line GSLb is raised to the target level of the fourth ground selection line voltage VGSL4, coupling occurs between the control gates and the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb. Due to this coupling, the voltages of the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb may be higher than the voltage supplied from the first bit line VBL1 to the drain of the sixth memory cell MC 6. At this time, the string selection transistors SST1a and SST1b are turned off. In other words, the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb are isolated from the first bit line BL1 and float between the turned-off ground selection transistor GSTa and the string selection transistors SST1a and SST1 b.

The fifth string selection line voltage VSSL5 and the fifth bit line voltage VBL5 may have substantially the same level. The voltage transmitted to the drain of the memory cell MC6 may have a level obtained by subtracting the threshold voltages of the string selection transistors SST1a and SST1b from the fifth string selection line voltage VSSL5 or the fifth bit line voltage VBL 5. In this case, if the drain voltage of the memory cell MC6 increases due to coupling, the on condition of the string selection transistors SST1a and SST1b is not satisfied, and thus the string selection transistors SST1a and SST1b are turned off.

After the string selection transistors SST1a and SST1b are turned off, the voltages of the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb are further increased due to the coupling effect. In other words, the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb are floated, and the voltage of the floated channels is raised. For example, the voltages of the channels of the first to sixth memory cells MC1 to MC6 and the ground selection transistor GSTb may be raised to the boosting voltage VBOOST. In other words, the boost voltage VBOOST is supplied to the drain of the selected ground selection transistor GSTa.

The fourth common source line voltage VCSL4 supplied to the common source line CSL is transmitted to the source of the selected ground selection transistor GSTa.

Hot holes occur around/in the ground selection transistor GSTa due to a voltage difference between the boost voltage VBOOST supplied to the drain of the ground selection transistor GSTa and the fourth common-source line voltage VCSL4 supplied to the source of the ground selection transistor GSTa. Since the fourth program voltage VPGM4 is applied to the control gate of the ground selection transistor GSTa, hot holes are injected into the ground selection transistor GSTa. In other words, the threshold voltage of the ground select transistor GSTa decreases.

In the unselected cell strings CS12, CS21, and CS22, as described with reference to fig. 11 to 13, the programming of the ground selection transistor GSTa can be inhibited by preventing the voltage of the drain of the ground selection transistor GSTa from being boosted.

The ground select transistor GSTb is programmed in a similar manner. For example, in the selected cell string, the drain voltage of the ground selection transistor GSTb is boosted. The low voltage supplied to the common source line CSL is transmitted to the source of the ground selection transistor GSTb. If the fourth program voltage VPGM4 is supplied to the ground selection transistor GSTb, the threshold voltage of the ground selection transistor GSTb of the selected cell string is lowered.

In the unselected cell strings, the voltage of the drain of the ground selection transistor GSTb is prevented from boosting. The low voltage supplied to the common source line CSL is transmitted to the source of the ground selection transistor GSTb. When the fourth program voltage VPGM4 is supplied to the ground select line GSLb, the threshold voltage of the ground select transistor GSTb of the unselected cell string is not lowered.

When the verifying step and the programming step of fig. 8 are repeatedly performed, the level of the fourth programming voltage VPGM4 may be gradually increased or decreased. When the verifying step and the programming step of fig. 8 are repeatedly performed, the level of the fourth pass voltage VPASS4 gradually increases or decreases, so that the level of the boosting voltage VBOOST may gradually increase or decrease.

Fig. 16 is a flowchart illustrating a second program operation according to an exemplary embodiment of the inventive concept. Referring to fig. 1 to 3 and 16, in step S410, a verification operation is performed using a verification voltage VFYu. If the verifying operation is performed, a first cell transistor having a threshold voltage lower than the verifying voltage VFYu and a second cell transistor having a threshold voltage higher than the verifying voltage VFYu are distinguished from each other among the cell transistors on which the first program operation is performed.

In step S420, it is determined whether the authentication operation has been passed. If it is determined that the verify operation has passed, the second programming operation may be completed. If the result of the verification operation is not determined to have passed, step S430 is performed. Steps S410 and S420 may be verification steps.

In step S430, programming of the first cell transistor having a lower threshold voltage than the verify voltage VFYu is inhibited. In step S440, the second transistor having a threshold voltage higher than the verify voltage VFYu is allowed to be programmed. After that, in step S450, a program voltage is supplied to the control gates of the first cell transistor and the second cell transistor. For example, the program voltage may be a voltage that causes hot hole injection in the second cell transistor.

In step S460, it is determined whether the maximum programming step is performed. For example, it may be determined whether the programming steps including steps S430 to S450 are performed a predetermined number of times.

As described with reference to fig. 10 to 15, in the second program operation, the threshold voltage of the selected cell transistor of the selected cell string is lowered by raising the drain voltage of the selected cell transistor of the selected cell string. The boost voltage is gradually reduced due to peripheral effects (PERIPHERAL EFFECT) such as leakage current. If the boosting voltage is gradually lowered, the programming efficiency of the selected cell transistor is lowered. In order to prevent the programming efficiency from being lowered due to the lowering of the boosting voltage, the programming steps including steps S430 to S450 may be performed several times.

For example, after the kth programming step is performed, the selected cell string may be restored. For example, the channel voltage of the cell transistor of the cell string of the memory block BLKa may be discharged. After that, after the verifying step, the voltages described with reference to fig. 9 or 14 are applied again so that the (k+1) -th programming step can be performed.

The voltage conditions may be controlled as the programming steps are repeatedly performed. For example, the level of the programming voltage applied to the control gate of the selected cell transistor may be increased or decreased. The level of the pass voltage VPASS applied to the unselected word lines increases or decreases, so that the level of the boost voltage VBOOST may increase or decrease. The level of the low voltage applied to the common source line CSL may be increased or decreased.

Fig. 17 is a timing diagram illustrating control of a level of a pass voltage in a second program operation according to an exemplary embodiment of the inventive concept. In fig. 17, the horizontal axis represents time T, and the vertical axis represents the level of pass voltage VPASS. An example of controlling the level of the pass voltage VPASS in the programming step of fig. 16 is shown in fig. 17.

Referring to fig. 17, a pass voltage VPASS is applied to the word line WL at a first time T1. After that, at the second, third, fourth, and fifth times T2, T3, T4, and T5, the level of the pass voltage VPASS increases. After that, at a sixth time T6, the pass voltage VPASS discharges.

As described with reference to fig. 16, the level of the boost voltage VBOOST gradually decreases with the lapse of time. As shown in fig. 17, if the level of the pass voltage VPASS gradually increases, the level of the boost voltage VBOOST gradually increases due to coupling. In other words, the decrease and increase of the boosting voltage VBOOST cancel each other out, so that the level of the boosting voltage VBOOST is maintained when the programming step of the second programming operation is performed.

Although the programming steps of the second programming operation are repeatedly performed as described with reference to fig. 16, the level of the pass voltage VPASS in each programming step may be controlled as described with reference to fig. 17.

Fig. 18 is a flowchart illustrating an operation method of a nonvolatile memory according to an exemplary embodiment of the inventive concept. Referring to fig. 1,2 and 18, in step S510, a first program operation is performed to raise a threshold voltage of a cell transistor. For example, the threshold voltage of the cell transistor selected as the program target may be increased.

In step S520, a second program operation is performed to lower the threshold voltage of the cell transistor having a higher threshold voltage than the verify voltage VFYu among the cell transistors. For example, the threshold voltage of a cell transistor having a higher threshold voltage than the verify voltage VFYu among the cell transistors on which the first program operation is performed may be lowered by the second program operation. For example, the verify voltage VFYu may be the upper end of the target threshold voltage range of the cell transistor.

In step S530, it is determined that the maximum number of iterations has been reached. For example, it is determined whether a predetermined number of first and second program operations have been performed. If the first and second program operations have not been performed a predetermined number of times, steps S510 and S520 are repeated, and thus, the first and second program operations are performed again. If the first programming operation and the second programming operation have been performed a predetermined number of times, programming of the cell transistor is completed.

If the operation of increasing the threshold voltage of the cell transistor through the first program operation and the operation of decreasing the threshold voltage of the cell transistor having the threshold voltage higher than the verify voltage VFYu through the second program operation are repeatedly performed, the threshold voltage distribution of the cell transistor may be decreased.

When the first program operation is repeatedly performed, voltages applied to the cell strings CS11, CS12, CS21, and CS22 may be changed. For example, the level of the program voltage VPGM may gradually increase.

When the second programming operation starts, voltages applied to the cell strings CS11, CS12, CS21, and CS22 may be initialized to initial values.

Fig. 19 is a flowchart illustrating an operation method of the nonvolatile memory 110 according to an exemplary embodiment of the inventive concept. Referring to fig. 1,2 and 19, in step S610, a first program operation is performed to raise a threshold voltage of a cell transistor. For example, the overall threshold voltage of the cell transistor selected as the programming target may be increased.

In step S620, a second program operation is performed to lower the threshold voltage of the cell transistor having a higher threshold voltage than the verify voltage VFYu among the cell transistors. For example, the threshold voltage of a cell transistor having a higher threshold voltage than the verify voltage VFYu among the cell transistors on which the first program operation is performed may be lowered by the second program operation. For example, the verify voltage VFYu may be the upper end of the target threshold voltage range of the cell transistor.

In step S630, a verification operation is performed on the cell transistor using the verification voltage VFYl. For example, if there are cell transistors having a threshold voltage lower than the verification voltage VFYl or the number of cell transistors having a threshold voltage lower than the verification voltage VFYl among the cell transistors is greater than a predetermined value, it may be determined that the verification operation has failed. If there are no cell transistors having a threshold voltage lower than the verify voltage VFYl or the number of cell transistors having a threshold voltage lower than the verify voltage VFYl among the cell transistors is not greater than a predetermined value, it may be determined that the result of the verify operation has passed.

In step S640, if the verifying operation is determined to have passed, programming of the cell transistor is completed. If the verification operation is determined to have failed, steps S610 to S630 are performed again.

If the number of times steps S610 to S630 are repeatedly performed reaches a predetermined threshold, it may be determined that programming of the cell transistor is completed and an error occurs.

Fig. 20 illustrates a change in threshold voltage of a cell transistor in the operation method of fig. 19 according to an exemplary embodiment of the inventive concept. In fig. 20, the horizontal axis represents the threshold voltage Vth of the cell transistor, and the vertical axis represents the number of cell transistors. In other words, fig. 20 shows the threshold voltage distribution of the cell transistor.

Referring to fig. 1,2, 19 and 20, an initial threshold voltage distribution of the cell transistor may be represented by a first line L1.

If the first program operation of step S610 is performed, the threshold voltage of the cell transistor is increased. For example, the threshold voltage distribution of the cell transistor may be changed from the first line L1 to the second line L2.

If the second program operation of step S620 is performed, the threshold voltage of the cell transistor having a higher threshold voltage than the verify voltage VFYu is lowered. For example, the threshold voltage higher than the verify voltage VFYu may become lower than the verify voltage VFYu. The first and second program operations are performed until the threshold voltage of the cell transistor is equal to or higher than the verify voltage VFY1. In other words, the threshold voltage distribution of the cell transistor may be changed from the second line L2 to the third line L3.

As described above, if the first and second program operations are performed, the threshold voltage distribution of the cell transistor is narrowed, and in particular, the threshold voltage of the cell transistor is limited to a range between the verify voltage VFYu and the verify voltage VFY 1. Since the threshold voltage of the cell transistor is controlled within the target range, the reliability of the nonvolatile memory 110 including the cell transistor is improved.

Fig. 21 is a block diagram illustrating a storage device according to an exemplary embodiment of the inventive concept. Referring to fig. 21, the storage device 100 includes a nonvolatile memory 110, a memory controller 120, and a Random Access Memory (RAM) 130.

The nonvolatile memory 110 is capable of performing write, read, and erase operations under the control of the memory controller 120. The nonvolatile memory 110 is capable of exchanging first DATA1 with the memory controller 120. For example, the nonvolatile memory 110 can receive the first DATA1 from the memory controller 120 and write the first DATA1. The nonvolatile memory 110 is capable of performing a read operation and outputting the read first DATA1 to the memory controller 120.

The nonvolatile memory 110 is capable of receiving a first command CMD1 and a first address ADDR1 from the memory controller 120. The nonvolatile memory 110 is capable of exchanging control signals CTRL with the memory controller 120. For example, the non-volatile memory 110 can receive at least one of the following signals: a chip select signal/CE selecting at least one semiconductor chip among the plurality of semiconductor chips constituting the nonvolatile memory 110, a command latch enable signal CLE indicating that the signal received from the memory controller 120 is a first command CMD1, an address latch enable signal ALE indicating that the signal received from the memory controller 120 is a first address ADDR1, a read enable signal/RE generated by the memory controller 120 in a read operation and periodically triggered for adjusting a timing, a write enable signal/WE activated by the memory controller 120 when the first command CMD1 or the first address ADDR1 is transmitted, a write prevention signal/WP activated by the memory controller 120 to prevent unwanted erasure or unwanted writing when power is changed, and a DATA strobe signal DQS generated by the memory controller 120 and periodically triggered for adjusting input synchronization of first DATA1 from the memory controller 120 in a write operation. For example, the nonvolatile memory 110 can output at least one of a ready & busy signal R/nB indicating whether the nonvolatile memory 110 performs a program, erase, or read operation and a DATA strobe signal DQS generated from a read enable signal/RE by the nonvolatile memory 110 and periodically triggered for adjusting output synchronization of the first DATA1 to the memory controller 120.

The first DATA1, the first address ADDR1, and the first command CMD1 can communicate with the memory controller 120 through the first channel CH 1. The first channel CH1 may be an input/output channel. The control signal CTRL can communicate with the memory controller 120 through a second channel. The second channel CH2 may be a control channel.

The nonvolatile memory 110 has the structure described with reference to fig. 1 to 20 and may operate according to the method described with reference to fig. 1 to 20. For example, the nonvolatile memory 110 can perform a first program operation of raising a threshold voltage of a cell transistor and a second program operation of lowering a threshold voltage of a cell transistor having a threshold voltage higher than a verify voltage among programmed cell transistors.

The non-volatile memory 110 may include flash memory. However, the nonvolatile memory 110 is not limited to including a flash memory. The nonvolatile memory 110 may include at least one of various nonvolatile memories such as a phase change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a ferroelectric RAM (FeRAM), and the like.

The memory controller 120 is configured to control the nonvolatile memory 110. For example, the memory controller 120 can control the nonvolatile memory 110 to perform a write, read, or erase operation. The memory controller 120 is capable of exchanging the first DATA1 and the control signal CTRL with the nonvolatile memory 110 and outputting the first command CMD1 and the first address ADDR1 to the nonvolatile memory 110.

The memory controller 120 is capable of controlling the nonvolatile memory 110 under the control of an external host device. The memory controller 120 is capable of exchanging second DATA2 with the external host device and receiving a second command CMD2 and a second address ADDR2 from the external host device.

The memory controller 120 is capable of exchanging the first DATA1 with the nonvolatile memory 110 through a first unit (e.g., a time unit or a DATA unit) and exchanging the second DATA2 with the external host device through a second unit (e.g., a time unit or a DATA unit) different from the first unit.

The memory controller 120 can exchange the first DATA1 with the nonvolatile memory 110 according to the first format and transmit the first command CMD1 and the first address ADDR1 to the nonvolatile memory 110. The memory controller 120 is capable of exchanging second DATA2 with the external host device according to a second format different from the first format and receiving a second command CMD2 and a second address ADDR2 from the external host device.

The memory controller 120 can use the RAM130 as a buffer memory, a cache (cache) memory, or an operation memory. For example, the memory controller 120 can receive the second DATA2 from the external host device, store the received second DATA2 in the RAM130 and write the second DATA2 stored in the RAM130 as the first DATA1 into the nonvolatile memory 110. The memory controller 120 is capable of reading the first DATA1 from the nonvolatile memory 110, storing the read first DATA1 in the RAM130, and outputting the first DATA1 stored in the RAM130 as second DATA2 to an external host device. The memory controller 120 can store data read from the nonvolatile memory 110 in the RAM130 and write the data stored in the RAM130 into the nonvolatile memory 110 again.

The memory controller 120 can store data or code for managing the nonvolatile memory 110 in the RAM 130. For example, the memory controller 120 can read code or data for managing the nonvolatile memory 110 from the nonvolatile memory 110 and load it into the RAM 130 to drive the nonvolatile memory 110.

The memory controller 120 may include an Error Correction Code (ECC) block 124. The ECC block 124 can generate parity based on the first DATA1 written into the nonvolatile memory 110. The generated parity can be written to the nonvolatile memory 110 together with the first DATA 1. The operation of generating the parity may be an error correction coding operation. The ECC block 124 can receive the first DATA1 and the parity from the nonvolatile memory 110. The ECC block 124 can correct errors of the first DATA1 using the received parity. The operation of correcting the error may be an error correction decoding operation.

In an error correction decoding operation, the ECC block 124 can perform simplified error correction or complete error correction. The simplified error correction may be error correction with reduced error correction time. The complete error correction may be one with higher reliability. The ECC block 124 can improve the operation speed and reliability of the storage device 100 by selectively performing simplified error correction or complete error correction.

The RAM 130 may include at least one of various random access memories such as Dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, feRAM, etc.

To reduce the overhead incurred in the erase operation in the non-volatile memory 110, the memory device 100 may perform address mapping. For example, when an external host device requests an over-write operation, the storage device 100 may store the over-write request data in the memory cells of the free storage space, instead of erasing the memory cells storing the existing data to store the over-write request data in the erased memory cells. The memory controller 120 can drive a flash translation layer (flash translationlayer, FTL) that maps logical addresses used in the external host device and physical addresses used in the nonvolatile memory 110 according to the above-described method. For example, the second address ADDR2 may be a logical address and the first address ADDR1 may be a physical address.

The storage device 100 is capable of performing a writing, reading, or erasing operation of data according to a request of an external host device. The storage device 100 may include a Solid State Drive (SSD) or a Hard Disk Drive (HDD). The storage device 100 may include a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, compact Flash (CF) card, smart media card (SM, SMC), memory stick, multimedia card (MMC, reduced Size (RS) -MMC, mmcmmicro), secure Digital (SD) card (SD, miniSD, microSD, secure Digital High Capacity (SDHC)), universal flash device (UFS), and the like. The storage device 100 may include an installed memory such as an embedded multimedia card (eMMC), UFS, perfect page new (PERFECTPAGE NEW, PPN), etc.

Fig. 22 is a block diagram illustrating a memory controller according to an exemplary embodiment of the inventive concept. Referring to fig. 22, the memory controller 120 includes a bus 121, a processor 122, a RAM 123, an ECC block 124, a host interface 125, a buffer control circuit 126, and a memory interface 127.

The bus 121 is configured to provide a channel between constituent elements of the memory controller 120.

The processor 122 is capable of controlling the overall operation of the memory controller 120 and performing logical operations. The processor 122 is capable of communicating with an external host device through the host interface 125. The processor 122 can store the second command CMD2 and the second address ADDR2 received through the host interface 125 in the RAM 123. The processor 122 is capable of generating a first command CMD1 and a first address ADDR1 from the second command CMD2 and the second address ADDR2 stored in the RAM 123, and outputting the generated first command CMD1 and first address ADDR1 through the memory interface 127.

The processor 122 can output the second DATA2 received through the host interface 125 through the buffer control circuit 126 or store the second DATA2 in the RAM 123. The processor 122 can output DATA stored in the RAM 123 or DATA received through the buffer control circuit 126 as first DATA1 through the memory interface 127. The processor 122 can store the first DATA1 received through the memory interface 127 in the RAM 123 or output the first DATA1 through the buffer control circuit 126. The processor 122 can output the DATA stored in the RAM 123 or the DATA received through the buffer control circuit 126 as the second DATA2 through the host interface 125, or output the DATA stored in the RAM 123 or the DATA received through the buffer control circuit 126 as the first DATA1 through the memory interface 127.

The RAM 123 may be used as an operation memory, a cache memory, or a buffer memory of the processor 122. RAM 123 is capable of storing code and commands that are executed by processor 122. RAM 123 is capable of storing data processed by processor 122. RAM 123 may comprise SRAM.

The ECC block 124 can perform an error correction operation. The ECC block 124 can generate an error correction code (e.g., parity) for performing error correction based on the first DATA1 to be output to the memory interface 127 or the second DATA2 received from the host interface 125. The first DATA1 and the parity can be output through the memory interface 127. The ECC block 124 can perform error correction of the received first DATA1 using the first DATA1 received through the memory interface 127 and the parity. The ECC block 124 may be included in the memory interface 127 as a constituent element of the memory interface 127.

The host interface 125 is configured to communicate with an external host device under control of the processor 122. The host interface 125 is capable of receiving a second command CMD2 and a second address ADDR2 from the external host device, and exchanging second DATA2 with the external host device.

The host interface 125 may be configured to perform communications using at least one of a number of different communications methods, such as Universal Serial Bus (USB), serial Advanced Technology Attachment (SATA), serial attached small computer system interface (SAS), high speed chip interconnect (HSIC), small Computer System Interface (SCSI), firewire, peripheral Component Interconnect (PCI), PCI express (PCIe), nonvolatile memory express (NVMe), UFS, SD, MMC, eMMC, and the like.

The buffer control circuit 126 is configured to control the RAM 130 (refer to fig. 21) under the control of the processor 122. The buffer control circuit 126 is capable of writing data in the RAM 130 and reading data from the RAM 130.

The memory interface 127 is configured to communicate with the nonvolatile memory 110 (see fig. 1) under the control of the processor 122. The memory interface 127 is capable of transmitting a first command CMD1 and a first address ADDR1 to the nonvolatile memory 110 and exchanging first DATA1 and a control signal CTRL with the nonvolatile memory 110.

The RAM 130 may not be provided to the storage device 100. In other words, the memory device 100 may not have separate memories located outside the memory controller 120 and the nonvolatile memory 110. In this case, the buffer control circuit 126 may not be provided to the memory controller 120. The functions of RAM 130 may be performed by internal RAM 123 of memory controller 120.

As an example, the processor 122 can control the memory controller 120 using code. The processor 122 is capable of loading code from a non-volatile memory (e.g., read only memory) disposed within the memory controller 120. As another example, the processor 122 can load code received from the memory interface 127.

The bus 121 of the memory controller 120 may be divided into a control bus and a data bus. The data bus may be configured to transmit data in the memory controller 120, and the control bus may be configured to transmit control information such as commands, addresses, etc. in the memory controller 120. The data bus and the control bus may be separate from each other and may not interfere or affect each other. The data bus may be connected to a host interface 125, a buffer control circuit 126, an ECC block 124, and a memory interface 127. The control bus may be connected to a host interface 125, a processor 122, a buffer control circuit 126, a RAM 123, and a memory interface 127.

Fig. 23 is a block diagram illustrating a computing device 1000 according to an exemplary embodiment of the inventive concept. Referring to fig. 23, a computing device 1000 includes a processor 1100, RAM 1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 is capable of controlling the overall operation of the computing device 1000 and performing logical operations. For example, the processor 1100 may be constructed in a system-on-a-chip (SoC). The processor 1100 may be a general purpose processor, a special purpose processor, or an application processor.

RAM 1200 can communicate with processor 1100. RAM 1200 may be the main memory of processor 1100 or computing device 1000. The processor 1100 may temporarily store code or data in the RAM 1200. The processor 1100 is capable of executing code and processing data using the RAM 1200. The processor 1100 is capable of executing various software such as an operating system, applications, and the like using the RAM 1200. The processor 1100 is capable of controlling the overall operation of the computing device 1000 using the RAM 1200. The RAM 1200 may include volatile memory such as SRAM, DRAM, SDRAM or nonvolatile memory such as PRAM, MRAM, RRAM, feRAM.

The storage device 1300 is capable of communicating with the processor 1100. The storage device 1300 can store data to be retained for a long time. In other words, the processor 1100 can store data to be retained for a long time in the storage device 1300. Storage device 1300 is capable of storing a boot image for driving computing device 1000. The storage 1300 is capable of storing source code for various software such as an operating system, applications, and the like. The storage device 1300 can store data processed by various software such as an operating system, applications, and the like.

The processor 1100 is capable of driving various software such as an operating system, applications, and the like by loading source code stored in the storage device 1300 into the RAM1200 and then executing the source code loaded into the RAM 1200. The processor 1100 can load data stored in the storage device 1300 into the RAM1200 and process the data loaded into the RAM 1200. The processor 1100 can load data to be retained for a long time among the data stored in the RAM1200 into the storage device 1300.

The memory device 1300 may include non-volatile memory such as flash memory, PRAM, MRAM, RRAM, feRAM, and the like.

The modem 1400 can communicate with external devices under the control of the processor 1100. For example, the modem 1400 can perform wired or wireless communication with an external device. The modem 1400 can perform communication based on at least one of various wireless communication methods such as Long Term Evolution (LTE), worldwide interoperability for microwave access (WiMax), global system for mobile communication (GSM), code Division Multiple Access (CDMA), bluetooth, near Field Communication (NFC), wireless fidelity (WiFi), radio Frequency Identification (RFID), or at least one of various wired communication methods such as USB, SATA, SCSI, firewire, PCI, PCIe, NVMe, UFS, SD, secure Digital Input Output (SDIO), universal Asynchronous Receiver Transmitter (UART), serial Peripheral Interface (SPI), high speed SPI (HS-SPI), RS232, inter integrated circuit (I2C), high Speed (HS) -I2C, integrated audio interface chip (I2S), sony/philips digital interface (S/PDIF), MMC, eMMC, etc.

The user interface 1500 is capable of communicating with a user under the control of the processor 1100. For example, the user interface 1500 may include a user input interface such as a keyboard, keypad, keys, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscopic sensor, vibration sensor, and the like. The user interface 1500 may include a user output interface such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Active Matrix OLED (AMOLED) display, a Light Emitting Diode (LED), a speaker, a motor, and the like.

The storage device 1300 may include the storage device 100 according to an exemplary embodiment of the inventive concept. The processor 1100, RAM 1200, modem 1400, and user interface 1500 can form a host device that communicates with the storage device 1300.

Fig. 24 illustrates a perspective view showing a structure of a memory block BLKa (refer to fig. 2) according to an embodiment of the inventive concept. Fig. 25 is a cross-sectional view illustrating a structure of a memory block BLKa according to an embodiment of the inventive concept. Referring to fig. 24 and 25, a substrate 111 is provided. In an embodiment, the substrate 111 may be a well having a first conductive type. For example, the substrate 111 may be a P-well formed by implanting a group 3 element such as boron into the substrate 111. For example, the substrate 111 may be a pocket-shaped P-well disposed in an N-well. Next, it is assumed that the substrate 111 is a P-well (or a pocket P-well). However, the substrate 111 is not limited to have a P-type.

A plurality of common source regions CSR extending in the first direction and spaced apart from each other in the second direction are disposed on the substrate 111. The plurality of common source regions CSR may be commonly connected to each other to form a common source line. The plurality of common source regions CSR may have a second conductive type different from the conductive type of the substrate 111. For example, the plurality of common source regions CSR may have an N-type. In the following, it is assumed that the plurality of common source regions CSR have an N-type. Hereinafter, the plurality of common source regions CSR are not limited to have an N type.

The plurality of insulating materials 112 and 112a are sequentially disposed on the substrate 111 in a third direction (i.e., a direction perpendicular to the substrate 111) between two common source regions adjacent to each other among the plurality of common source regions CSR. The plurality of insulating materials 112 and 112a may be spaced apart from each other in the third direction. The plurality of insulating materials 112 and 112a extend in a first direction. In an embodiment, the plurality of insulating materials 112 and 112a may include an insulating material such as a semiconductor oxide. In an embodiment, the thickness of the insulating material 112a in contact with the substrate 111 among the plurality of insulating materials 112 and 112a may be smaller than the thickness of the other insulating materials 112.

A plurality of pillars PL sequentially arranged in the first direction and penetrating the plurality of insulating materials 112 and 112a in the third direction are arranged between two adjacent common-source regions. In an embodiment, the plurality of pillars PL may be in contact with the substrate 111 through the insulating materials 112 and 112 a. In an embodiment, the pillars may be spaced apart from each other between two adjacent common-source regions in the first direction. The posts may be arranged in a line in a first direction.

Each of the plurality of columns PL includes a lower column PLa and an upper column PLb. The width of the lower column PLa may increase as the distance from the base 111 increases. The lower post PLa may comprise a variety of materials. For example, the lower column PLa may include a second information storage layer 116b, a channel layer 114, and an internal material 115 inside the channel layer 114. The second information storage layer 116b may include an insulating material such as silicon oxide, silicon nitride.

The upper portion of the lower column PLa may be filled with a silicon pad SP. The silicon pad SP may have the same conductive type as the channel layer 114. The silicon pad SP may have a P type or may be intrinsic silicon. The silicon pad SP may be provided to facilitate connection of the lower and upper pillars PLa and PLb.

The upper column PLb may be connected to the lower column PLa, specifically, to the silicon pad SP. The width of the upper column PLb may increase as the distance from the substrate increases. The upper column PLb may include a variety of materials. For example, the upper column PLb may include a second information storage layer 116b, a channel layer 114, and an internal material 115 inside the channel layer 114. The second information storage layer 116b may include an insulating material such as silicon oxide, silicon nitride.

The channel layer 114 may include a semiconductor material (e.g., silicon) having a first conductivity type. The channel layer 114 may include a semiconductor material (e.g., silicon) having the same conductivity type as the substrate 111. The channel layer 114 may include an intrinsic semiconductor having no conductivity type. The channel layer 114 may include a first channel layer 114a and a second channel layer 114b.

The inner material 115 may include an insulating material. For example, the interior material 115 may include an insulating material such as silicon oxide. For example, the interior material 115 may include an air gap. A first information storage layer 116a is disposed on the exposed surfaces of insulating materials 112 and 112a and pillars PL between two adjacent common-source regions. The first information storage layer 116a may include an insulating material such as silicon oxide, silicon nitride. The interior material 115 may include a first interior material 115a and a second interior material 115b.

Conductive materials CM1 to CM10 are disposed on exposed surfaces of first information storage layer 116a between two adjacent common source regions and between insulating materials 112 and 112 a. The conductive materials CM1 to CM10 may extend in the first direction. The conductive materials CM1 to CM10 may be separated by a word line Cut WL Cut on the common source region CSR. The word line Cut WL Cut may expose the common source region CSR. The word line slit WL Cut may extend in the first direction.

In an embodiment, the conductive materials CM1 to CM10 may include a metal conductive material. The conductive materials CM1 to CM10 may include a non-metallic conductive material such as polysilicon. In an embodiment, the first information storage layer 116a disposed on the upper surface of the uppermost one of the insulating materials 112 and 112a may be removed. In an embodiment, the first information storage layer 116a provided on the side surface facing the pillar PL among the side surfaces of the insulating materials 112 and 112a may be removed.

The plurality of drains 320 are disposed on the plurality of pillars PL. In an embodiment, the drain electrode 320 may include a semiconductor material (e.g., silicon) having a second conductivity type. For example, the drain electrode 320 may include a semiconductor material (e.g., silicon) having an N-type. Next, it is assumed that the drain electrode 320 includes N-type silicon. However, the drain electrode 320 is not limited to include N-type silicon. In an embodiment, drain 320 may extend onto channel layer 114 of pillar PL.

A plurality of bit lines BL extending in the second direction and spaced apart from each other in the first direction are disposed on the drain electrode 320. The bit line BL is connected to the drain 320. In an embodiment, the drain 320 and the bit line BL may be connected to each other through a contact plug (not shown). In an embodiment, the bit lines BL1 to BL2 may include a metal conductive material. In an embodiment, the bit lines BL1 through BL2 may include a non-metallic conductive material such as polysilicon.

The conductive materials CM1 to CM10 may have first to tenth heights according to the order from the substrate 111. The plurality of pillars PL form a plurality of cell strings together with the first information storage layer 116a and the plurality of conductive materials CM1 to CM 10. Each of the plurality of pillars PL forms one cell string with the first information storage layer 116a and the adjacent conductive materials CM1 to CM 10.

The pillars PL are disposed on the substrate 111 in the row direction and the column direction. The tenth conductive material CM10 may form rows. Pillars connected to the same tenth conductive material may form a row. The bit lines BL may form columns. Pillars connected to the same bit line may form a column. The pillars PL form a plurality of cell strings arranged in the row and column directions with the first information storage layer 116a and the plurality of conductive materials CM1 to CM 10.

The first information storage layer 116a and the second information storage layer 116b may be formed to form a tunnel insulating layer, a charge trapping layer, and a blocking insulating layer. At least one of a tunnel insulating layer, a charge trapping layer, and a blocking insulating layer may be included in the first information storage layer 116 a. At least another one of the tunnel insulating layer, the charge trapping layer, and the blocking insulating layer may be included in the second information storage layer 116 b.

In comparison to fig. 2, a first conductive material CM1 of a first height may form a ground select line GSLa and may form a control gate of a ground select transistor GSTa. The second conductive material CM2 of the second height may form a ground select line GSLb and may form a control gate of the ground select transistor GSTb. The third to eighth conductive materials CM3 to CM8 may form first to sixth word lines WL1 to WL6, respectively, and may form control gates of the first to sixth memory cells MC1 to MC 6.

The ninth conductive material CM9 of the ninth height may form string select lines SSL1a and SSL2a and may form a control gate of the string select transistor SSTa. The tenth conductive material CM10 of the tenth height may form string selection lines SSL1b and SSL2b and may form a control gate of the string selection transistor SSTb.

As shown in fig. 24 and 25, the structure of the connection portion where the lower and upper columns PLa and PLb are connected to each other is different from the structure of any other portion of the lower and upper columns PLa and PLb. For example, the channel layer 114 of the lower pillar PLa may not be directly connected to the channel layer 114 of the upper pillar PLb, but the channel layer 114 of the lower pillar PLa may be connected to the channel layer 114 of the upper pillar PLb through the silicon pad SP. The silicon pad SP may cause an effect similar to the expansion of the channel layer 114.

Since the structure of the connection portion is different from that of any other portion, the characteristics of the cell transistor corresponding to the connection portion may be different from those of the cell transistor corresponding to the other portion. Even if the same program, read, or erase voltage is applied, the change in threshold voltage of the cell transistor corresponding to the connection portion and the change in threshold voltage of the cell transistor corresponding to the other portion may be different. That is, the cell transistor corresponding to the connection portion may not be programmed, read, or erased by a normal programming, reading, or erasing method.

To prevent the above-described problem, the cell transistor corresponding to the connection portion may be used as a dummy memory cell. The dummy memory cells may not be used to program, read, or erase data. The dummy memory cell may provide only an on or off function to electrically connect or disconnect the channel layer 114 of the lower pillar PLa with the channel layer 114 of the upper pillar PLb.

Fig. 26 shows an example in which a cell transistor corresponding to a connection portion is used as a dummy memory cell. Referring to fig. 24 to 26, the first conductive material CM1 may form a ground selection line GSL and may form a control gate of the ground selection transistor GST. The second to fourth conductive materials CM2 to CM4 may form the first to third word lines WL1 to WL3, respectively, and may form control gates of the first to third memory cells MC1 to MC 3.

The fifth conductive material CM5 may form the dummy word line DWL and may form a control gate of the dummy memory cell DMC. The sixth to eighth conductive materials CM6 to CM8 may form fourth to sixth word lines WL4 to WL6 and may form control gates of the fourth to sixth memory cells MC4 to MC6, respectively. The ninth and tenth conductive materials are the same as those described above, and thus their description is omitted.

The fifth conductive material CM5 is shown in fig. 26 as forming the dummy word line DWL. However, embodiments of the inventive concept may not be limited thereto. For example, the fourth conductive material CM4 or the fourth and fifth conductive materials CM4 and CM5 may form one dummy word line or a plurality of dummy word lines. One conductive material CM1 is shown in fig. 26 as forming a ground select line. However, this shows modified examples included in the scope and spirit of the inventive concept without limiting the embodiments of the inventive concept.

The threshold voltages of the memory cells MC1 to MC6 are changed by a program operation and an erase operation. Data is written to the memory cells MC1 to MC6 by adjusting threshold voltages of the memory cells MC1 to MC6. The data written to the memory cells MC1 to MC6 is read by determining the threshold voltages of the memory cells MC1 to MC6. The data written into the memory cells MC1 to MC6 is erased by making the threshold voltages of the memory cells MC1 to MC6 have similar levels.

Fig. 27 shows changes in threshold voltages of the memory cells MC1 to MC6 when the program operation and the erase operation are performed on the memory cells MC1 to MC 6. In fig. 27, the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells. That is, fig. 27 shows the distribution of the threshold voltages of the memory cells MC1 to MC 6.

Referring to fig. 26 and 27, the erase operation adjusts the threshold voltages of the memory cells MC1 to MC6 such that the threshold voltages of the memory cells MC1 to MC6 are included in the erase state "E". The program operation adjusts the threshold voltages of the memory cells MC1 to MC6 such that the threshold voltages of the memory cells MC1 to MC6 are included in the erase state "E" and the first to seventh program states P1 to P7. If a program operation is performed, each memory cell may have a threshold voltage included in an erase state "E" and one of the first to seventh program states P1 to P7.

In an embodiment, when writing 3-bit data into one memory cell, the memory cell may be included in one of the erase state "E" and the first to seventh program states P1 to P7. When writing N-bit data (N is a positive integer) into one memory cell, each memory cell may be included in one of an erase state "E" and first through (2 ^N -1) th program states according to a program operation.

Fig. 28 is a flowchart showing a method of performing a program operation on the memory cells MC1 to MC 6. Referring to fig. 1, 26 and 28, in step S710, the nonvolatile memory 110 may receive a write command CMD1, an address ADDR1 and DATA1 from an external device (e.g., the memory controller 120 of fig. 21). In step S720, the nonvolatile memory 110 may load the received DATA1 onto the page buffer circuit 115.

In step S730, the nonvolatile memory 110 may perform a program operation to increase a threshold voltage of the memory cell selected by the address ADDR 1. As the program operation is performed, the threshold voltages of the memory cells included in the first to seventh program states P1 to P7 may be increased according to the write DATA 1. The voltage included in the memory cell in the erased state "E" can be maintained even if the program operation is performed on the basis of the write DATA 1.

In step S740, the nonvolatile memory 110 may perform a verification read operation. For example, the nonvolatile memory 110 may perform a verify-read operation by using first to mth verify voltages (M is an integer of 1 or more) corresponding to the first to seventh program states P1 to P7, respectively. The nonvolatile memory 110 may determine whether the threshold voltage of the memory cells included in the kth program state (k is a positive integer between 1 and M) is equal to or greater than the kth verify voltage.

In step S750, the nonvolatile memory 110 may determine whether a program operation is passed. If the threshold voltage of the memory cell programmed to the kth program state is not less than the kth verify voltage, the kth program state can be passed. If the first to seventh program states are passed, a program operation may be passed (S770). If the program operation is passed, the program operation ends. The nonvolatile memory 110 may report the completion of the programming operation to the memory controller 120. If the program operation is not passed, it may be determined that the program operation fails. In step S760, the nonvolatile memory 110 may determine whether the number of times of loop execution (or loop execution count) of the program operation corresponds to the maximum loop. For example, the execution of the program operation (S730), the execution of the verify-read operation (S740), and the determination of the pass of the program operation (S750) may constitute one loop.

If the cycle execution count does not correspond to the maximum cycle, the nonvolatile memory 110 may execute the next cycle S730, S740, and S750. If the loop execution count corresponds to the maximum loop, the nonvolatile memory 110 may determine that a program error occurs in step S780. The nonvolatile memory 110 may inform the memory controller 120 that an error occurs during a program operation.

Fig. 29 is a flowchart showing a method of performing an erase operation on the memory cells MC1 to MC 6. Referring to fig. 1, 26, 27, and 29, in step S810, the nonvolatile memory 110 may receive an erase command CMD1 and an address ADDR1 from an external device (e.g., the memory controller 120 of fig. 21).

In step S820, the nonvolatile memory 110 may perform an erase operation to lower a threshold voltage of a memory cell selected by the address ADDR 1. In step S830, the nonvolatile memory 110 may perform a verification read operation. For example, the nonvolatile memory 110 may perform a verify read operation by using a verify voltage corresponding to the erase state "E". The nonvolatile memory 110 may determine whether the threshold voltage of the memory cell is equal to or less than the verify voltage.

In step S840, the nonvolatile memory 110 may determine whether an erase operation is passed. If the threshold voltage of the memory cell is less than the verification voltage, an erase operation may be performed (S860). If the erase operation is passed, the erase operation ends. The nonvolatile memory 110 may inform the memory controller 120 of the completion of the erase state.

If the erase operation is not passed, it is determined that the erase operation fails. In step S850, the nonvolatile memory 110 may determine whether the number of times of loop execution (or loop execution count) of the erase operation corresponds to the maximum loop. For example, the execution of the erase operation (S820), the execution of the verify-read operation (S830), and the determination of the passage of the erase operation (S840) may constitute one loop.

If the cycle execution count does not correspond to the maximum cycle, the nonvolatile memory 110 may execute the next cycle S820, S830, and S840. If the cycle execution count corresponds to the maximum cycle, the nonvolatile memory 110 may determine that an erase error occurs in step S870. The nonvolatile memory 110 may inform the memory controller 120 of errors occurring during an erase operation.

Returning to fig. 26, the threshold voltages of the dummy memory cells DMC, the ground selection transistors GST, or the string selection transistors SSTa and SSTb may be adjusted within a specific range as described with reference to fig. 4 or 20. Thereafter, as a program operation, an erase operation, or a read operation is performed on the memory cells MC1 to MC6, the threshold voltages of the dummy memory cells DMC, the ground selection transistors GST, or the string selection transistors SSTa and SSTb may be changed due to interference or coupling.

If the threshold voltages of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistors SSTa and SSTb are out of the range defined by the verify voltages VFYl and VFYu, the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistors SSTa and SSTb may not be normally turned on or off during a program operation, a read operation, or an erase operation.

If the threshold voltages of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistors SSTa and SSTb are out of the range defined by the verify voltages VFYl and VFYu, the threshold voltages of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistors SSTa and SSTb may be readjusted to be included in the range defined by the verify voltages VFYl and VFYu through the first and second program operations.

Fig. 30 illustrates a change in threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST when the first program operation is performed. For example, the string selection transistor SST may include string selection transistors SSTa and SSTb. In fig. 30, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. That is, fig. 30 shows the distribution of threshold voltages.

Referring to fig. 26 and 30, the threshold voltage of some of the dummy memory cells DMC, the ground selection transistors GST, or the string selection transistors SST may be less than the verification voltage VFYl. If the first program operation is performed, the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST, which is smaller than the verification voltage VFYl, may be increased to the verification voltage VFYl or higher.

Fig. 31 is a flowchart illustrating a method of the nonvolatile memory 110 checking threshold voltages of the dummy memory cells DMC, the ground selection transistor GST, or the string selection transistor SST and performing a first program operation. Referring to fig. 26, 30, and 31, in step S910, the nonvolatile memory 110 may determine whether the check condition is satisfied.

The check condition may refer to a condition that the nonvolatile memory 110 checks that the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST must be satisfied. The check condition may include an internal environment variable or an external environment variable of the nonvolatile memory 110. An example of the inspection condition will be described more fully with reference to fig. 36.

If the check condition is not satisfied, the nonvolatile memory 110 does not check the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST. If the check condition is not satisfied, the nonvolatile memory 110 does not perform the first program operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST.

If the check condition is satisfied, the process proceeds to step S915. In step S915, the nonvolatile memory 110 may perform a verify read operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST by using the verify voltage VFYl. The nonvolatile memory 110 may determine whether the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is less than the verification voltage VFYl or equal to or greater than the verification voltage VFYl.

In step S920, the nonvolatile memory 110 may determine whether the check operation is passed. If the threshold voltage of the memory cell DMC, the ground selection transistor GST or the string selection transistor SST is not less than the verification voltage VFYl, a check operation may be performed. If the checking operation is passed, the nonvolatile memory 110 may end the process without performing the first programming operation or may determine that the first programming operation is passed without performing the first programming operation in step S960. Thereafter, the process associated with the first programming operation ends.

If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is less than the verification voltage VFYl, the check operation may fail. If the checking operation fails, the process proceeds to step S925. In step S925, the nonvolatile memory 110 may inhibit the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST having the threshold voltage equal to or greater than the verification voltage VFYl from being programmed.

For example, the dummy memory cells DMC, the ground selection transistors GST, or the string selection transistors SST connected to the bit line may be inhibited from being programmed by applying a supply voltage or a positive voltage to the bit line, the level of which is similar to that of the supply voltage.

In step S930, the nonvolatile memory 110 may allow the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST having the threshold voltage Vth less than the verification voltage VFYl to be programmed. For example, the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST connected to the bit line may be allowed to be programmed by applying a ground voltage or a low voltage to the bit line, the level of which is similar to that of the ground voltage.

In step S935, the nonvolatile memory 110 may supply a voltage according to fig. 32. Fig. 32 shows an example of a voltage applied to the memory block BLKb. Referring to fig. 26 and 32, a seventh bit line voltage VBL7 is applied to a bit line BL corresponding to a cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor) that allows programming. The seventh bit line voltage VBL7 may be a ground voltage or a low voltage having a level similar to that of the ground voltage.

The eighth bit line voltage VBL8 is applied to the bit line BL corresponding to a program-inhibited cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor). The eighth bit line voltage VBL8 may be a supply voltage or a positive voltage having a level similar to that of the supply voltage.

The fifth program voltage VPGM5 is applied to the dummy word line DWL, the string selection line SSL, or the ground selection line GSL corresponding to a cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor) that allows programming. The fifth programming voltage may be a high voltage that allows the cell transistor to undergo tunneling.

The fifth pass voltage VPASS5 is applied to the dummy word line DWL, the string selection line SSL, or the ground selection line GSL corresponding to a program-inhibited cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor). The fifth pass voltage VPASS5 may be a high voltage that is less than the fifth program voltage VPGM5 but allows the cell transistor (e.g., a dummy memory cell, a ground select transistor, or a string select transistor) to be turned on.

The fifth pass voltage VPASS5 may have different levels or the same level according to whether the fifth pass voltage VPASS5 is applied to any one of the dummy word line DWL, the string selection line SSL, and the ground selection line GSL. The sixth pass voltage VPASS6 may be applied to the word lines WL1 to WL6. The sixth pass voltage VPASS6 may be a high voltage that is smaller than the fifth program voltage VPGM5 but allows the memory cells MC1 through MC6 to be turned on. The sixth pass voltage VPASS6 may have different levels or the same level according to whether the sixth pass voltage VPASS6 is applied to any one of the word lines WL1 to WL6.

The fifth common source line voltage VCSL5 is applied to the common source line CSL. The fifth common source line voltage VCSL5 may be a ground voltage or a low voltage having a level similar to that of the ground voltage.

Returning to fig. 26, 30 and 31, in step S940, the nonvolatile memory 110 may perform a verify read operation on the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST by using the verify voltage VFYl. The nonvolatile memory 110 may determine whether the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is less than the verification voltage VFYl or equal to or greater than the verification voltage VFYl.

In step S945, the nonvolatile memory 110 may determine whether the first program operation is passed. If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is not less than the verification voltage VFYl, in step S960, the first programming operation may be possible. The nonvolatile memory 110 may end the first program operation.

If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is less than the verification voltage VFYl, the first programming operation may fail and the process proceeds to step S950. In step S950, the nonvolatile memory 110 may determine whether the number of times of loop execution (or loop execution count) of the program operation corresponds to the maximum loop. For example, steps S925 to S945 may form one cycle of the first program operation.

If the loop execution count does not correspond to the maximum loop, the nonvolatile memory 110 may execute the next loop. If the loop execution count corresponds to the maximum loop, the nonvolatile memory 110 may determine that a program error occurs in step S955. The nonvolatile memory 110 may inform the memory controller 120 that an error occurs during the first program operation.

Fig. 33 illustrates a variation in threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST when the second program operation is performed. In fig. 33, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. That is, fig. 33 shows the distribution of threshold voltages.

Referring to fig. 26 and 33, the threshold voltage of some of the dummy memory cells DMC, the ground selection transistors GST, or the string selection transistors SST may be greater than the verification voltage VFYu. If the second program operation is performed, the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST, which is greater than the verification voltage VFYu, may be reduced to the verification voltage VFYu or less.

Fig. 34 is a flowchart illustrating a method of the nonvolatile memory 110 checking the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST and performing the second program operation. Referring to fig. 26, 33, and 34, in step S1010, the nonvolatile memory 110 may determine whether the check condition is satisfied.

The nonvolatile memory 110 may not check the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST if the check condition is not satisfied. In addition, if the check condition is not satisfied, the nonvolatile memory 110 may not perform the second program operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST.

If the check condition is satisfied, the process proceeds to step S1015. In step S1015, the nonvolatile memory 110 may perform a verify read operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST by using the verify voltage VFYu. The nonvolatile memory 110 may determine whether the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is greater than the verification voltage VFYu or equal to or less than the verification voltage VFYu.

In step S1020, the nonvolatile memory 110 may determine whether the check operation is passed. If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is not greater than the verification voltage VFYu, a check operation may be performed. If the checking operation is passed, the nonvolatile memory 110 may end the process without performing the second programming operation or may determine that the second programming operation is passed without performing the second programming operation in step S1060. Thereafter, the process associated with the second programming operation ends.

If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is greater than the verification voltage VFYu, the checking operation may fail. If the check operation fails, the process proceeds to step S1025. In step S1025, the nonvolatile memory 110 may inhibit programming the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST having a threshold voltage equal to or less than the verification voltage VFYu.

In step S1030, the nonvolatile memory 110 may allow the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST having the threshold voltage Vth greater than the verification voltage VFYu to be programmed. For example, the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST connected to the bit line may be allowed to be programmed by applying a ground voltage or a low voltage to the bit line, the level of which is similar to that of the ground voltage.

In step S1035, the nonvolatile memory 110 may supply a voltage according to fig. 35. Fig. 35 shows an example of a voltage applied to the memory block BLKb. Referring to fig. 26, 34 and 35, a ninth bit line voltage VBL9 is applied to the bit line BL in comparison with a cell transistor (e.g., a dummy memory cell, a ground select transistor or a string select transistor) that allows programming. The ninth bit line voltage VBL9 may be a supply voltage or a positive voltage having a level similar to that of the supply voltage.

The tenth bit line voltage VBL10 is applied to the bit line BL corresponding to a program-inhibited cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor). The tenth bit line voltage VBL10 may be a ground voltage or a low voltage having a level similar to that of the ground voltage.

The sixth program voltage VPGM6 is applied to the dummy word line DWL, the string selection line SSL, or the ground selection line GSL corresponding to a cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor) that allows programming. The sixth program voltage VPGM6 may have a level that causes hot hole injection in the memory transistor. The sixth program voltage VPGM6 may have a lower level than the third common source line voltage VCSL 3. The sixth program voltage VPGM6 may have a level sufficient to turn off the dummy memory cell, the ground select transistor, or the string select transistor.

The seventh pass voltage VPASS7 is applied to the dummy word line DWL, the string selection line SSL, or the ground selection line GSL corresponding to a program-inhibited cell transistor (e.g., a dummy memory cell, a ground selection transistor, or a string selection transistor). The seventh pass voltage VPASS7 may be a high voltage that allows cell transistors (e.g., dummy memory cells, ground select transistors, or string select transistors) to be turned on.

The seventh pass voltage VPASS7 may have different levels or the same level according to whether the seventh pass voltage VPASS7 is applied to any one of the dummy word line DWL, the string selection line SSL, and the ground selection line GSL. The eighth pass voltage VPASS8 may be applied to the word lines WL1 to WL6. The eighth pass voltage VPASS8 may be a high voltage sufficient to turn on the memory cells MC1 through MC 6. The eighth pass voltage VPASS8 may have different levels or the same level according to whether the eighth pass voltage VPASS8 is applied to any one of the word lines WL1 to WL6.

The sixth common source line voltage VCSL6 is applied to the common source line CSL. The sixth common source line voltage VCSL6 may be a ground voltage or a low voltage having a level similar to that of the ground voltage.

Returning to fig. 26, 33 and 34, in step S1040, the nonvolatile memory 110 may perform a verify read operation on the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST by using the verify voltage VFYu. The nonvolatile memory 110 may determine whether the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is greater than the verification voltage VFYu or equal to or less than the verification voltage VFYu.

In step S1045, the nonvolatile memory 110 may determine whether the second program operation is passed. If the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST or the string selection transistor SST is not greater than the verifying voltage VFYu, the second programming operation may be performed (S1060). The nonvolatile memory 110 may end the second programming operation.

The second program operation may fail if the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is greater than the verifying voltage VFYu. If the second programming operation fails, the process proceeds to step S1050. In step S1050, the nonvolatile memory 110 may determine whether the number of times of loop execution (or loop execution count) of the program operation corresponds to the maximum loop. For example, steps S1025 to S1045 may form one cycle of the second program operation.

If the loop execution count does not correspond to the maximum loop, the nonvolatile memory 110 may execute the next loop. If the loop execution count corresponds to the maximum loop, the nonvolatile memory 110 may determine that a program error occurs in step S1055. The nonvolatile memory 110 may inform the memory controller 120 that an error occurs during the second programming operation.

As described above, when the check condition is satisfied, the nonvolatile memory 110 according to an embodiment of the inventive concept may check the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST, whose threshold voltage is less than the verification voltage VFYl. The nonvolatile memory 110 may perform a first program operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST whose threshold voltage is less than the verification voltage VFYl to allow the threshold voltage thereof to be increased.

When the check condition is satisfied, the nonvolatile memory 110 according to an embodiment of the inventive concept may check the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST, whose threshold voltage is greater than the verification voltage VFYu. The nonvolatile memory 110 may perform a second program operation on the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST whose threshold voltage is greater than the verification voltage VFYu to allow the threshold voltage thereof to be lowered.

Accordingly, even if the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST is changed due to disturbance or coupling, the threshold voltage of the dummy memory cell DMC, the ground selection transistor GST, or the string selection transistor SST may be adjusted to fall within the range defined by the verification voltages VFYl and VFYu. This would mean that the reliability of the nonvolatile memory 110 is improved.

In an embodiment, the inspection condition (hereinafter referred to as "first inspection condition") related to the verification voltage VFYl may be different from the inspection condition (hereinafter referred to as "second inspection condition") related to the verification voltage VFYu. The first program operation may be performed when the first check condition is satisfied, and the second program operation may be performed when the second check condition is satisfied.

As another example, the first inspection condition may be the same as the second inspection condition. When the first and second check conditions identical to each other are satisfied, the nonvolatile memory 110 may perform both the first and second program operations. When the first and second checking operations identical to each other are satisfied, the nonvolatile memory 110 may select and perform one of the first and second programming operations.

Fig. 36 illustrates an example of inspection conditions according to an embodiment of the inventive concept. Referring to fig. 1 and 36, the check condition may be a temperature of the nonvolatile memory 110 or the storage device 100 including the nonvolatile memory 110. When the temperature is equal to or greater than the first temperature T1, the inspection condition may be satisfied.

When the check condition is satisfied, the nonvolatile memory 110 may perform the first program operation or the second program operation. The nonvolatile memory 110 may perform the first program operation or the second program operation periodically with time if the temperature is higher than the first temperature T1.

When the temperature is equal to or less than the second temperature T2, the inspection condition may be satisfied. The nonvolatile memory 110 may perform a first program operation or a second program operation. The nonvolatile memory 110 may perform the first program operation or the second program operation periodically with time if the temperature is less than the second temperature T2.

The first temperature T1 and the second temperature T2 may be included together in the inspection condition. As another example, one of the first temperature T1 and the second temperature T2 may be included in the inspection condition, and the other thereof may not be included in the inspection condition.

The check condition may also include the number of program operations or erase operations. The number of program operations or erase operations may be managed for each of the memory blocks BLK1 to BLKz. For example, the number of times of a program operation or an erase operation may be managed by using a plurality of count cycles. For example, counts 0 through 999 could belong to a first period and counts 1000 through 1999 could belong to a second period.

The check condition may be satisfied when the number of program operations or erase operations of a particular memory block changes from one cycle (e.g., a first cycle) to another cycle (e.g., a second cycle). When the check condition is satisfied, the nonvolatile memory 110 may perform the first program operation or the second program operation. In an embodiment, the count periods may be uniform in magnitude. As another example, the count periods may differ from each other in magnitude.

For example, as the number of program operations or erase operations increases, the count period may decrease. That is, as the number of program operations or erase operations increases, the nonvolatile memory 110 may increase the execution frequency of the first program operation or the second program operation.

The check condition may also include the operation of the nonvolatile memory 110. For example, if the number of times the erase operation is performed after or before the previous check operation (e.g., S910 of fig. 31 or S1010 of fig. 34) is satisfied is equal to the first reference count R1, the check condition may be satisfied. The check condition may be satisfied if the number of times of the program operation performed after the previous check operation is equal to the second reference count R2. The first reference count R1 may have a fixed value. The check condition may be satisfied if the number of read operations performed after the previous check operation is equal to the third reference count R3.

Each of the first to third reference counts R1 to R3 may have a fixed value. As another example, the first to third reference counts R1 to R3 may have values determined according to a previously determined table or formula. As another example, each of the first to third reference counts R1 to R3 may have a value randomly generated after the checking operation.

The inspection conditions may also include time. For example, if the elapsed time after the previous inspection operation (e.g., S910 of fig. 31 or S1010 of fig. 34) is equal to or greater than the first reference time T1, the detection condition may be satisfied. The first reference time may have a fixed value. As another example, the first reference time T1 may have a value determined according to a previously determined table or formula. As another example, the first reference time T1 may have a value randomly generated after the checking operation.

Fig. 37 shows an application example of the memory block BLKb of fig. 26. Referring to fig. 37, a word line of the memory block BLKc adjacent to the ground selection line GSL may be the first dummy word line DWL1. The memory cell connected to the first dummy word line DWL1 may be a first dummy memory cell DMC1. The word lines of the memory block BLKc adjacent to the string selection lines SSL1a and SSL2a may be the second dummy word lines DWL2. The memory cell connected to the second dummy word line DWL2 may be a second dummy memory cell DMC2.

The word lines between the first and second dummy word lines DWL1 and DWL2 may be first to fifth word lines WL1 to WL5. The first to fifth word lines WL1 to WL5 may be connected to the first to fifth memory cells MC1 to MC5, respectively. The position of the dummy word line may not be limited to the connection portion as shown in fig. 26. For example, the dummy word line may be disposed at various positions of the memory block BLKc, if desired.

According to exemplary embodiments of the inventive concept, a threshold voltage of a cell transistor, particularly a ground selection transistor, may be programmed within a target range. Accordingly, a nonvolatile memory device having improved reliability and an operating method of the nonvolatile memory device are provided.

Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the inventive concept as defined in the following claims.

Claims

1. A method of operating a non-volatile memory device comprising a plurality of cell strings, each cell string comprising at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked along a direction perpendicular to a surface of a substrate on which the cell string is disposed, the method comprising:

determining whether the check condition is satisfied;

Performing a first verify operation on the dummy memory cells in the plurality of cell strings using a first verify voltage to detect a first dummy memory cell having a threshold voltage lower than the first verify voltage, if it is determined that the check condition is satisfied;

Performing a first programming operation on a first dummy memory cell, the first dummy memory cell having a first threshold voltage after the first programming operation;

performing a second verify operation on the first dummy memory cell using a second verify voltage, the second verify voltage being an upper limit of a target threshold voltage of the first dummy memory cell after the first program operation;

determining whether the first threshold voltage is higher than the second verification voltage;

Performing a second programming operation on the first dummy memory cell to reduce the threshold voltage of the first dummy memory cell from the first threshold voltage in the event that the first threshold voltage is determined to be higher than the second verify voltage, the first dummy memory cell having the second threshold voltage after the second programming operation; and

In the case where it is determined that the check condition is not satisfied, skipping the first verifying operation, the first programming operation, the second verifying operation and the second programming operation,

Wherein the second threshold voltage is lower than the first threshold voltage,

Wherein the first dummy memory cell is not used for programming, reading or erasing data and provides only an on or off function.

2. The method of claim 1, wherein the first program operation is an operation for increasing a threshold voltage of the first dummy memory cell from an initial threshold voltage to a first threshold voltage, and comprising the step of applying the first program operation voltage to a gate of the first dummy memory cell and the step of supplying a low voltage to a channel of the first dummy memory cell, the first program operation voltage being a positive voltage.

3. The method of claim 2, wherein the low voltage is supplied by: the first low voltage is supplied to the drain of the first dummy memory cell through a bit line coupled to the first dummy memory cell and the second low voltage is supplied to the source of the first dummy memory cell through a common source line coupled to the first dummy memory cell.

4. The method of claim 1, wherein a dummy memory cell of the plurality of cell strings is above a first memory cell of the plurality of memory cells in the direction and below a second memory cell of the plurality of memory cells in the direction, and

Wherein the first memory cell forms a first sub-block and the second memory cell forms a second sub-block.

5. The method of claim 1, wherein the second programming operation includes the step of applying a second programming operation voltage to the gate of the first dummy memory cell, the second programming operation voltage being a negative voltage.

6. The method of claim 5, wherein the second programming operation further comprises the step of supplying a third low voltage to the source of the first dummy memory cell through a common source line coupled to the first dummy memory cell.

7. The method of claim 6, wherein the drain of the first dummy memory cell is electrically floating by providing a first high voltage to the selected bit line and a second high voltage to the gate of the corresponding string selection transistor, respectively.

8. The method of claim 7, wherein the second programming operation further comprises applying a pass voltage to memory cells of the selected cell string other than the gate of the first dummy memory cell and the gate of the dummy memory cell.

9. The method of claim 1, wherein the method further comprises:

performing a first programming operation on a second dummy memory cell in the plurality of cell strings to raise a threshold voltage of the second dummy memory cell, the second dummy memory cell having a third threshold voltage after the first programming operation;

Performing a second verify operation on the second dummy memory cell using the second verify voltage;

Determining whether the third threshold voltage is equal to or lower than the second verification voltage;

In the case where the third threshold voltage is determined to be equal to or lower than the second verifying voltage, the second program operation is inhibited for the second dummy memory cell while the second program operation is being performed for the first dummy memory cell.

10. A method of operating a non-volatile memory device comprising a plurality of cell strings, each cell string comprising at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed, the dummy memory cells of the plurality of cell strings being above a first memory cell of the plurality of memory cells in the direction and below a second memory cell of the plurality of memory cells in the direction, the first memory cell forming a first sub-block, the second memory cell forming a second sub-block, the method comprising:

determining whether the check condition is satisfied;

performing a verify-read operation on a first ground select transistor in the plurality of cell strings using a first verify voltage if it is determined that the check condition is satisfied;

determining whether a first threshold voltage of the first ground select transistor is higher than a first verify voltage;

In the case that it is determined that the first threshold voltage of the first ground selection transistor is higher than the first verification voltage, performing a first program operation on the first ground selection transistor to lower the first threshold voltage of the first ground selection transistor;

in the case that it is determined that the first threshold voltage of the first ground selection transistor is not higher than the first verification voltage, skipping the first program operation; and

In the case where it is determined that the check condition is not satisfied, the verify-read operation and the first program operation are skipped,

Wherein the first ground select transistor is not used for programming, reading or erasing data and provides only an on or off function.

11. The method of claim 10, wherein the inspection condition is satisfied when the temperature is greater than or equal to a first temperature or when the temperature is less than or equal to a second temperature, wherein the second temperature is less than the first temperature.

12. The method of claim 10, wherein the check condition is satisfied when a number of times a memory cell associated with the first ground select transistor is programmed or erased increases to enter another of the plurality of number of time ranges.

13. The method of claim 12, wherein the size of each frequency range decreases as the number of times a memory cell is programmed or erased increases.

14. The method of claim 10, wherein the check condition is satisfied when a number of program operations, read operations, or erase operations of a memory cell associated with the first ground selection transistor after a previous check condition is satisfied is greater than or equal to a reference number.

15. The method of claim 10, wherein the check condition is satisfied when an erase operation is performed on a memory cell associated with the first ground select transistor.

16. The method of claim 10, the method further comprising:

performing a verify-read operation on a second ground select transistor in the plurality of cell strings using a first verify voltage if it is determined that the check condition is satisfied;

determining whether a second threshold voltage of the second ground select transistor is higher than the first verify voltage;

in a case where it is determined that the second threshold voltage of the second ground selection transistor is not higher than the first verifying voltage, the first programming operation is inhibited for the second ground selection transistor while the first programming operation is being performed for the first ground selection transistor.

17. The method of claim 10, the method further comprising:

Performing a second verify-read operation on the dummy memory cells in the plurality of cell strings using a second verify voltage if it is determined that the check condition is satisfied;

determining whether a threshold voltage of the dummy memory cell is higher than a second verify voltage;

In the event that the threshold voltage of the dummy memory cell is determined to be higher than the second verify voltage, a second programming operation is performed on the dummy memory cell to reduce the threshold voltage of the dummy memory cell.

18. The method of claim 10, the method further comprising:

performing a third verify read operation on the first ground select transistor using a third verify voltage if it is determined that the first threshold voltage of the first ground select transistor is not higher than the first verify voltage;

Determining whether the first threshold voltage of the first ground select transistor is lower than a third verify voltage;

in case it is determined that the first threshold voltage of the first ground selection transistor is lower than the third verifying voltage, a third programming operation is performed on the first ground selection transistor to raise the first threshold voltage of the first ground selection transistor.

19. The method of claim 10, the method further comprising:

Performing a fourth verify-read operation on the dummy memory cells in the plurality of cell strings using a fourth verify voltage if it is determined that the check condition is satisfied;

Determining whether a threshold voltage of the dummy memory cell is lower than a fourth verify voltage;

in the case where it is determined that the threshold voltage of the dummy memory cell is lower than the fourth verifying voltage, a fourth program operation is performed on the dummy memory cell to increase the threshold voltage of the dummy memory cell.

20. A method of operating a nonvolatile memory device comprising a plurality of cell strings, each cell string comprising at least one string selection transistor, a plurality of memory cells, at least one dummy memory cell, and at least one ground selection transistor stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed, the method comprising:

Performing a first program operation on memory cells in the plurality of cell strings to raise a first threshold voltage of the memory cells, the programmed memory cells having one of an erased state and a plurality of programmed states according to the programmed first threshold voltage;

determining whether the check condition is satisfied;

In the case where it is determined that the check condition is satisfied, performing a first verifying operation on the ground select transistor, the string select transistor, and the dummy memory cell in the plurality of cell strings using a first verifying voltage to detect at least one of the ground select transistor, the string select transistor, and the dummy memory cell having at least one second threshold voltage higher than the first verifying voltage;

Performing a second programming operation on the at least one of the ground select transistor, the string select transistor, and the dummy memory cell to lower the at least one second threshold voltage of the at least one of the ground select transistor, the string select transistor, and the dummy memory cell when the at least one second threshold voltage of the at least one of the ground select transistor, the string select transistor, and the dummy memory cell is higher than the first verify voltage;

Performing a third programming operation on the at least one of the ground select transistor, the string select transistor, and the dummy memory cell to raise the at least one second threshold voltage when the at least one second threshold voltage is lower than a second verify voltage,

Wherein, in the case where it is determined that the check condition is not satisfied, the first verifying operation, the second programming operation, and the third programming operation are skipped,

Wherein the ground select transistor, the string select transistor, and the dummy memory cell are not used to program, read, or erase data and only provide an on or off function.