CN109637927B - Method for manufacturing metal grid - Google Patents
Method for manufacturing metal grid Download PDFInfo
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- CN109637927B CN109637927B CN201811516520.2A CN201811516520A CN109637927B CN 109637927 B CN109637927 B CN 109637927B CN 201811516520 A CN201811516520 A CN 201811516520A CN 109637927 B CN109637927 B CN 109637927B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 71
- 239000002184 metal Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 123
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 81
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- 239000011229 interlayer Substances 0.000 claims abstract description 69
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 44
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000126 substance Substances 0.000 claims abstract description 38
- 239000007769 metal material Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000007517 polishing process Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000306 component Substances 0.000 claims description 21
- 230000005669 field effect Effects 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000008358 core component Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a metal gate, which comprises the following steps: providing a semiconductor substrate with a pseudo gate structure, a silicon nitride side wall and a contact etching stop layer; step two, forming an interlayer film; thirdly, carrying out a first chemical mechanical polishing process to planarize the interlayer film, and forming a disc-shaped concave structure on the surface of the interlayer film; fourthly, carrying out secondary back-etching process to carry out back-etching on the silicon nitride and enabling the surfaces of the silicon nitride on the two sides of the polysilicon gate to be lower than the disc-shaped recessed structure; removing the polysilicon gate; filling a metal material layer corresponding to the metal gate; and seventhly, carrying out a second chemical mechanical polishing process to planarize the metal material layer, wherein the second chemical mechanical polishing process removes all the metal material layers on the surface of the interlayer film and enables the metal material layers to be only filled in the polysilicon gate removal area, so that a metal gate is formed. The invention can eliminate the metal residue on the interlayer film by the chemical mechanical polishing process of the metal gate.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a metal gate.
Background
In the current advanced logic chip process, in order to increase the electrical performance of the device, the original polysilicon gate is removed and replaced by metal, and the used process method is metal chemical mechanical polishing.
However, since the chemical mechanical polishing of the silicon oxide in the prior art forms Dish-shaped (Dish) recesses on the top surface of the silicon oxide dielectric layer, i.e., the interlayer film, between the polysilicon gates, metal residues may be generated during the subsequent chemical mechanical polishing of the metal. The metal residue can cause short circuit of the circuit when the metal plug is deposited after the etching of the contact hole, and the yield of the product is directly impacted. The following is now described with reference to the drawings: as shown in fig. 1A to 1E, the device structure diagram in each step of the conventional method is shown, and the conventional method for manufacturing a metal gate includes the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate 101, forming a plurality of dummy gate structures on the semiconductor substrate 101, where each dummy gate structure is formed by overlapping a gate dielectric layer 102 and a polysilicon gate 103, a silicon nitride sidewall 104 is formed on a side surface of each dummy gate structure, and a Contact Etch Stop Layer (CESL)105 made of a silicon nitride material covers a top surface of the polysilicon gate 103, a side surface of the silicon nitride sidewall 104 of the polysilicon gate 103, and a surface of the semiconductor substrate 101 outside the dummy gate structure.
In the conventional method, the semiconductor substrate 101 is a silicon substrate.
The gate dielectric layer 102 comprises a high dielectric constant layer (HK) with an interfacial layer between the high dielectric constant layer and the semiconductor substrate 101; and forming a high-dielectric-constant metal gate (HKMG) by overlapping the gate dielectric layer 102 comprising the high-dielectric-constant layer and a subsequently formed Metal Gate (MG) 7.
Generally, a field oxide layer is formed in the semiconductor substrate 101, and an active region is isolated by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
The size of the polysilicon gate 103 in the active region outside the core region is larger than the size of the polysilicon gate 103 in the active region in the core region. Two sizes of the polysilicon gate 103 are shown in fig. 1A.
Step two, as shown in fig. 1A, forming an interlayer film 6 composed of silicon oxide, where the interlayer film 6 is formed on the surface of the contact etch stop layer 105, and the interlayer film 6 completely fills and extends the spacing region between the dummy gate structures to the top surface of the dummy gate structures.
Step three, as shown in fig. 1A, a chemical mechanical polishing process of silicon oxide is performed to planarize the interlayer film 6, the chemical mechanical polishing process is stopped at the top surface of the polysilicon gate 103 and exposes the top surface of the polysilicon gate 103, a dish-shaped recess structure is formed on the surface of the interlayer film 6 after the chemical mechanical polishing process, and the depth of the bottom of the dish-shaped recess structure is below the top surface of the polysilicon gate 103. The depth of the bottom of the dish-shaped recess structure is shown by dashed line AA, as indicated by dashed line 201.
And fourthly, as shown in fig. 1B, removing the polysilicon gate 103.
And step five, as shown in fig. 1C, filling a metal material layer 107 corresponding to the metal gate 107, wherein the metal material layer and the metal gate are both represented by reference numeral 107. The metal material layer 107 completely fills the region where the polysilicon gate 103 is removed and extends to the surfaces of the silicon nitride side wall 104, the contact etching stop layer 105 and the interlayer film 6 outside the region where the polysilicon gate 103 is removed.
Step six, as shown in fig. 1D, a chemical mechanical polishing process of metal is performed to planarize the metal material layer 107.
It can be seen that the surface of the metallic material layer 107 before the metal overpolishing is shown by the dotted line BB. As shown in fig. 1E, after metal over-grinding, the surface of the metal material layer 107 is lower than the surface shown by the dotted line BB. But the metal material layer 107 still remains in the butterfly-shaped recess structure.
Disclosure of Invention
The invention aims to provide a manufacturing method of a metal gate, which can eliminate metal residues on an interlayer film by a chemical mechanical polishing process of the metal gate.
In order to solve the above technical problem, the method for manufacturing a metal gate provided by the present invention comprises the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate, forming a plurality of pseudo gate structures on the semiconductor substrate, wherein the pseudo gate structures are formed by overlapping gate dielectric layers and polysilicon gates, silicon nitride side walls are formed on the side faces of the pseudo gate structures, and contact etching stop layers composed of silicon nitride materials cover the top surfaces of the polysilicon gates, the side faces of the silicon nitride side walls of the polysilicon gates and the surface of the semiconductor substrate outside the pseudo gate structures.
And step two, forming an interlayer film composed of silicon oxide, wherein the interlayer film is formed on the surface of the contact etching stop layer, and the interlayer film completely fills the interval region between the pseudo gate structures and extends to the top surface of the pseudo gate structures.
And step three, carrying out a first chemical mechanical polishing process to planarize the interlayer film, wherein the first chemical mechanical polishing process is stopped at the top surface of the polysilicon gate and exposes the top surface of the polysilicon gate, the interlayer film is positioned in an interval area between the polysilicon gates after the first chemical mechanical polishing process and forms a disc-shaped concave structure on the surface of the interlayer film, and the depth of the bottom of the disc-shaped concave structure is positioned below the top surface of the polysilicon gate.
And fourthly, carrying out a second back etching process, wherein the second back etching process carries out self-aligned back etching on the silicon nitride between the polysilicon gate and the interlayer film and reduces the top surfaces of the silicon nitride side walls and the contact etching stop layer at two sides of the polysilicon gate to the lowest position lower than the disc-shaped concave structure of the interlayer film.
And fifthly, removing the polysilicon gate.
And sixthly, filling a metal material layer corresponding to the metal gate, wherein the metal material layer completely fills the region where the polysilicon gate is removed and extends to the surfaces of the silicon nitride side wall, the contact etching stop layer and the interlayer film outside the region where the polysilicon gate is removed.
Step seven, carrying out a second chemical mechanical polishing process to planarize the metal material layer, wherein the second chemical mechanical polishing process removes all the metal material layers on the surface of the interlayer film and can over-polish the interlayer film, and the surface of the over-polished interlayer film is lower than the lowest position of the disc-shaped recessed structure; and filling the metal material layer after the second chemical mechanical grinding process only in the polysilicon gate removing region to form a metal gate.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer, and an interface layer is arranged between the high dielectric constant layer and the semiconductor substrate; forming HKMG by overlapping the gate dielectric layer of the high-dielectric constant layer and the metal gate.
In a further improvement, in the first step, the step of forming the dummy gate structure includes the following sub-steps:
and sequentially forming the gate dielectric layer and the first layer of polysilicon.
And forming a hard mask layer on the surface of the first layer of polysilicon.
And defining a forming area of the dummy gate structure by adopting a photoetching process.
And sequentially removing the hard mask layer, the polysilicon gate and the gate dielectric layer outside the forming region of the pseudo gate structure by adopting an etching process to form the pseudo gate structure.
And removing the hard mask layer after the silicon nitride side wall is formed and before the contact etching stop layer is formed.
In a further improvement, a field oxide layer is formed in the semiconductor substrate provided in the first step, and an active region is isolated by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
In a further refinement, a size of the polysilicon gate in the active region outside the core region is larger than a size of the polysilicon gate in the active region in the core region.
In a further improvement, the components corresponding to the metal grid comprise a core component and components outside a core area.
In a further refinement, the component is a field effect transistor.
In a further refinement, the component comprises an n-type field effect transistor and a p-type field effect transistor.
The further improvement is that the component enhancement process is also carried out after the silicon nitride side wall is formed in the fourth step; and forming a source region and a drain region of the component on the surface of the semiconductor substrate at two sides of the polysilicon gate after the component enhancement process is completed.
In a further improvement, the component enhancement process is a silicon germanium process.
In a further improvement, the device enhancement process forms a germanium-silicon layer in a source region or a drain region of the p-type field effect transistor.
In a seventh step, after the second chemical mechanical polishing process, the top surface of the interlayer film is higher than the top surfaces of the silicon nitride sidewall and the contact etch stop layer, and the metal gate also extends to the top surfaces of the silicon nitride sidewall and the contact etch stop layer.
The further improvement is that the second etching back process in the fourth step adopts dry etching.
In a further improvement, the metal material corresponding to the metal grid comprises aluminum.
In the invention, after the planarization of the interlayer film and the removal of the polysilicon gate are carried out, the self-alignment back etching is carried out on the silicon nitride positioned between the polysilicon gate and the interlayer film, and the top surfaces of the silicon nitride side wall and the contact etching stop layer are reduced to be lower than the lowest position of the disc-shaped concave structure of the interlayer film, so that when the chemical mechanical grinding process of metal, namely the second chemical mechanical grinding process, is carried out after the polysilicon gate is subsequently removed and the metal material layer is filled, because the top surface of the interlayer film comprises the disc-shaped concave structure and is positioned on the top surfaces of the silicon nitride side wall and the contact etching stop layer, the metal material layer on the surface of the interlayer film can be completely removed, the interlayer film can also be ground to a certain extent, the metal residue of the chemical mechanical grinding process of the metal gate on the interlayer film can be eliminated, and finally, the short circuit caused by the metal residue on the interlayer film can also be avoided, thereby improving the yield of the product.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1E are block diagrams of steps in a conventional method for fabricating a metal gate;
FIG. 2 is a flow chart of a method of an embodiment of the present invention;
fig. 3A-3F are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
Fig. 2 is a flowchart of a method according to an embodiment of the present invention, and fig. 3A to 3F are device structure diagrams in steps of the method according to the embodiment of the present invention, and the method for manufacturing a metal gate according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 1, forming a plurality of dummy gate structures on the semiconductor substrate 1, wherein the dummy gate structures are formed by overlapping gate dielectric layers 2 and polysilicon gates 3, silicon nitride side walls 4 are formed on the side surfaces of the dummy gate structures, and contact etching stop layers 5 made of silicon nitride materials cover the top surfaces of the polysilicon gates 3, the side surfaces of the silicon nitride side walls 4 of the polysilicon gates and the surface of the semiconductor substrate 1 outside the dummy gate structures.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate.
The gate dielectric layer 2 comprises a high dielectric constant layer, and an interface layer is arranged between the high dielectric constant layer and the semiconductor substrate 1; and forming HKMG by overlapping the gate dielectric layer 2 of the high dielectric constant layer and the metal gate 7 formed subsequently.
The forming step of the dummy gate structure comprises the following sub-steps:
and sequentially forming the gate dielectric layer 2 and the first layer of polysilicon.
And forming a hard mask layer on the surface of the first layer of polysilicon.
And defining a forming area of the dummy gate structure by adopting a photoetching process.
And sequentially removing the hard mask layer, the polysilicon gate 3 and the gate dielectric layer 2 outside the forming region of the pseudo gate structure by adopting an etching process to form the pseudo gate structure.
And removing the hard mask layer after the silicon nitride side wall 4 is formed and before the contact etching stop layer 5 is formed.
Forming a field oxide layer in the semiconductor substrate 1 provided in the first step, and isolating an active region by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
The size of the polysilicon gate 3 in the active region outside the core region is larger than the size of the polysilicon gate 3 in the active region in the core region. Two sizes of the polysilicon gate 3 are shown in fig. 3A.
Step two, as shown in fig. 3A, forming an interlayer film 6 composed of silicon oxide, where the interlayer film 6 is formed on the surface of the contact etch stop layer 5, and the interlayer film 6 completely fills and extends the spacing region between the dummy gate structures to the top surface of the dummy gate structures.
Step three, as shown in fig. 3A, a first chemical mechanical polishing process is performed to planarize the interlayer film 6, the first chemical mechanical polishing process is stopped at the top surface of the polysilicon gate 3 and exposes the top surface of the polysilicon gate 3, after the first chemical mechanical polishing process, the interlayer film 6 is located in an interval area between the polysilicon gates 3 and forms a disc-shaped recess structure on the surface of the interlayer film 6, and the depth of the bottom of the disc-shaped recess structure is located below the top surface of the polysilicon gate 3. The depth of the bottom of the dish-shaped recess structure is shown by the dashed line CC, as indicated by the dashed line 301.
And fourthly, as shown in fig. 3B, performing a second etching back process, wherein the second etching back process performs self-aligned etching back on the silicon nitride between the polysilicon gate 3 and the interlayer film 6 and reduces the top surfaces of the silicon nitride side walls 4 and the contact etching stop layer 5 at the two sides of the polysilicon gate 3 to the lowest position lower than the disc-shaped recessed structure of the interlayer film 6. The top surfaces of the silicon nitride spacers 4 and the contact etch stop layer 5 are shown by dashed lines DD.
And the second etching process in the fourth step adopts dry etching.
And step five, as shown in fig. 3C, removing the polysilicon gate 3.
Step six, as shown in fig. 3D, filling the metal material layer 7 corresponding to the metal gate 7, where the metal material layer and the metal gate are both denoted by reference numeral 7. The metal material layer 7 completely fills the region where the polysilicon gate 3 is removed and extends to the surfaces of the silicon nitride side wall 4, the contact etching stop layer 5 and the interlayer film 6 outside the region where the polysilicon gate 3 is removed.
Seventhly, as shown in fig. 3E, performing a second chemical mechanical polishing process to planarize the metal material layer 7, wherein the second chemical mechanical polishing process removes all the metal material layers 7 on the surface of the interlayer film 6 and over-polishes the interlayer film 6, the surface of the interlayer film 6 after over-polishing is lower than the lowest position of the disc-shaped recessed structure, and the surface of the interlayer film 6 after over-polishing is shown as a dotted line FF.
As shown in fig. 3F, the metal material layer 7 is usually polished by the second cmp process, and the metal material layer 7 after the second cmp process is only filled in the removed region of the polysilicon gate 3 to form a metal gate 7.
In the seventh step, after the second chemical mechanical polishing process, the top surface of the interlayer film 6 is higher than the top surfaces of the silicon nitride side wall 4 and the contact etching stop layer 5, and the metal gate 7 also extends to the top surfaces of the silicon nitride side wall 4 and the contact etching stop layer 5.
The metal material corresponding to the metal grid 7 comprises aluminum.
In the embodiment of the present invention, the components corresponding to the metal gate 7 include a core component and a component outside the core region. The component is a field effect transistor. The components include n-type field effect transistors and p-type field effect transistors.
Step four, after the silicon nitride side wall 4 is formed, an assembly enhancement process is carried out; and forming a source region and a drain region of the component on the surface of the semiconductor substrate 1 at two sides of the polysilicon gate 3 after completing the component enhancement process.
The component enhancement process is a germanium-silicon process.
And forming a germanium-silicon layer on the source region or the drain region of the p-type field effect transistor by the assembly enhancement process.
In the embodiment of the invention, after the planarization of the interlayer film 6 and the removal of the polysilicon gate 3 are carried out, the self-aligned etching back is carried out on the silicon nitride between the polysilicon gate 3 and the interlayer film 6, and the top surfaces of the silicon nitride side wall 4 and the contact etching stop layer 5 are reduced to be lower than the lowest position of the disc-shaped concave structure of the interlayer film 6, so that when the chemical mechanical polishing process of metal, namely the second chemical mechanical polishing process, is carried out after the subsequent removal of the polysilicon gate 3 and the filling of the metal material layer 7, because the top surface of the interlayer film 6 including the disc-shaped concave structure is positioned above the top surfaces of the silicon nitride side wall 4 and the contact etching stop layer 5, the metal material layer 7 on the surface of the interlayer film 6 can be completely removed, the interlayer film 6 can also be subjected to certain over-polishing, and the metal residue of the chemical mechanical polishing process of the metal gate 7 on the interlayer film 6 can be eliminated, therefore, short circuit caused by metal residue on the interlayer film 6 can be prevented, and the yield of the product can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method for manufacturing a metal gate is characterized by comprising the following steps:
providing a semiconductor substrate, forming a plurality of pseudo gate structures on the semiconductor substrate, wherein each pseudo gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, a silicon nitride side wall is formed on the side surface of each pseudo gate structure, and a contact etching stop layer composed of a silicon nitride material covers the top surface of the polysilicon gate, the side surface of the silicon nitride side wall of the polysilicon gate and the surface of the semiconductor substrate outside the pseudo gate structure;
step two, forming an interlayer film composed of silicon oxide, wherein the interlayer film is formed on the surface of the contact etching stop layer, and the interlayer film completely fills the interval region between the pseudo gate structures and extends to the top surface of the pseudo gate structures;
thirdly, carrying out a first chemical mechanical polishing process to planarize the interlayer film, wherein the first chemical mechanical polishing process is stopped at the top surface of the polysilicon gate and exposes the top surface of the polysilicon gate, the interlayer film is positioned in an interval area between the polysilicon gates after the first chemical mechanical polishing process and forms a disc-shaped concave structure on the surface of the interlayer film, and the depth of the bottom of the disc-shaped concave structure is positioned below the top surface of the polysilicon gate;
performing a second back etching process, wherein the second back etching process performs self-aligned back etching on the silicon nitride between the polysilicon gate and the interlayer film and reduces the top surfaces of the silicon nitride side walls on the two sides of the polysilicon gate and the contact etching stop layer to the lowest position lower than the dish-shaped recessed structure of the interlayer film;
fifthly, removing the polysilicon gate;
filling a metal material layer corresponding to the metal gate, wherein the metal material layer completely fills the region where the polysilicon gate is removed and extends to the surfaces of the silicon nitride side wall, the contact etching stop layer and the interlayer film outside the region where the polysilicon gate is removed;
step seven, carrying out a second chemical mechanical polishing process to planarize the metal material layer, wherein the second chemical mechanical polishing process removes all the metal material layers on the surface of the interlayer film and can over-polish the interlayer film, and the surface of the over-polished interlayer film is lower than the lowest position of the disc-shaped recessed structure; and filling the metal material layer after the second chemical mechanical grinding process only in the polysilicon gate removing region to form a metal gate.
2. A method of manufacturing a metal gate as claimed in claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. A method of manufacturing a metal gate as claimed in claim 1, wherein: the gate dielectric layer comprises a high dielectric constant layer, and an interface layer is arranged between the high dielectric constant layer and the semiconductor substrate; and forming the high-dielectric-constant metal gate by overlapping the gate dielectric layer comprising the high-dielectric-constant layer and the metal gate.
4. A method of manufacturing a metal gate as claimed in claim 1, wherein: in the first step, the step of forming the dummy gate structure includes the following sub-steps:
sequentially forming the gate dielectric layer and the first layer of polycrystalline silicon;
forming a hard mask layer on the surface of the first layer of polycrystalline silicon;
defining a forming area of the pseudo gate structure by adopting a photoetching process;
removing the hard mask layer, the polysilicon gate and the gate dielectric layer outside the forming region of the pseudo gate structure in sequence by adopting an etching process to form the pseudo gate structure;
and removing the hard mask layer after the silicon nitride side wall is formed and before the contact etching stop layer is formed.
5. A method of manufacturing a metal gate as claimed in claim 1, wherein: forming a field oxide layer in the semiconductor substrate provided by the first step, and isolating an active region by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
6. A method of manufacturing a metal gate as claimed in claim 5, wherein: the size of the polysilicon gate in the active region outside the core region is larger than the size of the polysilicon gate in the active region in the core region.
7. A method of manufacturing a metal gate as claimed in claim 5, wherein: the components corresponding to the metal grid comprise core components and components outside the core area.
8. A method of manufacturing a metal gate as claimed in claim 7, wherein: the component is a field effect transistor.
9. A method of manufacturing a metal gate as claimed in claim 8, wherein: the components include n-type field effect transistors and p-type field effect transistors.
10. A method of manufacturing a metal gate as claimed in claim 9, wherein: step four, after the silicon nitride side wall is formed, an assembly enhancement process is carried out; and forming a source region and a drain region of the component on the surface of the semiconductor substrate at two sides of the polysilicon gate after the component enhancement process is completed.
11. A method of manufacturing a metal gate as claimed in claim 10, wherein: the component enhancement process is a germanium-silicon process.
12. A method of manufacturing a metal gate as claimed in claim 11, wherein: and forming a germanium-silicon layer on the source region or the drain region of the p-type field effect transistor by the assembly enhancement process.
13. A method of manufacturing a metal gate as claimed in claim 1, wherein: in step seven, after the second chemical mechanical polishing process, the top surface of the interlayer film is higher than the top surface of the silicon nitride side wall and the top surface of the contact etching stop layer, and the metal gate also extends to the top surfaces of the silicon nitride side wall and the contact etching stop layer.
14. A method of manufacturing a metal gate as claimed in claim 1, wherein: and the second etching process in the fourth step adopts dry etching.
15. A method of manufacturing a metal gate as claimed in claim 1, wherein: the metal material corresponding to the metal gate comprises aluminum.
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| CN114695098B (en) * | 2022-02-28 | 2025-03-14 | 上海华力集成电路制造有限公司 | Method for manufacturing zero-layer interlayer film |
| CN118248628A (en) * | 2024-05-29 | 2024-06-25 | 浙江创芯集成电路有限公司 | Method for forming semiconductor structure |
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| CN101946329A (en) * | 2008-02-15 | 2011-01-12 | 日本优尼山帝斯电子株式会社 | Semiconductor device and method for manufacturing the same |
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| CN108493159A (en) * | 2018-04-13 | 2018-09-04 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
| CN108695259A (en) * | 2018-05-21 | 2018-10-23 | 上海华力集成电路制造有限公司 | The manufacturing method of MOS transistor with HKMG |
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| US8921178B2 (en) * | 2012-05-16 | 2014-12-30 | Renesas Electronics Corporation | Semiconductor devices with self-aligned source drain contacts and methods for making the same |
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| CN101946329A (en) * | 2008-02-15 | 2011-01-12 | 日本优尼山帝斯电子株式会社 | Semiconductor device and method for manufacturing the same |
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