CN109558757B - Vehicle identification system, electronic tag reader-writer and multi-rate decoding matching method - Google Patents
Vehicle identification system, electronic tag reader-writer and multi-rate decoding matching method Download PDFInfo
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Abstract
The invention relates to a vehicle identification system, an electronic tag reader-writer and a multi-rate decoding matching method, wherein the multi-rate decoding matching method comprises the following steps of processing a return signal of a vehicle-mounted electronic tag and performing AD sampling to obtain an AD sampling signal: carrying out digital band-pass filtering processing on the AD sampling signal to obtain a band-pass filtering signal; converting the rate of the bandpass filtered signal according to the reverse link rate of the return signal so that the converted rate is equal to the decoded data rate; and carrying out low-pass filtering processing on the signals after the rate conversion to obtain low-pass filtering signals, and sending the low-pass filtering signals to a decoder for decoding. By implementing the technical scheme of the invention, the decoder can perform decoding processing according to a fixed rate, the performance and the speed of decoding are not influenced, and the decoding of various rates is completed by using few resources.
Description
Technical Field
The invention relates to the field of Intelligent Transportation Systems (ITS), in particular to a vehicle identification System, an electronic tag reader-writer and a multi-rate decoding matching method.
Background
An electronic license plate, namely an automobile electronic identifier, is an electronic identity card which combines a common license plate with an ultrahigh Frequency Radio Frequency Identification (RFID) technology. The automobile electronic identification is used as the basis of intelligent traffic, can help traffic management departments to realize fine management of vehicles, will guide the revolution of the intelligent traffic industry, and drive the upgrading of the comprehensive traffic management system. In addition, the electronic license plate is also one of the car networking entrances, and traffic big data operation services such as bus electronic stop board operation, real-time traffic road condition information service, pedestrian navigation and the like can be benefited through the traffic big data obtained by the electronic license plate.
In recent years, the internet of things RFID technology is more and more applied in daily life due to the characteristics of automation, accuracy and quick identification. The automobile electronic identification technology is a practical application of the RFID technology of the Internet of things in the field of intelligent transportation, and the identification and monitoring of vehicles are automatically completed in a non-contact and non-stop manner by providing the vehicle information identification carrier, so that the bottleneck of the original traffic information acquisition technology is broken through, the accurate acquisition, the dynamic acquisition and the mass acquisition of vehicle information are realized, the traditional road traffic management mode is changed, and a huge revolution is brought to traffic management. The automobile electronic identification system is characterized in that an RFID vehicle-mounted electronic tag used for storing automobile identity data is arranged on the inner side of a front windshield of an automobile and is communicated with a vehicle-mounted electronic tag reader-writer arranged on the section of an urban road, so that data in the RFID vehicle-mounted electronic tag can be read and written. However, the data Frequency (i.e. the reverse Link Frequency (BLF)) of the data returned by the in-vehicle electronic tag is different, and the difference and span between the rates are large, and the in-vehicle electronic tag reader-writer side needs to support decoding of signals at all the reverse Link rates, so that decoding matching of multiple rates becomes a technical bottleneck of the in-vehicle electronic tag reader-writer.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a vehicle identification system, an electronic tag reader, and a multi-rate decoding matching method, aiming at the defect that the above-mentioned vehicle-mounted electronic tag reader in the prior art cannot support decoding of signals at all reverse link rates.
The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-rate decoding matching method is constructed, and after a return signal of a vehicle-mounted electronic tag is processed and AD sampled to obtain an AD sampling signal, the following steps are carried out:
carrying out digital band-pass filtering processing on the AD sampling signal to obtain a band-pass filtering signal;
converting the rate of the bandpass filtered signal according to the reverse link rate of the return signal so that the converted rate is equal to the decoded data rate;
and carrying out low-pass filtering processing on the signals after the rate conversion to obtain low-pass filtering signals, and sending the low-pass filtering signals to a decoder for decoding.
Preferably, the step of converting the rate of the band-pass filtered signal based on the reverse link rate of the return signal comprises:
the rate of the band-pass filtered signal is converted using a Farrow filter, and the rate conversion multiple of the Farrow filter satisfies the following condition:
when F _ decoder/BLF is less than or equal to 2, Ratio is F _ decoder/BLF;
when F _ decoder/BLF >2 and (F _ decoder/BLF)/(2 ^ M) ≦ 2, Ratio ═ F _ decoder/BLF)/(2 ^ M;
wherein Ratio is the rate conversion multiple of the Farrow filter, and F _ decoder is the decoding data rate; BLF is reverse link rate; m is a natural number;
judging whether the ratio of the decoding data rate to the reverse link rate is greater than 2, if so, executing the next step;
and performing frequency division 2 decimation processing on the digital signal output by the Farrow filter by using an M-stage half-band filter.
Preferably, before the step of converting the rate of the band-pass filtered signal by using a Farrow filter, the method further comprises:
determining the maximum read-write address of the RAM according to the reverse link rate and the decoding data rate, and sequentially writing the band-pass filtering signals into the RAM;
and determining the time and the address of reading data from the RAM each time according to the reverse link rate and the decoding data rate, and sending the read data to a Farrow filter.
Preferably, the step of determining the address at which data is read from the RAM each time comprises:
the address of the read data is determined according to the following equation:
Dk＝floor(Ratio＊(2＾L))*k/(Ratio＊(2＾L))；
wherein Dk is the address of the current read data; floor () is rounded down; l is the conversion rate fixed point bit width; k is the sequence number value of the current read data, and the initial value is 1.
Preferably, the step of determining the time at which each data read from the RAM comprises:
determining the write-once full time of the RAM according to the maximum read-write address of the RAM;
and determining the reading time of each data in the RAM according to the write-once time and the conversion rate fixed point bit width, and enabling 2 ^ L data to be read out in the write-once time.
Preferably, the order of the Farrow filter is fourth, and the coefficients of the four multipliers are:
W0＝factor*(Ratio*k–floor(Ratio*k))*(Ratio*k–floor(Ratio*k)-1)；
W1＝-W0-(Ratio*k–floor(Ratio*k))+1；
W2＝-W0+(Ratio*k–floor(Ratio*k))；
W3＝W0；
wherein, W0, W1, W2 and W3 are coefficients of four multipliers respectively; the factor is a weighting factor.
Preferably, the step of performing digital band-pass filtering processing on the AD sampling signal includes:
determining a bandpass cutoff frequency based on the reverse link rate;
calculating the coefficient of the digital band-pass filter according to the band-pass cut-off frequency to construct the digital band-pass filter;
and performing digital band-pass filtering processing on the AD sampling signal by using the constructed digital band-pass filter.
The invention also constructs a vehicle-mounted electronic tag reader-writer, which comprises: the processing module that is used for going on handling to on-vehicle electronic tags's return signal, and be used for carrying out AD sampling to the signal after handling and obtain the sampling module of AD sampled signal, still include:
the digital band-pass filter is used for carrying out digital band-pass filtering processing on the AD sampling signal so as to obtain a band-pass filtering signal;
a rate conversion module for converting the rate of the band-pass filtered signal according to the reverse link rate of the return signal so that the converted rate is equal to the decoded data rate;
and the low-pass filter is used for carrying out low-pass filtering processing on the band-pass filtering signal after the rate conversion so as to obtain a low-pass filtering signal, and sending the low-pass filtering signal to a decoder for decoding.
The invention also constructs a vehicle-mounted electronic tag reader-writer, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor is used for executing the computer program stored in the memory and realizing the method.
The present invention also provides a vehicle identification system including: a plurality of in-vehicle electronic tags mounted on a vehicle; and the vehicle-mounted electronic tag reader-writer is arranged on the road.
By implementing the technical scheme of the invention, after the received return signal from the vehicle-mounted electronic tag is converted into the digital signal, the digital signal is subjected to digital band-pass filtering processing, then rate conversion, then low-pass filtering processing and finally sent into the decoder for decoding, so that the decoder can perform decoding processing at a fixed rate, the performance and the speed of decoding cannot be influenced, the decoding at various rates can be completed by few resources, the anti-interference capability of a reader-writer can be improved, and the stability and the reliability of an electronic license plate system can be improved.
Drawings
In order to illustrate the embodiments of the invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort. In the drawings:
FIG. 1 is a flow chart of a first embodiment of a multi-rate decoding matching method of the present invention;
FIG. 2 is a flowchart illustrating a first embodiment of step S30 in FIG. 1;
FIG. 3 is a diagram of the read/write control of the RAM and the logic structure of the Farrow filter according to the present invention;
FIG. 4 is a logic structure diagram of a first embodiment of the vehicle-mounted electronic tag reader/writer according to the present invention;
fig. 5 is a logical structure diagram of a second embodiment of the in-vehicle electronic tag reader/writer according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a first embodiment of a multi-rate decoding and matching method according to the present invention, which is applied to a vehicle-mounted electronic tag reader/writer, and specifically includes the following steps:
and S10, processing and AD sampling a return signal of the vehicle-mounted electronic tag to obtain an AD sampling signal.
In the step, after receiving an uplink signal returned by the vehicle-mounted electronic tag, the vehicle-mounted electronic tag reader firstly performs noise cancellation, demodulation, intermediate frequency filtering, amplification and other processing, and then sends the uplink signal to an analog-to-digital converter (ADC) for sampling, so as to obtain an AD sampling signal.
And S20, carrying out digital band-pass filtering processing on the AD sampling signal to obtain a band-pass filtering signal.
In this step, the AD sampling signal output by the analog-to-digital converter is sent to a digital band-pass filter to filter out-of-band noise. In addition, the bandpass cutoff frequency of the digital bandpass filter may be set according to different reverse link rates.
And S30, converting the rate of the band-pass filtering signal according to the reverse link rate of the return signal so as to enable the converted rate to be equal to the decoding data rate.
And S40, carrying out low-pass filtering processing on the signals after the rate conversion to obtain low-pass filtering signals, and sending the low-pass filtering signals to a decoder for decoding.
In this step, since the extraction and interpolation of the signal in the step S30 bring nonlinear changes when performing rate conversion, the signal needs to be subjected to a low-pass filter for smooth compensation after completing the rate conversion, and then sent to a decoder for decoding, so that the subsequent decoding performance can be improved, which is helpful for improving the system sensitivity. Note that since the frequency of the signal after rate conversion is fixed, the low-pass filter may sample the same filter coefficient.
According to the technical scheme of the embodiment, after the received return signal from the vehicle-mounted electronic tag is converted into the digital signal, the digital signal is subjected to digital band-pass filtering processing, then rate conversion is performed, low-pass filtering processing is performed, and finally the digital signal is sent to the decoder to be decoded, so that the decoder can perform decoding processing according to a fixed rate, the performance and the speed of decoding cannot be influenced, decoding at various rates can be completed by few resources, meanwhile, the anti-jamming capability of a reader-writer can be improved, and the stability and the reliability of an electronic license plate system are improved.
In a preferred embodiment, step S20 includes the steps of:
s21, determining a band-pass cut-off frequency according to the reverse link rate;
s22, calculating coefficients of the digital band-pass filter according to the band-pass cut-off frequency to construct the digital band-pass filter;
and S23, carrying out digital band-pass filtering processing on the AD sampling signal by using the constructed digital band-pass filter.
In this embodiment, the corresponding bandpass cutoff frequency is determined based on the reverse link rate of the return signal, and the coefficients of the digital bandpass filter are determined based on the bandpass cutoff frequency. The digital band-pass filter uses different coefficients for return signals of different reverse link rates, which improves the receive sensitivity. In a specific example, the order of the digital band-pass filter takes 70 orders, and the corresponding filtering characteristics can be realized by the same set of multiplier and adder.
In a preferred embodiment, the digital signal processing part of the vehicle-mounted electronic tag reader-writer is realized based on an FPGA platform, that is, steps S20 to S40 can be performed in the FPGA, and the high-performance decoding function of the reader-writer can be quickly completed depending on the high-speed parallel processing capability of the FPGA.
Fig. 2 is a flowchart of a first embodiment of step S30 in fig. 1, in which step S30 specifically includes the following steps:
step S31, a Farrow filter is used for converting the rate of the band-pass filtering signal, and the rate conversion multiple of the Farrow filter meets the following conditions:
when F _ decoder/BLF is less than or equal to 2, Ratio is F _ decoder/BLF;
when F _ decoder/BLF >2 and (F _ decoder/BLF)/(2 ^ M) ≦ 2, Ratio ═ F _ decoder/BLF)/(2 ^ M;
wherein Ratio is the rate conversion multiple of the Farrow filter, and F _ decoder is the decoding data rate; BLF is reverse link rate; m is a natural number.
Step S32, judging whether the ratio of the decoding data rate to the reverse link rate is greater than 2, if so, executing step S33; if not, go to step S40;
and S33, performing frequency division extraction processing on the digital signal output by the Farrow filter by using the M-stage half-band filter.
With respect to this embodiment, it is first explained that the sampling rate of an analog-to-digital converter (ADC) is a system index, and an appropriate ADC device is selected according to the frequency of a signal processed by a reader/writer. Decoding algorithm the number of sample points N processed per symbol is determined by the subsequent decoding algorithm. And the decoded data rate is the ratio of the sampling rate to the number of samples N processed per symbol. In addition, since the reverse link rates of different return signals are different from each other, the converted data rate is not necessarily an integer multiple of the rate of all the signals before conversion, and therefore, fractional conversion, that is, rate conversion using a Farrow filter, is required. In order to make the signal after rate conversion have no characteristic loss and do not affect the decoding performance, when the data rate conversion multiple is larger than 2, firstly, the Farrow filter is used for carrying out conversion of decimal multiple to make the multiple relation between the rate of the signal output by the Farrow filter and the data rate processed by the decoder be an integer power of 2, and then the signal output by the Farrow filter is sent to the half-band filter to carry out extraction processing of frequency division by 2 until the final data frequency is obtained. When the data rate conversion multiple is less than or equal to 2, the data rate conversion multiple is only required to be sent to a Farrow filter for fractional conversion, and the data rate conversion multiple is not required to be sent to a half-band filter. In a specific example, first, the decoded data rate after conversion, F _ decoder, is determined by the sampling rate, F _ sample, of the analog-to-digital converter and the number of sample points, N, processed by the decoding algorithm per symbol. If the data rate conversion multiple F _ decoder/BLF is less than or equal to 2, the rate conversion multiple Ratio of the Farrow filter is F _ decoder/BLF, and the received data under the BLF only needs to pass through the Farrow filter and does not need to pass through the half-band filter; if the data rate conversion multiple F _ decoder/BLF is greater than 2, and (F _ decoder/BLF)/(2 ^ M) is less than or equal to 2, then Ratio ═ is (F _ decoder/BLF)/(2 ^ M), the received data under the BLF firstly passes through a Farrow filter and then passes through an M-level half-band filter, and the rate conversion of the digital signal is completed.
Further, since the total amount of data before and after rate conversion is different, the signal output by the digital band-pass filter can be stored in the RAM whose read/write address can be controlled, and then the appropriate data can be read out from the RAM by controlling the read/write address of the RAM, and then sent to the Farrow filter for extraction or interpolation. Specifically, between step S20 and step S30, the following steps are further included:
s50, determining the maximum read-write address of the RAM according to the reverse link rate and the decoding data rate, and sequentially writing the band-pass filtering signals into the RAM;
and S60, determining the time and the address of reading data from the RAM each time according to the reverse link rate and the decoding data rate, and sending the read data to a Farrow filter.
In step S60, the step of determining the address of each read data from the RAM further includes:
s61, determining the address of read data according to the following formula:
Dk＝floor(Ratio＊(2＾L))*k/(Ratio＊(2＾L))；
wherein Dk is the address of the current read data; floor () is rounded down; l is the conversion rate fixed point bit width; k is the sequence number value of the current read data, and the initial value is 1.
In step S60, the step of determining the time of reading data from the RAM each time includes:
s62, determining the write-once full time of the RAM according to the maximum read-write address of the RAM;
and S63, determining the reading time of each data in the RAM according to the one-time full writing time and the conversion rate fixed point bit width, and enabling 2 & ltL & gt data to be read in the one-time full writing time.
The read and write address control logic for the RAM is described below:
first, the FPGA processes the main frequency F _ main and the fixed-point bit width L of the slew rate, where the main frequency F _ main is generally selected to be an integer multiple of the sampling rate F _ sample, and for example, 2, 4, or 8 times of the F _ sample is suitable. The larger the fixed point bit width L is, the higher the precision is, the more FPGA resources are needed, and L is generally selected to be 8 or 10. The RAM has the storage depth of 2 ^ (L +1), and the RAM has the read-write address range of 0-floor (2 ^ L)) -1. When the reverse link rates are different, different rate conversion can be realized only by selecting different read-write addresses.
The digital signal outputted by the digital band-pass filter is stored in RAM, all the received data are written in sequence, the correspondent write address is traversed to floor (Ratio (2 ^ L)) from 1, then it is circulated in sequence, every time the data of floor (Ratio (2 ^ L)) are written in, 2 ^ L data can be read out, the read address is: floor (Ratio < 2 > -L)). k/(Ratio < 2 > -L))) with the initial value of k being 1, k being added with 1 for each data read, and returning to 1 for recycling when k is equal to 2 < L >.
Because the total amount of data written into the RAM is different from the total amount of data read out of the RAM, after the BLF is determined, the writing speed of the RAM is fixed, in order to prevent the phenomenon of reading out of the RAM or covering the RAM, the reading speed of the RAM needs to be controlled, the condition that the data are just read out for 2 & ltLambda & gt L within the time of writing in floor (2 & ltLambda & gt L) is met, and the phenomenon of reading out of the RAM or covering the RAM cannot occur.
Taking FPGA main frequency as 8 times of sampling frequency as an example, writing data into the RAM every 8 clock cycles, and when the conversion multiple is more than 1, because the total amount of the read data is less than the amount of the written data, the clock cycle of reading data every time is more than 8; when the conversion multiple is less than 1, the clock cycle per read data is less than 8 because the total amount of read data is greater than the amount of written data.
The reverse link rate that the national standard needs to support at present includes 64kHz, 137kHz, 174kHz, 320kHz, 128kHz, 274kHz, 349kHz, 640kHz, taking the ADC sampling rate as 6MSPS, taking as an example that each symbol of the decoding algorithm processes 16 data, the decoded data rate after conversion F _ decoder is 375 kHz. If the selected conversion rate fixed point bit width L is 8, the conversion rate multiple of the Farrow filter, the number of stages of the half-band filter and the maximum RAM read-write address are shown in the following table:
when the selected slew rate fixed point bit width L is 8, the storage depth of the RAM is 512. Under each different BLF, the write address of the RAM respectively traverses from 1 to the maximum read-write address of the RAM shown in the table above, the read address of the RAM is obtained through calculation, for example, the BLF is 640KHz, other conditions are consistent with those described above, the conversion multiple of the Farrow filter is 0.5859375 at this time, the filter needs to perform interpolation processing by using data read from the RAM, the maximum read-write address of the RAM is 150 at this time, one data is written into the RAM every 8 clock cycles, 256 data need to be read out every 150 written data, that is, 256(2 & ltr & gt 8) data are read out in 1200(150 & ltr & gt 8) clock cycles, and one data is read out every 4 or 5 clock cycles on average, so that the writing and reading of the whole RAM can be smooth, and the phenomenon of address reading out or covering cannot occur. For another example, one data is written in every 8 clock cycles, taking BLF as 64K as an example, 256 data needs to be read out while writing 375 numbers, that is, 256(2 ^ 8) data is read out every 3000(375 × 8) clock cycles, which is equivalent to one data is read out every 11.71875 clock cycles, because the read-out clock cycles are fixed to be integer, it is possible to read out one number every 11 clock cycles and then 12 clock cycles in 3000 clock cycles, and it is guaranteed that 256 numbers are read out every 3000 clock cycles, so that the input and output flows are matched, each reverse link rate corresponds to different read enable mechanisms, multiple mechanisms can be simultaneously implemented in the circuit, and then different mechanisms can be selected to implement through the reverse link rate.
Combining the input/output control of the RAM and the logical structure diagram of the Farrow filter shown in fig. 3, taking as an example that the ADC sampling rate is 6MSPS, each symbol of the decoding algorithm processes 16 data, the FPGA main frequency is 48MHz, the slew rate fixed point bit width L is 8, the output data of the digital band-pass filter is directly written into the RAM, the write address of the RAM is selected by the BLF to cycle between 1 to 375, 1 to 350, 1 to 300, 1 to 275, 1 to 150, the read enable can control the read data frequency (i.e., control the time and period of reading data) by selecting the BLF, the read address is accumulated by 375, 350, 300, 275 or 150 by selecting the BLF, and the accumulated value is divided by 256 to retain the integer part, which is the read address.
In addition, regarding the Farrow filter, it should be noted that the larger the selected order, the better the performance and the higher the complexity. With reference to fig. 3, the order of the Farrow filter is 4, the data read from the RAM and the data read three times before are used for the extraction or interpolation process of the Farrow filter, and only three real multipliers (substantially four multipliers, one of which can be omitted because the fourth multiplier is the same as the first multiplier) and one adder are needed to complete the process, and the coefficients of the four multipliers of the filter are calculated by selecting different conversion rates from the BLF, and each time one data is read from the RAM, the four coefficients also change correspondingly, and the calculation method of the four coefficients is as follows:
W0＝factor*(Ratio*k–floor(Ratio*k))*(Ratio*k–floor(Ratio*k)-1)
W1＝-W0-(Ratio*k–floor(Ratio*k))+1
W2＝-W0+(Ratio*k–floor(Ratio*k))
W3＝W0
w0, W1, W2, and W3 are coefficients of four multipliers, respectively. The factor is a weighting factor, which is related to the order of the filter, and is typically a fixed value, for example 9/32.
And each time a number is taken out from the RAM, k is added with 1, because fixed point calculation is adopted in the FPGA, the BLF is 640KHz, the ADC sampling rate is 6MSPS, each symbol of a decoding algorithm processes 16 data, the FPGA main frequency is 48MHz, and the conversion rate fixed point bit width L is 8, the calculation of the four multiplier coefficients can be consistent with the read address calculation of the RAM, the BLF is selected to be accumulated by 375, 350, 300, 275 or 150, the accumulated value is used for dividing 256 to keep a decimal part, and the decimal part is divided by 256 to obtain (Ratio k-floor (Ratio k)), so that the four coefficients can be calculated.
With reference to fig. 3, the Farrow filter implements a convolution by a digital circuit, that is, four coefficients are multiplied by four input signals respectively and then accumulated, and since the first coefficient is the same as the fourth coefficient, the first input signal and the fourth input signal can be added and then multiplied by the coefficients, so that only three multipliers and one adder are needed to implement accumulation after multiplication of the input signals.
Regarding the half-band filter, it should be noted that the data calculated by the Farrow filter determines whether the data needs to be extracted by the half-band filter according to the rate conversion multiple, and if not, the data is directly sent to the low-pass filter; if necessary, the signal is passed through a half-band filter and then fed into a low-pass filter. The number of stages of the half band filter is determined by the conversion factor between the BLF and the decoder processing data frequency, and if the data frequency after passing through the Farrow filter is equal to the decoder processing data frequency, the half band filter is not required to pass through, and if the factor between the data frequency after passing through the Farrow filter and the decoder processing data frequency is the M-th power of 2, the M-stage half band filter is also required to pass through. The half-band filter extracts data output by the Farrow filter, one of every two output data is extracted for calculation, the order of the half-band filter is 4, the coefficient is fixed, and the operation can be completed through 4 real number multipliers and 1 adder.
Fig. 4 is a logic structure diagram of a first embodiment of the vehicle-mounted electronic tag reader-writer according to the present invention, where the vehicle-mounted electronic tag reader-writer of the embodiment includes: a processing module 11, a sampling module 12, a digital band-pass filter 13, a rate conversion module 14 and a low-pass filter 15. The processing module 11 is configured to process a return signal of the vehicle-mounted electronic tag; the sampling module 12 is configured to perform AD sampling on the processed signal to obtain an AD sampled signal; the digital band-pass filter 13 is configured to perform digital band-pass filtering processing on the AD sampling signal to obtain a band-pass filtering signal; the rate conversion module 14 is configured to convert the rate of the bandpass filtered signal according to the reverse link rate of the return signal, so that the converted rate is equal to the decoding data rate; the low-pass filter 15 is configured to perform low-pass filtering processing on the rate-converted band-pass filtered signal to obtain a low-pass filtered signal, and send the low-pass filtered signal to a decoder for decoding. The digital band pass filter 13, the rate conversion module 14 and the low pass filter 15 can be implemented in an FPGA.
Preferably, the rate conversion module 14 includes a Farrow filter, a determination module, and a half-band filter, wherein the Farrow filter converts the rate of the band-pass filtered signal, and the rate conversion multiple of the Farrow filter satisfies the following condition:
when F _ decoder/BLF is less than or equal to 2, Ratio is F _ decoder/BLF;
when F _ decoder/BLF >2 and (F _ decoder/BLF)/(2 ^ M) ≦ 2, Ratio ═ F _ decoder/BLF)/(2 ^ M;
the judging module is used for judging whether the ratio of the decoding data rate to the reverse link rate is more than 2. The half-band filter is used for performing M-stage 2-frequency division decimation processing on the digital signal output by the Farrow filter.
Further, the rate conversion module 14 further includes a RAM, and determines a maximum read/write address of the RAM according to the reverse link rate and the decoded data rate of the return signal, and sequentially writes the band-pass filtered signal into the RAM. The time and address of each read of data from the RAM is determined based on the reverse link rate and the decoded data rate, and the read data is fed into a Farrow filter.
Fig. 5 is a logical structure diagram of a second embodiment of the in-vehicle electronic tag reader-writer according to the present invention, where the in-vehicle electronic tag reader-writer of this embodiment includes a processor 10 and a memory 20, where the memory 20 stores a computer program, and the processor 10 is configured to execute the computer program stored in the memory 20 and implement the method of the above embodiment.
The invention further constructs a vehicle identification system, which comprises a vehicle-mounted electronic tag reader-writer arranged on a road and a plurality of vehicle-mounted electronic tags loaded on a vehicle, wherein the logical structure diagram of the vehicle-mounted electronic tag reader-writer can refer to the above description, and the description is omitted here.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. A multi-rate decoding matching method is characterized in that after a return signal of a vehicle-mounted electronic tag is processed and AD sampled to obtain an AD sampling signal, the following steps are carried out:
carrying out digital band-pass filtering processing on the AD sampling signal to obtain a band-pass filtering signal;
converting the rate of the bandpass filtered signal using a Farrow filter based on the reverse link rate of the return signal such that the converted rate is equal to the decoded data rate;
and carrying out low-pass filtering processing on the signals after the rate conversion to obtain low-pass filtering signals, and sending the low-pass filtering signals to a decoder for decoding.
2. The multi-rate decoding matching method of claim 1, wherein the step of using a Farrow filter to convert the rate of the band-pass filtered signal based on the reverse link rate of the return signal comprises:
the rate of the band-pass filtered signal is converted using a Farrow filter, and the rate conversion multiple of the Farrow filter satisfies the following condition:
when F _ decoder/BLF is less than or equal to 2, Ratio is F _ decoder/BLF;
when F _ decoder/BLF >2 and (F _ decoder/BLF)/(2 ^ M) ≦ 2, Ratio ═ F _ decoder/BLF)/(2 ^ M;
wherein Ratio is the rate conversion multiple of the Farrow filter, and F _ decoder is the decoding data rate; BLF is reverse link rate; m is a natural number;
judging whether the ratio of the decoding data rate to the reverse link rate is greater than 2, if so, executing the next step;
and performing frequency division 2 decimation processing on the digital signal output by the Farrow filter by using an M-stage half-band filter.
3. The multi-rate decoding matching method of claim 2, further comprising, prior to the step of converting the rate of the band-pass filtered signal using a Farrow filter:
determining the maximum read-write address of the RAM according to the reverse link rate and the decoding data rate, and sequentially writing the band-pass filtering signals into the RAM;
and determining the time and the address of reading data from the RAM each time according to the reverse link rate and the decoding data rate, and sending the read data to a Farrow filter.
4. The multi-rate decode matching method of claim 3, wherein the step of determining the address at which data is read from the RAM each time comprises:
the address of the read data is determined according to the following equation:
Dk＝floor(Ratio＊(2＾L))*k/(Ratio＊(2＾L))；
wherein Dk is the address of the current read data; floor () is rounded down; l is the conversion rate fixed point bit width; k is the sequence number value of the current read data, and the initial value is 1.
5. The multi-rate decode matching method of claim 4, wherein the step of determining the time to read data from the RAM each time comprises:
determining the write-once full time of the RAM according to the maximum read-write address of the RAM;
and determining the reading time of each data in the RAM according to the write-once time and the conversion rate fixed point bit width, and enabling 2 ^ L data to be read out in the write-once time.
6. The multirate decoding matching method of claim 4 wherein the Farrow filter has an order of four, and the coefficients of its four multipliers are:
W0＝factor*(Ratio*k–floor(Ratio*k))*(Ratio*k–floor(Ratio*k)-1)；
W1＝-W0-(Ratio*k–floor(Ratio*k))+1；
W2＝-W0+(Ratio*k–floor(Ratio*k))；
W3＝W0；
wherein, W0, W1, W2 and W3 are coefficients of four multipliers respectively; the factor is a weighting factor.
7. The multi-rate decoding matching method of claim 1, wherein the step of performing digital band-pass filtering processing on the AD sampled signal comprises:
determining a bandpass cutoff frequency based on the reverse link rate;
calculating the coefficient of the digital band-pass filter according to the band-pass cut-off frequency to construct the digital band-pass filter;
and performing digital band-pass filtering processing on the AD sampling signal by using the constructed digital band-pass filter.
8. An in-vehicle electronic label reader-writer, comprising: a processing module for being directed at on-vehicle electronic tags's return signal is handled, and be used for carrying out AD sampling to the signal after handling and obtain AD sampling signal's sampling module, its characterized in that still includes:
the digital band-pass filter is used for carrying out digital band-pass filtering processing on the AD sampling signal so as to obtain a band-pass filtering signal;
a rate conversion module for converting the rate of the band-pass filtered signal using a Farrow filter according to the reverse link rate of the return signal so that the converted rate is equal to the decoded data rate;
and the low-pass filter is used for carrying out low-pass filtering processing on the band-pass filtering signal after the rate conversion so as to obtain a low-pass filtering signal, and sending the low-pass filtering signal to a decoder for decoding.
9. An in-vehicle electronic tag reader comprising a memory and a processor, the memory storing a computer program, characterized in that the processor is configured to execute the computer program stored in the memory and to implement the method of any of claims 1-7.
10. A vehicle identification system, comprising:
a plurality of in-vehicle electronic tags mounted on a vehicle; and
the in-vehicle electronic tag reader/writer according to claim 8 or 9 provided on a road.
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