CN102426370A - Segment correlation accumulation method for GPS signal acquisition algorithm - Google Patents
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Abstract
The invention discloses a segment correlation accumulation method for a GPS signal capture algorithm, which is characterized in that the length of a matched filtering block is set as the length of an I-path register block, a Q-path register block and a local C/A code register block, and meanwhile, the obtained segment correlation data is stored by using a series of division discrimination results and finally output to a post-stage FFT processing module. The technical scheme optimizes the occupation amount of the register resources in the whole correlation accumulation process, saves the use amount of the register on one hand, and is beneficial to design.
Description
Technical field
The present invention relates to the method used in the gps signal capture technique, specifically is a kind of relevant accumulation method of segmentation that belongs in the part matched filtering parallel frequency catching algorithm.
Background technology
Gps satellite navigation neceiver baseband digital signal is handled mainly to use and is caught and follow the tracks of two modules.Trapping module is mainly realized the estimation to satellite signal carrier frequency and pseudo-code code phase; For the carrier wave ring of tracking module and sign indicating number ring provide the initial value of frequency and code phase, the accurate and fragile carrier wave ring of tracking module is encircled with sign indicating number can operate as normal and locking satellite signal.
In the technology of trapping module utilization, be one of important acquisition algorithm based on the parallel frequency catching algorithm of part matched filtering always.Segmentation is relevant to add up this algorithm through the zero intermediate frequency digital signal on I road and Q road is carried out respectively, has not only obtained spreading gain, and has reduced data rate, thereby reduced counting of follow-up Fast Fourier Transform (FFT) (FFT) module, has reduced the realization difficulty.Though this algorithm does not need very complicated Fourier transform module, if the relevant accumulator module of segmentation is not optimized design, its realization often need expend huge register resources, increases the power consumption of trapping module greatly.Based on this, the relevant accumulation method of segmentation is reasonably designed, make it have the saving characteristics of resources, the inevitable demand when just becoming such trapping module design.
Summary of the invention
Inevitable demand when designing based on above trapping module, the present invention proposes a kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm, and its technical scheme is following:
A kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm, it may further comprise the steps:
Step 1: initialization comprises: synchronizing sequence receives I, the Q road zero intermediate frequency digital signal from Digital Down Convert; Set periodic sampling in the C/A sign indicating number 1ms H that counts, the sampling number A of half chip, and the number C of the length B of a matched filter block and said matched filter block; Make D=B/A, D is an integer; Other establishes initial value is a variable k of 0;
Step 2: division is differentiated, and after the completion above-mentioned steps one, is that dividend, D are divisor with k, makes its merchant be Y, and remainder is X, constructs a bivector [X, Y]:
4) if X=Y=0, the sequence order of then press signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with B length this locality C/A sign indicating number of preface, deposit in separately in I road block of registers, Q road block of registers and the C/A block of registers of B length; K increases progressively 1 then;
5) if Y＞0 and X=0 then continue to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposit said I road block of registers and Q road block of registers separately in; Continue simultaneously to read the local C/A sign indicating number of B length and deposit said C/A sign indicating number block of registers in; K increases progressively 1 then;
6) if X＞0 and Y＞0 are then continued to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposited said I road block of registers and Q road block of registers separately in, k increases progressively 1 then;
Step 3: relevant adding up; After carrying out step 2, the common mark of current data in said I road block of registers, Q road block of registers and the C/A block of registers is designated as current X, the corresponding said bivector [X, Y] of Y value; Data in said I road block of registers that again will be this moment and the Q road block of registers respectively with C/A sign indicating number block of registers in data make relevant accumulating operation, the still corresponding said bivector of each operation result that obtains [X, Y], and preservation separately;
Step 4: reset: set up criterion with k=D*C; If; Then with said I road block of registers, Q road block of registers and C/A sign indicating number block of registers empty, k zero setting, all said I roads, Q road zero intermediate frequency digital signal are initial reads and the initial original order of pressing each sequence that reads of sequence of local C/A sign indicating number is reset X=Y=0 in the said bivector; If not, then still get back to other situation that step 2 is judged the k value;
Step 5: read: will go up the said operation result that a step obtains, will wait the owner of X value mark to read each time, and all carry out FFT one by one and handle by the ordering of X.
As the preferred person of present technique scheme, on the basis of above technical scheme, following improvement can be arranged:
In one preferred embodiment, said I road block of registers prime also is provided with input block, an I road, and said Q road block of registers prime also is provided with input block, a Q road; The control that this input block, I road and input block, Q road receive sequential circuit transfers to said I road block of registers and Q road block of registers with the I road zero intermediate frequency digital signal and the Q road zero intermediate frequency digital signal of correspondence respectively by its sequence order.
In one preferred embodiment, said C/A sign indicating number block of registers prime has a storer by sequence order circulation output C/A sign indicating number.
In one preferred embodiment, it is D that a line number is set, and columns is the storage matrix of C, and each said operation result deposits the capable Y row of the X corresponding cells of this storage matrix in by said bivector [X, Y]; In the said step 5 said storage matrix is read by the row full line.
On the scheme basis that is provided with I road, input block, Q road; In one preferred embodiment; Input block, I road described in the said step 4, input block, Q road are read the data of (G*H-B*C) length respectively on existing state; Simultaneously the reading pointer of said local C/A sign indicating number recovers initial value, reads a little with the initial of each corresponding sequence of resetting.
As the pairing device of above technical scheme, can be following scheme:
A kind of segmentation of gps signal acquisition algorithm adding up device of being correlated with, it comprises:
One I road input buffer, its input end connects the I road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects an I road block of registers;
One Q road input buffer, its input end connects the Q road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects a Q road block of registers;
One C/A sign indicating number sequence storage unit, its output terminal connects a C/A sign indicating number block of registers;
Between said I road block of registers and C/A sign indicating number block of registers, has the relevant totalizer in I road; Has the relevant totalizer in Q road between said Q road block of registers and the C/A sign indicating number block of registers; The relevant relevant totalizer output terminal with the Q road of totalizer in this I road all is connected to one first buffer register;
The said first buffer register output terminal connects a RAM matrix, and this RAM matrix connects the FFT processing module through one second buffer register;
Wherein, the memory length of said I road block of registers, Q road block of registers and C/A sign indicating number block of registers is the matched filtering block length B of setting; The line number of said RAM matrix is removed the merchant D of half chip samples point for the matched filtering block length; Said RAM matrix column number is matched filter block number C; Other has time schedule controller to connect said I road input buffer, Q road input buffer, C/A sign indicating number sequence storage unit and said RAM matrix simultaneously.
The beneficial effect that the present invention brings is:
With the matched filtering block length as I road, Q road and local C/A sign indicating number register length, the register resources occupancy volume of whole relevant cumulative process is optimized, saved the register use amount.
2. adopting D length line number, C length is the storage matrix of columns, optimizes the road storage resources, also is beneficial to being connected and reading of summation module and back grade FFT module.
3. the entire process apparatus structure is succinct, and treatment effeciency is high.
Description of drawings
Embodiment is described further the present invention below in conjunction with accompanying drawing:
Fig. 1 is the embodiment process flow diagram of the relevant segmentation accumulation method of the present invention;
Fig. 2 is the segmentation adding up device block diagram of correspondence embodiment illustrated in fig. 1.
Embodiment
Like Fig. 1, the embodiment process flow diagram of the relevant segmentation accumulation method of the present invention; Fig. 2 is the segmentation adding up device block diagram of correspondence embodiment illustrated in fig. 1.Explain in conjunction with this two figure:
Begin from flow process, initialization step 10 has comprised the periodic sampling of setting in the C/A sign indicating number 1ms H=16367667 that counts, the sampling number A=8 of half chip, and so the length B=664 of matched filter block, and the number C=49 of said matched filter block be D=B/A=83.Specifically, it is optimal values after the emulation that the length B of matched filter block is set at 664, and this length 664 also is the length of I road block of registers 112 among Fig. 2, Q road block of registers 122 and C/A sign indicating number block of registers 102.
Level has I road input buffer 111 before the input end of I road block of registers 112, and accordingly, the input end value prime of Q road block of registers 122 has Q road input buffer 121; I road, Q road input buffer have an input end Iport and Qport separately, connect respectively from I road after the Digital Down Convert and Q road orthogonal signal; The input end prime of C/A block of registers 102 is C/A sign indicating number sequence storage unit 101 of a ROM form; Under the control of time schedule controller 170; I road input buffer 111, Q road input buffer 121 are exported the two-way orthogonal signal respectively to level thereafter synchronously, and C/A sign indicating number sequence storage unit is also exported the C/A sign indicating number of 1ms loop cycle synchronously simultaneously; I road block of registers 112, Q road block of registers 122 and C/A sign indicating number block of registers 102 controlled receiving sequences separately of beginning and processing get into division discriminating step 20 at this moment.
In division discriminating step 20, be that dividend, D are divisor with k (initial value 0), make its merchant be Y, remainder is X, constructs a bivector [X, Y], according to handling respectively behind the following condition distinguishing:
1) judges in the step 21; If k=0, i.e. X=Y=0 is [0 to the bivector assignment in step 22 then; 0]; Press the sequence order of signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with the local C/A sign indicating number of the B length of preface, deposit in separately in I road block of registers 112, Q road block of registers 122 and the C/A block of registers 102; K increases progressively 1 then;
2) judge in the step 23, if k is non-vanishing and be the n of D doubly (n is an integer), i.e. Y＞0 and X=0; Then the bivector assignment is [0 in step 24; K/D], continue to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposit I road block of registers 112 and Q road block of registers 122 separately in; Continue simultaneously to read the local C/A sign indicating number of B length and deposit C/A sign indicating number block of registers 102 in; K increases progressively 1 then;
3) like the judgement of step 23, if k is non-vanishing and be not the integral multiple of D also, get final product X＞0 and Y＞0, promptly change step 25 over to, bivector [X, Y] occurs with non-zero; Then continue to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposit I road block of registers 112 and Q road block of registers 122 separately in, k increases progressively 1 then;
More than 1), 2) and 3) three kinds of situation, from the carrying out flow process and can know of actual sequence, increase progressively gradually from 0 beginning from the k value; Only can select one of which each time and carry out,, must keep in corresponding data in I road block of registers 112, Q road block of registers 122 and the C/A sign indicating number block of registers 102 whenever carrying out once; Simultaneously can concrete bivector [X of assignment; Y], whenever obtain a bivector, then change next relevant accumulation step 30 over to.
In relevant accumulation step 30,102 the common mark of current data in said I road block of registers 112, Q road block of registers 122 and the C/A block of registers is designated as current X, the corresponding said bivector [X, Y] of Y value; Data in said I road block of registers 112 that again will be this moment and the Q road block of registers 122 respectively with C/A sign indicating number block of registers 102 in data make relevant accumulating operation, accordingly, processing element is the I road relevant totalizer 123 with the Q road of totalizer 113 of being correlated with; Each operation result that obtains still corresponding this moment is the bivector of assignment [X, Y], and preserves separately; Each relevant accumulation step 30 is carried out and is obtained an operation result and its corresponding bivector [X, Y], and preserves these corresponding results in order.
Confirm each operation result and corresponding bivector [X; Y] after; The capital gets into reset process 40; The effect of this step is to judge whether all data owing to the segmentation addition in the complete process dispose, so, with reference to the instantaneous value of k value; With k=D*C is to set up criterion; In determining step 41 if the result, know then that all data segmentation phase adduction is preserved for being and finish, so entering replacement step 42; With I road block of registers 112, Q road block of registers 122 and C/A sign indicating number block of registers 102 empty, k puts 0, all I roads, Q road zero intermediate frequency digital signal are initial reads and the initial original order of pressing each sequence that reads of sequence of local C/A sign indicating number is reset, and comprises that I road input buffer 111, Q road input buffer 121 read the data of (G*H-B*C) length respectively and read a little to reach the initial of each corresponding sequence of resetting on existing state.X, Y all put 0 in the bivector;
If in the determining step 41, the judged result of k=D*C does not mean that then the data that are used for matched filtering segmentation addition do not dispose, and still get back to other situation that step 2 is judged the k value this moment, in this example, gets back to step 23 and continues to judge the k value; As long as k is not incremented to net result D*C, division discriminating step 20 can be carried out repeatedly, all is able to preserve until bivector [X, Y] and corresponding operation result thereof.The method of this preservation is to obtain through depositing operation result in RAM matrix 140 through first buffer register 130 each time, and this RAM matrix is a two-dimensional storage environment, and its line number is that matched filtering block length B removes the half chip samples A that counts, promptly 83; Its columns is matched filter block number C, promptly 49.
When reset process 40 is able to complete execution; Be after 140 storages of RAM matrix finish, to get into reading step 50: in this reading step 50, under time schedule controller 170 controls; All operation results with 140 storages of RAM matrix; Read the FFT processing module 160 of level after arriving via second impact damper 150, all FFT conversion of finishing dealing with line by line by its row full line; The way of output of these RAM matrix 140 full lines, its each row are the row that the vector of all under the same X value is formed in the corresponding bivector [X, Y].
It is thus clear that, in the whole relevant processing procedure that adds up, block of registers; No matter be the block of registers of I road, Q road or C/A sign indicating number; Its length all is not more than the matched filtering block length B of setting, and through simulation optimization, controlled register length can be optimized; The design of convenient register resources distributes, and also is beneficial to the relevant accumulator module of being saved very much register resources.
The above is merely preferred embodiment of the present invention, so can not limit the scope that the present invention implements according to this, the equivalence of promptly doing according to claim of the present invention and description changes and modifies, and all should still belong in the scope that the present invention contains.
Claims (6)
1. relevant accumulation method of the segmentation that is used for the gps signal acquisition algorithm, it is characterized in that: it may further comprise the steps:
Step 1: initialization comprises: synchronizing sequence receives I, the Q road zero intermediate frequency digital signal from Digital Down Convert; Set periodic sampling in the C/A sign indicating number 1ms H that counts, the sampling number A of half chip, and the number C of the length B of a matched filter block and said matched filter block; Make D=B/A, D is an integer; Other establishes initial value is a variable k of 0;
Step 2: division is differentiated, and after the completion above-mentioned steps one, is that dividend, D are divisor with k, makes its merchant be Y, and remainder is X, constructs a bivector [X, Y]:
1) if X=Y=0, the sequence order of then press signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with B length this locality C/A sign indicating number of preface, deposit in separately in I road block of registers, Q road block of registers and the C/A block of registers of B length; K increases progressively 1 then;
2) if Y＞0 and X=0 then continue to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposit said I road block of registers and Q road block of registers separately in; Continue simultaneously to read the local C/A sign indicating number of B length and deposit said C/A sign indicating number block of registers in; K increases progressively 1 then;
3) if X＞0 and Y＞0 are then continued to read the I road of A length, the zero intermediate frequency digital signal on Q road, and deposited said I road block of registers and Q road block of registers separately in, k increases progressively 1 then;
Step 3: relevant adding up; After carrying out step 2, the common mark of current data in said I road block of registers, Q road block of registers and the C/A block of registers is designated as current X, the corresponding said bivector [X, Y] of Y value; Data in said I road block of registers that again will be this moment and the Q road block of registers respectively with C/A sign indicating number block of registers in data make relevant accumulating operation, the still corresponding said bivector of each operation result that obtains [X, Y], and preservation separately;
Step 4: reset: set up criterion with k=D*C; If; Then with said I road block of registers, Q road block of registers and C/A sign indicating number block of registers empty, k zero setting, all said I roads, Q road zero intermediate frequency digital signal are initial reads and the initial original order of pressing each sequence that reads of local C/A sign indicating number sequence is reset X=Y=0 in the said bivector; If not, then still get back to other situation that step 2 is judged the k value;
Step 5: read: will go up the said operation result that a step obtains, will wait the owner of X value mark to read each time, and all carry out FFT one by one and handle by the ordering of X.
2. according to the said a kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm of claim 1, it is characterized in that: said I road block of registers prime also is provided with input block, an I road, and said Q road block of registers prime also is provided with input block, a Q road; The control that this input block, I road and input block, Q road receive sequential circuit transfers to said I road block of registers and Q road block of registers with the I road zero intermediate frequency digital signal and the Q road zero intermediate frequency digital signal of correspondence respectively by its sequence order.
3. according to the said a kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm of claim 1, it is characterized in that: said C/A sign indicating number block of registers prime has a storer by sequence order circulation output C/A sign indicating number.
4. according to the said a kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm of claim 1; It is characterized in that: it is D that a line number is set; Columns is the storage matrix of C, and each said operation result deposits the capable Y row of the X corresponding cells of this storage matrix in by said bivector [X, Y]; In the said step 5 said storage matrix is read by the row full line.
5. according to the said a kind of relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm of claim 2; It is characterized in that: input block, I road described in the said step 4, input block, Q road are read the data of (G*H-B*C) length respectively on existing state; Simultaneously the reading pointer of said local C/A sign indicating number recovers initial value, reads a little with the initial of each corresponding sequence of resetting.
6. the relevant adding up device of the segmentation of a gps signal acquisition algorithm, it is characterized in that: it comprises:
One I road input buffer, its input end connects the I road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects an I road block of registers;
One Q road input buffer, its input end connects the Q road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects a Q road block of registers;
One C/A sign indicating number sequence storage unit, its output terminal connects a C/A sign indicating number block of registers;
Between said I road block of registers and C/A sign indicating number block of registers, has the relevant totalizer in I road; Has the relevant totalizer in Q road between said Q road block of registers and the C/A sign indicating number block of registers; The relevant relevant totalizer output terminal with the Q road of totalizer in this I road all is connected to one first buffer register;
The said first buffer register output terminal connects a RAM matrix, and this RAM matrix connects the FFT processing module through one second buffer register;
Wherein, the memory length of said I road block of registers, Q road block of registers and C/A sign indicating number block of registers is the matched filtering block length B of setting; The line number of said RAM matrix is removed the merchant D of half chip samples point for the matched filtering block length; Said RAM matrix column number is matched filter block number C; Other has time schedule controller to connect said I road input buffer, Q road input buffer, C/A sign indicating number sequence storage unit and said RAM matrix simultaneously.
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| CN109752740A (en) * | 2018-12-28 | 2019-05-14 | 航天信息股份有限公司 | A kind of method and system carrying out signal capture using multi-access-like segment correlation and FFT |
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