CN109492306B

CN109492306B - Association layer denotation method for design rule verification result

Info

Publication number: CN109492306B
Application number: CN201811338930.2A
Authority: CN
Inventors: 李桢荣; 吴琴霞
Original assignee: Huada Empyrean Software Co Ltd
Current assignee: Shenzhen Huada Jiutian Technology Co.,Ltd.
Priority date: 2018-11-12
Filing date: 2018-11-12
Publication date: 2020-04-07
Anticipated expiration: 2038-11-12
Also published as: CN109492306A

Abstract

A method for relabeling a design rule verification result at an association layer comprises the following steps: analyzing the design rule corresponding to the layout verification result to obtain the associated layer corresponding to the check; hiding a non-associated layer on the layout; the inverse height highlights the wrong location of the validation result. The associated layer reverse marking method of the design rule verification result only highlights the associated layer on which the design rule depends and hides all other layers except the associated layer, thereby avoiding that the analysis and judgment of a design engineer are influenced by overlapping of multiple layers of graphics in a reverse marking area, and further shortening the verification period.

Description

Association layer denotation method for design rule verification result

Technical Field

The invention relates to the field of automatic design of semiconductor integrated circuits, in particular to back-end layout design, design rule verification and layout debugging analysis in the automatic design of the semiconductor integrated circuits.

Background

Layout design and verification are important in the design process of the integrated circuit, the efficiency of the integrated circuit design can be effectively improved through efficient and accurate verification, and the risk of design failure is greatly reduced. However, as the process continuously progresses to the nanometer level, in the design of the ultra-large scale or even very large scale integrated circuit, the layout scale is expanded sharply, the time required for each verification of the layout is longer and longer, and the modification of the layout after each verification is more complicated and time-consuming because of the layout scale, so the iteration cycle of the layout verification and the modification of the layout is longer. At the present stage, the mainstream layout verification usually adopts technologies such as hierarchical verification and parallel verification to accelerate the layout verification, but because the scale is too large, the layout verification still consumes time each time.

The conventional layout verification comprises design rule verification and layout and schematic diagram consistency verification. After each design rule is verified, a design engineer needs to perform error checking analysis on the layout according to the result reported by the verification tool, the error position is highlighted by the error checking tool usually, a user analyzes all layer graphs in the area highlighted by the error position, and then analyzes the graph violating the design rule and modifies the layout correspondingly, but the number of layer layers used by the layout is also different according to the difference of layout design processes, the area highlighted often has several layers of graphs overlapping together, and the analysis of the design engineer can cause some obstacles to influence the efficiency.

Disclosure of Invention

In order to solve the defects in the prior art, the invention aims to provide a correlation layer denotation method for a design rule verification result, which highlights a correlation layer on which a design rule depends, hides all other layers except the correlation layer on a layout, and avoids the influence on analysis and judgment of a design engineer caused by overlapping of multiple layers of graphics in a denotation area.

In order to achieve the above object, the method for relabeling the design rule verification result at the association layer provided by the invention comprises the following steps:

1) analyzing the design rule corresponding to the layout verification result to obtain the associated layer corresponding to the check;

2) hiding a non-associated layer on the layout;

3) the inverse height highlights the wrong location of the validation result.

Further, the step 1) further comprises the following steps:

21) traversing and analyzing the design rule file, recording and calculating to generate an original layer and a middle layer of each middle layer, and recording the middle layer checked by each design rule;

22) recursively analyzing all original layers on which each intermediate layer depends;

23) and merging the original layers which are depended by all the middle layers checked by each design rule to serve as the associated layers of the design rule.

Further, the non-associated layer in step 2) refers to a layer in the layout except for the associated layer.

In order to achieve the above object, the present invention further provides a computer readable storage medium, on which computer instructions are stored, and the computer instructions execute the steps of the above method for associating layer denormal of the design rule verification result when executed.

When the design rule is verified after the layout design, the associated layer on which the design rule depends can be automatically analyzed according to the design rule to which the verification result belongs, all other layers except the associated layer on the layout are hidden, and then the anti-labeling highlighting is carried out, so that only the layer associated with the verification result can be displayed, and the problem of analysis obstacle caused by the overlapping of the irrelevant layers does not exist any more.

Therefore, the method can remove irrelevant layers and only display relevant layers, greatly facilitates the analysis of design engineer on the verification result of the design rule, and has great practicability on the shortening of the design period of the whole layout.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of an association-level denotation method of design rule verification results according to the present invention;

FIG. 2 is a schematic diagram of a design layout according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating layer results according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an anti-labeling highlight result according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Fig. 1 is a flowchart of an association-level denotation method of a design rule verification result according to the present invention, and the association-level denotation method of a design rule verification result of the present invention will be described in detail with reference to fig. 1.

Fig. 2 is a schematic diagram of a design layout according to an embodiment of the present invention. In the present invention, description will be given taking the layout shown in fig. 2 and "RULE checkrule1" in the following design RULE contents as an example.

layer( L1 1 )

layer( L2 2 )

layer( L3 3 )

layer( L4 4 )

layer( L5 5 )

AA0 = geom_inside( L4 L1 )

AA1 = geom_and( AA0 L3 )

RULE checkrule1 { space( AA1<2 region) }

AA2 = geom_not ( L2 L1 )

AA3 = geom_and ( L1 L5 )

RULE checkrule2 { space( AA2 AA3<5 region ) }

For convenience of description, the layout and the design rule of this embodiment are simplified, and it is assumed that L1, L2, L3, L4, and L5 are all the original layers appearing in the layout, and only the rule "checkrule1" is used for description in this embodiment.

First, in step 101, an associated layer of a layout verification result is determined.

In this step, the design rule corresponding to the verification result is analyzed to obtain the associated layer corresponding to the check. Specifically, the method comprises the following steps:

1) traversing and analyzing the design rule file, recording which original layers and middle layers are generated by operation of each middle layer, and recording which middle layers are checked by each design rule;

in this embodiment, the recorded middle layer AA0 is generated by the operation of the original layer L1 and L4, and the layer result generated by the layout is shown as AA0 in fig. 3; the middle layer AA1 is generated by the operation of a middle layer AA0 and an original layer L3, and the layer result generated by the layout is shown as AA1 in FIG. 3; the middle layer AA2 is generated by original layer L1 and L2 operations, and the middle layer AA3 is generated by original layer L1 and L5 operations. The check made in the design rule "checkrule1" relates to the middle layer AA1, and the check made in "checkrule2" relates to the middle layers AA2 and AA 3.

2) Recursively analyzing all original layers on which the intermediate layers depend for each intermediate layer;

the middle layer AA0 depends on the original layers L1 and L4; the middle layer AA1 depends on the middle layers AA0 and L3, and then the original layers on which the middle layer AA1 depends are L1, L3, and L4. The middle layer AA2 depends on the original layers L1 and L2; the intermediate layer AA3 depends on the original layers L1 and L5.

3) For each design rule, merging the original layers which are depended by all the middle layers checked by the design rule, namely the related layers of the design rule;

taking the design rule "checkrule1" as an example, the middle layer involved in the check is AA1, and the original layers on which AA1 depends are L1, L3, and L4, then all the original layers on which the design rule checkrule1 depends are L1, L3, and L4, that is, L1, L3, and L4 are associated layers of the design rule "checkrule 1".

In step 102, the non-associated layers on the layout are hidden.

In this step, all other layers on the hidden layout except the associated layer, that is, only the associated layer is displayed, specifically, in the present embodiment, L2 and L5 in the hidden layout, only the associated layers L1, L3 and L4 of the design rule "checkrule1" are displayed.

In step 103, the error position of the verification result is highlighted in a reverse marking mode.

In this step, the false position of the verification result is highlighted by the anti-mark.

Specifically, fig. 4 is a schematic diagram of an anti-labeling highlight result according to an embodiment of the present invention.

The invention further provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions execute the steps of the above-mentioned association-layer denotation method for the design rule verification result when running, and the association-layer denotation method for the design rule verification result is described in the foregoing section and is not described again.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A correlation layer denotation method for a design rule verification result is characterized by comprising the following steps:

the step 1) further comprises the following steps:

traversing and analyzing the design rule file, and recording and operating to generate an original layer and a middle layer of each middle layer; recording the middle layer checked by each design rule;

recursively analyzing all original layers on which each intermediate layer depends;

merging the original layers which are depended by all the middle layers checked by each design rule to serve as the associated layers of the design rule;

2) hiding a non-associated layer on the layout;

3) the inverse height highlights the wrong location of the validation result.

2. The method for denormalizing an associated layer of a design rule verification result according to claim 1, wherein the non-associated layer in step 2) is a layer in the layout except for the associated layer.

3. A computer readable storage medium having stored thereon computer instructions, wherein the computer instructions when executed perform the steps of the method for correlation level denormalization of a design rule validation result of any of claims 1-2.