CN104615793A

CN104615793A - Data description method capable of automatically realizing design of electronic system

Info

Publication number: CN104615793A
Application number: CN201310535485.XA
Authority: CN
Inventors: 刘伯安
Original assignee: Individual
Current assignee: Individual
Priority date: 2013-11-04
Filing date: 2013-11-04
Publication date: 2015-05-13
Also published as: WO2015062397A1

Abstract

The invention provides a data description method capable of automatically realizing the design of an electronic system. The data description method exhibits uniqueness, completeness and convenience. Data description realized on the basis of the method disclosed by the invention can realize one type of tool software which has the following characteristics: the tool software can automatically generate a symbol, a circuit and a layout of a circuit module, sets a variable parameter of the circuit module, has as few workloads including keyboard and mouse input operations as possible, has as few use experience requirements of EDA (Electronic Design Automation) tool software as possible, has as few revision and maintenance workloads of a design result as possible, changes a transplantation workload of a processing technology as few as possible, changes the transplantation workload of an original equipment manufacturer as few as possible and is especially suitable for designing a full-custom integration circuit.

Description

A kind of data description method automatically realizing electronic system design

Technical field

The present invention relates generally to auxiliary (the Engineer Design Assistant of the engineering design of electronic system, EDA) describing method of tool software institute usage data, the such as describing method of institute's usage data such as printed circuit board (PCB) eda tool software, integrated circuit eda tool software.Specifically, the present invention relates to and describe an electronic system by data, then automatically generate the circuit diagram of electronic system, the data description technique of printed circuit board diagram or integrated circuit diagram etc. based on these data by eda tool software.

Background technology

February nineteen forty-six, First electronic digital computer ENIAC is born in the U.S., in more than 30 year thereafter, the hardware and software of computer system product is all completed alone by a company, the i.e. software of the said firm's both hardware also scheduler system of scheduler system, the software development business development computer software of computer system company outsourcing can only be accepted by third party software company, and this situation is continued until 1981.In 1981, the IBM Corporation of the U.S. is by its personal computer (Personal Computer, PC) product has pushed market to and by the software of this product, hardware resources is open, this behave has expedited the emergence of independently third party's computer software company, these companies can self-developing computer software direct in market sale, the kind of computer application software and quantity have had a lasting rapid growth, make to there has also been a lasting rapid growth to the demand of computer system, impel design and the process technology of integrated circuit, the hardware and software technology etc. of computing machine has had a high-speed developing period more than 30 years, the use of high-performance computer spreads to small business and family, computing machine and auxiliary (EDA) tool software of engineering design have become the indispensable instrument of slip-stick artist.

In the design process of electronic system, eda tool software is widely used, printed circuit design and integrated circuit (IC) design are the major domains using eda tool software, design process comprises electric circuit diagram design, the emulation of system work process, the layout design of P.e.c. or integrated circuit, comprise the emulation etc. of the system work process of domain impact, electric circuit diagram design wherein and layout design process have very high efficiency under the help of eda tool software, but still need to expend more human resources, and it is also higher to the training requirement of human resources (slip-stick artist), the target of patented method of the present invention is to provide a kind of simple and direct data description method, make eda tool software can do more routine work automatically, expending and training requirement to human resources to human resources in further reduction electronic system design process.

Be supplied to the data that eda tool software carries out process automatically, uniqueness and completeness must be had, here uniqueness refers to that eda tool software can not carry out same operation based on different data or carry out different operations based on same data, here completeness refers to that eda tool software can complete all operations target based on data, under the prerequisite ensureing uniqueness and completeness, reduce the target that data volume is the inventive method as much as possible, reducing data volume is improve the effective means of design and maintenance work efficiency.

Explanation of nouns

In the description of this patent method, with or word adds the following noun that parantheses and numeral occur and all has the implication of following explanation.

Accompanying drawing explanation

Below first the accompanying drawing of instructions of the present invention is simply introduced, and then in conjunction with these accompanying drawings, each enforcement example of the present invention is introduced, principle of the present invention and feature are described.

In figures in the following:

Fig. 1 realizes according to a preferred embodiment of the present invention (0000) schematic diagram;

Fig. 2 realizes according to a preferred embodiment of the present invention (1000) one of schematic diagram;

Fig. 3 realizes according to a preferred embodiment of the present invention (1000) schematic diagram two;

Fig. 4 realizes according to a preferred embodiment of the present invention (1000) schematic diagram three;

Fig. 5 is the simple and direct describing method schematic diagram of the inner circuit module (0200) different to the identical component parameter of circuit structure of simple and direct description (0600) according to preferred embodiment realization of the present invention;

Fig. 6 realizes according to a preferred embodiment of the present invention (2000) schematic diagram;

Fig. 7 realizes according to a preferred embodiment of the present invention (3000) schematic diagram;

Fig. 8 realizes according to a preferred embodiment of the present invention (4000) one of schematic diagram;

Fig. 9 realizes according to a preferred embodiment of the present invention (4000) schematic diagram two;

Figure 10 realizes according to a preferred embodiment of the present invention (4100) schematic diagram;

Figure 11 realizes according to a preferred embodiment of the present invention (4200) schematic diagram;

Figure 12 realizes according to a preferred embodiment of the present invention (5000) schematic diagram of list;

Figure 13 realizes according to a preferred embodiment of the present invention (5200) schematic diagram of list;

Figure 14 realizes according to a preferred embodiment of the present invention (5300) schematic diagram of list;

Figure 15 realizes according to a preferred embodiment of the present invention (5400) schematic diagram of list;

Figure 16 realizes according to a preferred embodiment of the present invention (5500) schematic diagram of list;

Figure 17 realizes according to a preferred embodiment of the present invention (9090) schematic diagram of list;

Figure 18 realizes according to a preferred embodiment of the present invention (5230) schematic diagram;

Figure 19 realizes according to a preferred embodiment of the present invention (5330) schematic diagram;

Figure 20 realizes according to a preferred embodiment of the present invention (5240) schematic diagram;

Figure 21 realizes according to a preferred embodiment of the present invention (5250) schematic diagram;

Figure 22 realizes according to a preferred embodiment of the present invention (9080) schematic diagram;

Figure 23 realizes according to a preferred embodiment of the present invention (9100) schematic diagram;

Figure 24 realizes according to a preferred embodiment of the present invention (9110) schematic diagram.

Figure 25 realizes according to a preferred embodiment of the present invention (9120) schematic diagram.

Figure 26 realizes according to a preferred embodiment of the present invention (9130) schematic diagram.

Figure 27 realizes according to a preferred embodiment of the present invention (9140) schematic diagram.

Embodiment

What the present invention related generally to is a kind of data description method, makes slip-stick artist right (0100) the least possible information is inputted when understanding very few, just can be by automatic realization (0200) (0203), (0205), (0206) and arrange (0204).

First the framework (to five) of data description method of the present invention is below described, and then the feature (six to ten) of the inventive method is described.

(0000) be according to method of the present invention (0001) set of the data prepared, Fig. 1 is the schematic diagram of design data, is made up of, is respectively five grouped datas (1000), design rule (2000), (3000), (4000), (5000) list etc.

Right when list etc. are described, first not to repeatedly occurring (9000), (9010), (9020), (9030), (9040), (9050), (9060), (9070), (9080), etc. (9090) be described, will be described thereafter.

One, (1000) explanation

the whole of description deviser design name and the set of grouped data.

Circuit module is called Cell by general software, and divide into groups with Library and one or more levels Category, method of the present invention continues this method, but the grouping rank of information is restricted to 4 grades at the most, with address Cell, with (0400) call Library, respectively with (0401), (0402), (0403) the multistage Category of address such as.Same in, name need unique.

Fig. 2, Fig. 3, Fig. 4 are schematic diagram, data to comprise (0201), and to be subordinate to (0400) (0401), (0402), (0403), data are generally determined by deviser, quantity all do not limit.

may reside in or or or under.

Two, (2000) explanation

it is the set of P.e.c. or integrated circuit technology data, comprise the information such as design rule (Design Rule) of technique physical parameter, domain, as electric parameter, mechanical parameter, minimum and maximum line width, minimum spacing, etc., data are often divided into several groups data are generally produced family (Foundry) by generation processing and are provided.

Method of the present invention adopts the method for grouping to be described, and Fig. 6 is the schematic diagram of design rule, with the classification of rule classification (2001) address, with (2002) address rule, with (2003) rule name and data are called.

Three, (3000) explanation

be the set of custom parameter, in automatic generation and setting deng time use, good custom parameter, is conducive to design data more succinct and readable better, generally defined by deviser, its quantity does not limit.

Method of the present invention also adopts the method for grouping to be described, and Fig. 7 is schematic diagram, with (3001) address classification, with (3002) parameter is called, with (3003) parameter name and data are called.

Each remove outward, 3 substances are also had: (3004), (3005), (3006).

the content that must arrange, type as string variable (string), integer variable (int), floating-point variable (float), length variable (1ength), Boolean variable (boolean) etc. by decision is set, wherein length variable is used in layout design, need when data processing to be multiplied by a scale-up factor (hereinafter referred to as length factor), such as, in the design of integrated circuit, length factor can be set to 1.0e6, when the channel length of a MOS transistor is 100.0n, the value of its length variable is floating number 0.1.

If in quote time the information errors that provides or owe clear and definite, then settings be used. to arrange can be system function, also can be comprising of software convention with etc. the agreement function of information, it also can be the callable function that deviser defines.

with setting data can not had.

Remove outward, can also comprise (9100) and parameter quote the content of (9110), but can not direct or indirect oneself quote, with illustrate, refer to the relevant portion in " data referencing explanation " in the subsequent content of this instructions.

If have (0204), in module parameter, one is defined grouping, this grouping be all lookup protocol 's .

Four, (4000) explanation

be in modular circuit and middle placement (0300) set of data.

Fig. 8, Fig. 9 are schematic diagram, with (0400) be one-level grouping, with (0300) be secondary data packets, three grades of groupings be with (0301) or (0302) head the list of signers (0305), its content comprises (0303), (0304), (4100), (4200) etc. example determined by deviser, its quantity does not limit.

Figure 10 is (4100) schematic diagram, relevant setting comprises (4010), (4011), (4020), (4021), (9020), (9030), (9060), (9070) etc.

Figure 11 is (4200) schematic diagram, relevant setting comprises (4010), (4011), (4020), (4021), (9030), (9060), (9070) etc.

need to change the title of variable element and assignment, assignment can directly be arranged, and also can be that a rule invocation or parameter are quoted, each can not have or have multiple quantity can not exceed variable element quantity, be list.

be or middle needs connect (0308) title and connection thereof (5000) title, by example whole and (9000) list.

with be the coordinate of reference point.

Five, (5000) tabulate

be (0203), (0205), (0206) electrical network in (5002), (9000), (5100), (5200), (5300), (5400), (5500) set of data such as, Tu12Shi the schematic diagram of list, list is determined by deviser, quantity do not limit.

be type, have the selection such as input, output, two-way, network, substrate (substrate), N trap (N-well), P trap (P-well), wherein input, export, two-way etc. represents should ? in have pin, network represents this be inner signal network, does not have outside connection, and substrate, N trap, P trap etc. represent should only in circuit diagram, there is line, without connecting up but may needing to place layer mark in domain.

with ? deng operation in all likely use.

if be set up, representing should it is a bus network.

Also comprise in Figure 12 (5100) schematic diagram, provide in automatically generate the setting of this network pin. there is the parameter that three basic, the first (5101), representing should ? in orientation, have the selection of four, upper and lower, left and right; It two is (5102), represent that this network pin exists in position coordinates; It three is (5103), represent whether be a Low level effective signal or minus polarity signal, so that determine whether will be in should on add a small circle.

Figure 13 is (5200) schematic diagram of list, its content comprises (9000), (9010), (9020), (9090) list, (5220), (5230), (5240), (5250) etc.

there are single line and bus two selection, so that automatically with different width and color line.

Figure 18 is (5230) if be set up, schematic diagram, represents that this line needs to add (5001) label (Label).

Figure 20 is (5240) if be set up, schematic diagram, represents that this line needs to add (5001) pin, pin type comprises and the selection such as to connect between input, output, two-way, paging.

Figure 21 is (5230) if be set up, schematic diagram, represents that this line is a connectionless networks, need to add without linkage flag.

Figure 14 is (5300) arrange the schematic diagram of Yuan, its content comprises (9000), (9010), (9030), (9090) list, (5320), (5330), (5340) etc.

Type of wiring has rectangle and cabling two selection.Rectangular wiring needs the position arranging a pair diagonal angle as wire location.Cabling wiring needs to arrange also need embody line end shape in data to select, the length of link position list is greater than or equals 2.

Figure 19 is (5330) if be set up, schematic diagram, represents that this wiring needs to add (5001) label (Label), (5331) need to arrange, (5332) be one (9080).

Figure 15 is (5400) schematic diagram of list, its content comprises (9000), parameter (9010), (9030), (9040), (9050), (9060), (9070), (5420), (5430) etc.

with be the coordinate of reference point.

Network pin shapes is about decided to be rectangle, with rectangle length and width.

Figure 16 is (5500) schematic diagram of list, its content comprises (9000), (9010), (9050), (9060), (9070), (5520) etc.

with be the coordinate of reference point.

the content of selective listing is generally provided by man of foundry.

Six, (0600) explanation

In design time, can run into need design multiple same circuit structure but in circuit components and parts there is different parameters the invention provides a kind of simple and direct describing method, make multiple share one group of description.

Such as: CMOS phase inverter is made up of a P type and a N-type MOS transistor, raceway groove number (finger) and the channel width (width) of MOS transistor all can have multiple change, and Fig. 5 is of the present invention providing to the schematic diagram that CMOS phase inverter describes.

Suppose that CMOS phase inverter belongs to baseCell, its first-level class be CMOS, be driver, be inv, under baseCell/CMOS/driver/inv, Fig. 5 gives and adopts realization of the present invention a preferred embodiment schematic diagram of CMOS phase inverter.

In Figure 5, simple and direct list (0620) gives the list of simple and direct variable (0603) and the name prefix of circuit module, name prefix is inv, and have finger and width two simple and direct variablees, they are the variable element of PMOS and nmos pass transistor, the change of finger has 2, called after M1 and M2 respectively, the change of width also has 2, respectively called after W0 and W1, automatic generation 4 simple and direct descriptions (0600), respectively:

invM1W0/finger=0／width=0

invM1W1/finger=0／width＝1

invM2W0／finger=1／width=0

invM2W1/finger=1／width=1

Above-mentioned in, invM1W0, invM1W1, invM2W0, invM2W1 are the name of circuit module respectively, finger=0 and finger=1 etc. represent the sequence number of finger change, width=0 and width=1 represents the sequence number that width changes.

Width=(“W0”“W1”“W2”“W3”“W4”)

In order to arrange finger and the width parameter of PMOS and nmos pass transistor, also need (3000) and (4000) take corresponding behave in, a kind of method of optimization is as follows:

? middle definition:

fetF=(12)

pfetW=(240.0n340.0n)

nfetW=(120.0n170.0n)

FetF is int variable column Yuan, pfetW and nfetW is length variable column Yuan, supposes that they all belong to (3001) VAR.

In PMOS 's middle interpolation optimum configurations:

finger=VAR／fetF／Cell／finger

width=VAR／pfetW／Cell／width

In PMOS 's middle interpolation

finger＝VAR／fetF／Cell/finger

width＝VAR／nfetW／Cell／width

Cell/finger and Cell/width represent respectively from (Cell) obtain the sequence number of finger and width in, obtain the lists such as fetF, pfetW, nfetW respectively according to sequence number value, at example PMOS and nmos pass transistor etc. time to parameter f inger and width assignment, assignment method by determine, method getparms refers to follow-up relevant explanation.

Finger and width of the PMOS of CMOS phase inverter invM1W0 be respectively 1 and 240.0n, NMOS tube finger and width be respectively 1 and 120.0n.

Finger and width of the PMOS of CMOS phase inverter invM1W1 be respectively 1 and 340.0n, NMOS tube finger and width be respectively 1 and 170.0n.

The PMOS finger of CMOS phase inverter invM2W0 and width be respectively 2 and 240.0n, NMOS tube finger and width be respectively 2 and 120.0n.

Finger and width of the PMOS of CMOS phase inverter invM2W1 be respectively 2 and 340.0n, NMOS tube finger and width be respectively 2 and 170.0n.

also can realize by other similar method, but no matter how realize, equal demand fulfillment following requirements:

1, the parameter name list of uniqueness is ensured;

2, the name list of the Parameters variation corresponding with each element of parameter name list of uniqueness is ensured;

3, the data referencing list of the parameter corresponding with each element of parameter name list of uniqueness is ensured;

4, supplemental characteristic row Yuan corresponding with data referencing list of uniqueness is ensured;

5, the method for the exercisable data that get parms according to data referencing list content;

6, the exercisable value by supplemental characteristic is assigned to by the method for the components and parts of example.

Seven, data referencing explanation

In the method for the invention, data referencing comprises (9100), (9110), (9120), (9130), (9140) etc.

(9160) be orientation arrange, the target of arranging to be cited is rectangle, have upper (rectangle coboundary), under (rectangle lower boundary), left (rectangle left margin), right (rectangle right margin), X (rectangular horizontal direction mid point), the selection such as Y (rectangular vertical direction mid point), what X, left and right expression were quoted is transverse axis coordinate data, the ordinate of orthogonal axes data that Y, upper and lower expression are quoted.

(9170) to of the same name collective quote the processing selecting of result, have do not arrange, minimum value, maximal value, deng selection.

? in, do not have with no with therefore need from result in select transverse axis coordinate data or ordinate of orthogonal axes data.

Data referencing needs to arrange (9080), to table data quote also need arrange (9090), illustrate and refer to with explanation.

1, (9100) explanation

Figure 23 is schematic diagram, content comprise (9200), deng.

content comprise (2001), (2002).

2, (9110) explanation

Figure 24 is schematic diagram, content comprise (3001), (2002), (9200), deng.

content comprise (3001), (3002).

? definition in, Ke Yiyou xiang He , but can not direct or indirect oneself quote.

3, (9120) explanation

Figure 25 is schematic diagram, content comprise (9000), select (9030), (9200), (9150), deng.

content comprise (0400), (0301), (0305), (0304) etc.

(9150) be or in one of content.

4, (9130) explanation

Figure 26 is schematic diagram, content comprise (9000), (9030), (9200), deng.

content comprise (5001), (5410) etc.

5, (9140) explanation

Figure 27 is schematic diagram, the content of rule invocation comprises (9000), (9030), reference object (9200), deng.

content comprise (5001), (5510) etc.

The content of above-mentioned data referencing meets the requirement of adequacy and uniqueness, makes can be correct carry out data referencing.

6, (9180) explanation

In the method for the invention, form be the prefix character string that can separate with separator (such as: slash) with comprise the heavy floating number of field delimiter or the character string of floating number list, in order to value distinguish, value or row Yuan Yuansu value can not be integer character string. can be table data by non-row Yuan data-mapping, also can each element in table data be given different value.Prefix character string is determined the heavy territory mapped or the heavy territory of data transformation, refer to the relevant portion in follow-up many places data list explanation.

7, (9190) explanation

In the method for the invention, be the parameter needing when data referencing to arrange, it comprises the heavy integer of field delimiter or the character string of Integer List, if (9210) be not a list, then index of reference arrange meaningless.Suppose length be L, in list, the index value of first element is one of 0 or 1, is determined by tool software, value or the value of list element is I, then must have 0≤I<L or 1≤I< (L-1) to ensure do not go beyond the scope.Due to can be right element repeated citing, list length can exceed quotes the results list length, therefore (9220) arrange Yuan Changdu can exceed list length.

Nine, data arrange explanation

Be below in many places by the explanation that the data used are arranged.

1, (9000) explanation

Bus parameter has multiple method to set up, can generate relevant by bus parameter (9001):

A. positive integer K: <0:abs (K)-1>;

B. negative integer K: <abs (K)-1:0>;

C. Integer List (K...E) and abs (K) <abs (E): <0:abs (K)-1>;

D. Integer List (K...E) and abs (K) >abs (E): <abs (K)-1:0>.

Suppose that N is a positive integer, so:

A.<0:N-1> represents the Integer List of <01... (N-2) (N-1) >, and list length is N;

B.<N-1:0> represents < (N-1) (N-2) ... the Integer List of 10>, and row Yuan Changdu is N.

In the method for the invention, be the parameter with multiple implication, illustrate respectively below.

A. with

be set up expression to need for every sub-line of bus places one

B.

be set up expression to need for every sub-line of bus places one

C.

be set up expression to need for every sub-line of bus places one

D.

be set up expression to need for every sub-line of bus places one

E.

be set up expression to need for every sub-line of bus places one

F.

be set up expression be distributed on every sub-line of bus.

G.

be set up expression be distributed on every sub-line of bus.

H.

be set up expression be distributed on every sub-line of bus.

2, (9010) explanation

Exampleization one time, often there is a numeric parameter, suppose that the title of this parameter is M, numerical value is N, so represent this need to repeat in module domain to place N number of and pin connects identical, in the method for the invention, numerical value of N being given should 's ? be greater than 1 expression distribution corresponding with the unit module repeating to place.

3, (9020) explanation

Generally, the page size of circuit diagram can be arranged to the size that A0, A1, A2, A3, A4, A5 etc. can export with draught machine, nearly all circuit diagram can draw completely in one page, but in order to use and file conveniently, the size of A5 is too little, and A0, A1, A2, A3 etc. often can not with common printer outputs, and A4 is the optimal selection of circuit diagram page size, therefore method of the present invention does not support the circuit diagram without paging, all all adopt paging, therefore with need to arrange etc. not having its with corresponding 's it is identical, be exactly the title of circuit diagram paging, by determine.

4, (9030) explanation

with need to arrange wiring or the layer residing for pin, also need to arrange the layer quoted, layer selects data to be provided by man of foundry, and method of the present invention, in design rule, adds one layer, each layer is selected to be in Layer layer is selected to be unified in framework under.

5, (9040) explanation

? middle placement time, setting that often can not be simple and direct or reference point coordinate, that the orientation that coordinate is arranged is selected, have, upper and lower, left and right, a left side/under, left/upper, right/under, right side/first-class selection, the orientation that denotation coordination is arranged respectively is mid point, top mid point, following mid point, left side mid point, the right mid point, the lower left corner, the upper left corner, the lower right corner, the upper right corner etc.

6, (9050) explanation

? or middle placement wiring label, circuit pin, unsettled mark etc., need to arrange have the selections such as R0, R90, R180, R270, MX, MY, MXR90, MYR90, do not rotate when representing placement module respectively or overturn, 90-degree rotation angle, revolve turnback angle, rotate 270 degree angles, with X-axis be with reference to mirror image switch, with Y-axis be with reference to mirror image switch, with X-axis be after reference mirror image switch again 90-degree rotation angle, take Y-axis as 90-degree rotation angle etc. again after reference mirror image switch.

7, (9090) tabulate

list is or coordinate points list, Tu17Shi the schematic diagram of list, list length needs to be more than or equal to 2, does not have maximum number quantitative limitation.

Each link position by (9060) and (9070) form, with be

8, (9080) explanation

be or middle placement deng or figure 22 is schematic diagram, pass through deng, obtain raw data list and export after the summation of its element.

in the quantity of referenced items do not limit, if only had in the referenced items of coordinate data with then need by with or reference coordinate value be added after export.

Ten, multiple table data explanation

Below the multiple table data used in method of the present invention is described.

? time, if be set up, suppose length be B, so need exampleization B each title by with the element value of middle correspondence determines, as mistake:

A. ：nfet

B. ：db

C. ：[0：7]

So the 3rd routine assumed name claim can be nfet_db2 or nfet_db_2 etc., the module hereinafter referred to as like this name is (9230).

Represent with B below length, if be not set up, B is 1.

? time, if value is greater than 1 for M=3, then need repetition exampleization M example assumed name claims also to need difference to identify, by determining, is below common title:

A. without arranging: nfet_db.1, nfet_db.2, nfet_db.3 etc.;

B. be set up: nfet_db2.1, nfet_db2.2, nfet_db2.3 etc.

Represent with M below

Some there is bus pin, represent certain pin with T below length, if be not set up, then T is 1.? in a pin be equivalent to T pin, in a pin be exactly T pin.

Some there is pin of the same name, represent with P below the quantity of certain pin of the same name.

? in, with be all a length be the list of B, in, it is one (B, M) double list.

? with in network perforation, with it is the list of (B, M, T, a B) quadruple.

? in result be one (B, P) double list, also need to consider it when carrying out data processing setting. in result be the list of (B, M, T, a P) quadruple.Pin is quoted and the result quoted of boring a hole is all the list of (B, M, T, a P) quadruple.B represents and is distributed in on pin of the same name, T represents on bus pin.

with result be a scalar or list.

can be that Yuan or triple list or quadruple list are rearranged in a list or two.

Therefore in the method for the invention, need to produce multiple different table data, also need to change mutually to mate data, illustrate below.

1, directly arrange

The method of direct setting is exactly for each heavy territory of multiple list defines a separator, arranges list by the character string comprising separator, determines which heavy domain list the substring of character string belongs to, thus produce the list needed according to separator.Use below be set to example illustrate a preferred implementation method.

there is R0, R90, R180, R270, MX, MY, MXR90, MYR90 etc. 8 selection.Define four separators (# ,=, * ,+) four heavy territories of respectively corresponding (B, M, T, P) quadruple list.

One complete setup string:

R0+R90*R180+R270=MX+MY*MXR90+MYR90#MYR90+MXR90*MY+M X=R270+R180*R90+R0

First use separator " # " corresponding to " B " that character string is divided into substring:

(R0+R90*R180+R270=MX+MY*MXR90+MYR90

MYR90+MXR90*MY+MX＝R270+R180*R90+R0)

Then separator "=" corresponding to " M " is used to continue character string to separate:

((R0+R90*R180+R270 MX+MY*MXR90+MYR90)

(MYR90+MXR90*MY+MX R270+R180*R90+R0))

Separator " * " corresponding to " T " is used character string to be separated further again:

(((R0+R90 R180+R270)

(MX+MY MXR90+MYR90))

((MYR90+MXR90 MY+MX)

(R270+R180 R90+R0)))

Separator "+" corresponding to " P " is finally used to be divided in character string by character string:

((((R0 R90) (R180 R270))

((MX MY) (MXR90 MYR90)))

(((MYR90 MXR90) (MY MX))

((R270 R180) (R90 R0))))

So just obtain (B, M, T, P) quadruple list arrange, if the data type of multiple list is not character string type, then need each element of multiple list to be converted to corresponding data type.

Generally, do not need above-mentioned complete setting, the setting of simplification can be used, when the change not arranging heavy territory is considered as the variable change when this heavy territory, arranges and do not change.

The most simply arranging is occurs without any the separator of variable, such as R0, when representing that four heavy domain variablies change, arrange and all do not change.

Secondary simple setting only has the separator of a heavy domain variable to occur, such as R0#R90, R180=R270, MX*MY, MXR90+MYR90 etc., when indicating a heavy domain variable change, change.

The separator of double or three heavy domain variablies can also be only had to occur, indicates double or three heavy domain variablies change time, change.

To the list length not having the heavy territory arranged then to need to arrange this heavy territory.

Above-mentioned direct setting method, can be applied to deng setting, repeat no more.

2, assignment and arithmetic is mapped

Process multiple list assignment or monodrome, list, arithmetic between multiple list time, the method that the present invention takes is as follows:

When A, single-value data and list or multiple row Yuan Jinhang arithmetic, each element of single-value data and list or multiple list carries out four fundamental rules;

When arithmetic is carried out in B, list and list, the length of two lists needs equal, each element to carry out arithmetic respectively;

When arithmetic is carried out in C, multiple list and multiple list, when the multiple lengths of two multiple lists needs equal, each element to carry out arithmetic respectively;

D, list and multiple row Yuan Jinhang arithmetic time, arithmetic is carried out in the change that list is mapped to a heavy variable of multiple list, illustrates below.

Suppose a list R and (B, M, T, a P) multiple list D respectively:

R= (R0 R1)

D=((((0.0 0.5)(1.0 1.5))

((2.0 2.5)(3.0 3.5)))

(((4.0 4.5)(5.0 5.5))

((6.0 6.5)(7.0 7.5))))

When R and D carries out arithmetic, R is mapped in the change of a heavy domain variable of D, heavy territory is selected to represent by the mapping prefix that separator (such as: slash) separates with one, and mapping prefix is in this example B, M, T, P respectively, and here is that D and R is added four kinds of situations.

D+B/R=((((0.0+R0 0.5+R0)

(1.0+R0 1.5+R0))

((2.0+R0 2.5+R0)

(3.0+R0 3.5+R0)))

(((4.0+R1 4.5+R1)

(5.0+R1 5.5+R1))

((6.0+R1 6.5+R1)

(7.0+R1 7.5+R1))))

D+M/R=((((0.0+R0 0.5+R0)

(1.0+R0 1.5+R0))

((2.0+R1 2.5+R1)

(3.0+R1 3.5+R1)))

(((4.0+R0 4.5+R0)

(5.0+R0 5.5+R0))

((6.0+R1 6.5+R1)

(7.0+R1 7.5+R1))))

D+T/R＝((((0.0+R0 0.5+R0)

(1.0+R1 1.5+R1))

((2.0+R0 2.5+R0)

(3.0+R1 3.5+R1)))

(((4.0+R0 4.5+R0)

(5.0+R1 5.5+R1))

((6.0+R0 6.5+R0)

(7.0+R1 7.5+R1))))

D+P／R＝((((0.0+R0 0.5+R1)

(1.0+R0 1.5+R1))

((2.0+R0 2.5+R1)

(3.0+R0 3.5+R1)))

(((4.0+R0 4.5+R1)

(5.0+R0 5.5+R1))

((6.0+R0 6.5+R1)

(7.0+R0 7.5+R1))))

The situation that D with R is multiplied is the same, by in equation above+change * into, D with R subtracts each other, subtrahend is got negative after be added, D with R be divided by, and is multiplied after divisor being got inverse, the value of R imparting D is equivalent to D that R and element be 0 and is added or R is multiplied with the D that element is 1.

The method that above-mentioned substance maps, can be applied to deng setting, repeat no more.

3, multiple list transform

In the method for the invention, need to rearrange multiple list, the form rearranged has two kinds, a kind of form is the data exchange between two heavy territories, another kind of form is that the data in two heavy territories are incorporated into one of them heavy territory, the list length in merged heavy territory becomes 1, illustrates multiple list transform method of the present invention below.

Suppose there is (B, M, T, P) multiple list D as follows:

D＝((((0.0 0.5)(1.0 1.5))

((2.0 2.5)(3.0 3.5)))

(((4.0 4.5)(5.0 5.5))

((6.0 6.5)(7.0 7.5))))

The result E heavy for the B of D numeric field data and the heavy numeric field data of T being carried out exchanging is as follows:

E＝((((0.0 0.5)(4.0 4.5))

((2.0 2.5)(6.0 6.5)))

(((1.0 1.5)(5.0 5.5))

((3.0 3.5)(7.0 7.5))))

By as follows for the result K that the data in the data in heavy for the B of D territory and the heavy territory of P are incorporated into the heavy territory of P:

K=((((0.0 0.5 4.0 4.5)

(1.0 1.5 5.0 5.5))

((2.0 2.5 6.0 6.5)

(3.0 3.5 7.0 7.5))))

The method of above-mentioned multiple row Yuan Bianhuan, can be applied to deng setting, with substance mapping class seemingly, before setting data increase a conversion prefix of separating with separator (such as: slash), repeat no more.

Use above-mentioned etc. method, meet automatic realization 's with time requirement to mutual coupling between data list.

Automatically the data description method realizing electronic system design of the present invention, with through checking, also have based on the data of description that the inventive method realizes, a kind of following features that has can be realized

● automatically generative circuit module symbol, circuit, domain and its variable element is set;

● the workload of the input operations such as the least possible keyboard and mouse;

● the use experience requirement of the least possible eda tool software;

● the amendment of the least possible design result and maintenance workload;

● the transplanting workload of the least possible change processing technology;

● the transplanting workload of the least possible man of change foundry;

● be particularly useful for the design of full custom ic.

Use data description method of the present invention, add suitable line and (or) routing strategy, just can be by automatically realize automatic connecting and (or) the wiring of modular circuit, further reduce the workload of electronic system design.

Claims

1. the identical but method for the circuit module of Parameters variation of the multiple circuit structure of simple and direct description, comprising:

A) a parameter name list is set;

B) the change name list of one or more parameter corresponding with each element of parameter name list is set;

C) the data referencing list of one or more parameter corresponding with each element of parameter name row Yuan is set;

D) one or more supplemental characteristic list corresponding with data referencing list is set;

E) method of the exercisable data that get parms according to data referencing list content;

F) the exercisable value by supplemental characteristic is assigned to by the method for example components and parts.

2. give a method for multiple list indirect assignment by character string, comprising:

A) for each of multiple list redefines a separator;

B) an assignment character string is set;

C) multiple data assignment of being separated by separator of exercisable substep are to the method for list;

D) the exercisable method multiple list character string being converted to multiple List data Type.

3. the assignment between monodrome, list, multiple list etc. and a method for arithmetic, comprising:

A) assignment and the arithmetic such as monodrome and monodrome, list and list, multiple list and multiple list, direct or corresponding element carries out assignment and arithmetic;

B) assignment and the arithmetic such as monodrome and list, monodrome and multiple list, monodrome and each element carry out assignment and arithmetic;

C) assignment of list and multiple list and arithmetic, list carries out assignment and arithmetic with a heavy territory of selected multiple list.

4. a transform method for multiple table data, comprising:

A) data in any two heavy territories of the exercisable multiple list method of carrying out exchanging;

B) the row Yuan Changdu in another heavy territory is become the method for 1 by the exercisable data by any two heavy territories of the multiple list heavy territory be incorporated among two heavy territories simultaneously.

5. quote a method to set up for technical parameter or custom parameter request, comprising:

A) group names is set;

B) rule or parameter name are set;

C) selectable arrange one map prefix;

What d) exercisable method as claimed in claim 2 was arranged quotes ratio;

E) index of reference of exercisable method setting as claimed in claim 2.

6. quote a method to set up for the component's feet position requests in circuit diagram or domain, comprising:

A) the routine assumed name arranging components and parts claims;

B) bus parameter is set;

C) number parameter is set;

D) pin name is set;

E) selectable arrange one conversion prefix;

What f) exercisable method as claimed in claim 2 was arranged quotes orientation;

What g) exercisable method as claimed in claim 2 was arranged quotes ratio;

H) layer that exercisable method as claimed in claim 2 is arranged is selected.

I) arrange one and quote sequence;

J) index of reference of exercisable method setting as claimed in claim 2.

7. quote a method to set up for the Pin locations request in domain, comprising:

A) network name is set;

B) pin name is set;

C) bus parameter is set;

D) number parameter is set;

E) selectable arrange one conversion prefix;

What g) exercisable method as claimed in claim 2 was arranged quotes ratio;

H) layer that exercisable method as claimed in claim 2 is arranged is selected;

I) arrange one and quote sequence;

J) index of reference of exercisable method setting as claimed in claim 2.

8. quote a method to set up for the punch position request in domain, comprising:

A) network name is set;

B) a perforation title is set;

C) bus parameter is set;

D) number parameter is set;

E) selectable arrange one conversion prefix;

What g) exercisable method as claimed in claim 2 was arranged quotes ratio;

H) layer that exercisable method as claimed in claim 2 is arranged is selected;

I) arrange one and quote sequence;

J) index of reference of exercisable method setting as claimed in claim 2.

9. a method to set up for coordinate data, comprising:

A) the rule invocation request of selectable method setting as claimed in claim 5;

B) the parameter quote request of selectable method setting as claimed in claim 5;

C) the cell refernce request of selectable method setting as claimed in claim 6;

D) the pin quote request of selectable method setting as claimed in claim 7;

E) the perforation quote request of selectable method setting as claimed in claim 8;

F) exercisable method as claimed in claim 3 will quote the method that result and reference coordinate value (if necessary) are sued for peace together;

G) exercisable method as claimed in claim 4 will quote the method for result conversion.

10. the method to set up of the example request of components and parts in modular circuit or module domain; Comprise:

A) bus parameter is set;

B) number parameter is set;

C) list of a components and parts variable element is set;

D) list of a component's feet and connection thereof is set;

E) placement direction of exercisable method setting as claimed in claim 2;

F) the transverse axis coordinate that arranges of exercisable method as claimed in claim 9 and ordinate of orthogonal axes.

11. place label, pin, a method to set up of asking without linkage flag etc. in circuit diagram, comprising:

A) placement direction of exercisable method setting as claimed in claim 2;

B) the transverse axis coordinate that arranges of exercisable method as claimed in claim 9 and ordinate of orthogonal axes.

12. 1 kinds of methods to set up of placing label request in domain, comprising:

A) layer that exercisable method as claimed in claim 2 is arranged is selected;

B) label font of exercisable method setting as claimed in claim 2;

C) label height of exercisable method setting as claimed in claim 2;

D) placement direction of exercisable method setting as claimed in claim 2;

E) the transverse axis coordinate that arranges of exercisable method as claimed in claim 9 and ordinate of orthogonal axes.

13. 1 kinds of methods to set up of placing pin request in circuit symbol, comprising:

A) pin name is provided;

B) pin type is provided;

C) a symbol orientation is set;

D) character position is set;

E) a symbol level is set.

In circuit diagram, place line and label, pin, method to set up without linkage flag request, comprising for 14. 1 kinds:

A) network name is provided;

B) network type is provided;

C) bus parameter is set;

D) number parameter is set;

E) a line type is set;

F) paging that exercisable method as claimed in claim 2 is arranged is selected;

G) the link position list of exercisable method setting as claimed in claim 9;

H) the placement label request that arranges of the selectable method as claim 11;

I) the placement pin request that arranges of the selectable method as claim 11;

J) placement that arranges of the selectable method as claim 11 is without linkage flag request.

15. 1 kinds of methods to set up of placing wiring and asking in domain, comprising:

A) network name is provided;

B) network type is provided;

C) bus parameter is set;

D) number parameter is set;

E) type of wiring is set;

F) layer that exercisable method as claimed in claim 2 is arranged is selected;

G) the wire location list of exercisable method setting as claimed in claim 9;

H) the placement label request that arranges of the selectable method as claim 12;

I) wiring width that selectable method as claimed in claim 9 is arranged is arranged.

16. 1 kinds of methods to set up of placing pin request in domain, comprising:

A) network name is provided;

B) network type is provided;

C) pin name is set;

D) bus parameter is set;

E) number parameter is set;

F) layer that exercisable method as claimed in claim 2 is arranged is selected;

G) alignment that exercisable method as claimed in claim 2 is arranged is selected;

H) set direction of exercisable method setting as claimed in claim 2;

I) the transverse axis coordinate that arranges of exercisable method as claimed in claim 9 and ordinate of orthogonal axes;

J) pin length of selectable method setting as claimed in claim 9;

K) pin widths of selectable method setting as claimed in claim 9.

17. 1 kinds of methods to set up of placing perforation and asking in domain, comprising:

A) selectablely a network name is provided;

B) selectablely a network type is provided;

C) a perforation title is set;

D) bus parameter is set;

E) number parameter is set;

F) keyhole mode is set;

H) set direction of exercisable method setting as claimed in claim 2;

I) the transverse axis coordinate that arranges of exercisable method as claimed in claim 9 and ordinate of orthogonal axes.

In circuit symbol or circuit diagram or domain, set up network and place line, wiring, pin, perforation, label, method to set up without linkage flag request, comprising for 18. 1 kinds:

A) network name is set;

B) network type is set;

C) the symbol pin request that arranges of the exercisable method as claim 13;

D) circuit connection that arranges of the exercisable method as claim 14 and label, pin, placement request without linkage flag;

E) the domain wiring that arranges of the exercisable method as claim 15 and the placement request of label;

F) the placement request of domain pin that arranges of the exercisable method as claim 16;

G) the placement request that the domain that the exercisable method as claim 17 is arranged is bored a hole.

19. 1 kinds of data description method automatically realizing electronic system design, comprising:

A) data of description of the exercisable design module containing claim 1 method;

B) the design rule data of the technology of printed circuit or integrated circuit;

C) user-defined design parameter data;

D) the module exampleization data of components and parts request are placed in exercisable modular circuit containing claim 6 method or module domain;

E) set up network in exercisable module symbolic containing claim 18 method or modular circuit or module domain and place line, wiring, pin, perforation, label, the module network data list of asking without linkage flag etc.

20. 1 kinds of tool software automatically realizing electronic system design, based on the data of description of the such as method of claim 19, generate circuit symbol and (or) circuit diagram and (or) the domain of electronic system automatically and arrange its variable element.