CN109445365B - Screening test method of FPGA embedded multiplier - Google Patents
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Abstract
The invention relates to a performance test method of an FPGA embedded multiplier, which comprises the following steps: (1) designing an IP core function of the embedded multiplier; (2) designing a pseudo-random sequence test vector; (3) RTL level code emulation; (4) analyzing the circuit design by using the test result; (5) and copying the module and outputting the logic design. The screening test method of the FPGA embedded multiplier adopts a test method based on BIST, and overcomes the defects of high test cost and high test technical difficulty of ATE; meanwhile, the pseudo-random sequence is used as excitation input, so that the test time is reduced, and the test efficiency is improved. The method makes full use of the programmable characteristic of the FPGA chip and abundant programmable logic units and embedded Memory units (BRAMs) in the chip. The method has the advantages of simple implementation steps, strong transportability and certain engineering application value.
Description
Technical Field
The invention relates to a screening test method of an FPGA embedded multiplier, belonging to the technical field of integrated circuits.
Background
With the development of the technical fields of computers, information technology, integrated circuit design and the like, the importance of digital signal processing is increasingly expressed in various fields due to the advantages of high precision, high flexibility, easy large-scale integration, capability of carrying out multi-dimensional data processing and the like. The digital signal processing system is used as a carrier of digital signal processing, a core component of the digital signal processing system is a digital signal processing unit, the FPGA is used as a typical representative of a reconfigurable digital processing unit, and the digital signal processing system is distinguished from numerous digital processing units by the advantages of strong computing power, flexibility, low cost and the like, and is depended by more and more users.
The Field Programmable Gate Array (FPGA) generally integrates dozens or even hundreds of embedded multiplier modules, the embedded multiplier modules have various functions and complex internal structures, and are limited by test time and test cost, so that an FPGA manufacturer generally cannot perform comprehensive functional test on a common commercial FPGA chip. In the high-reliability application field, a user needs to perform supplementary screening test on purchased commercial chips so as to meet the requirement of the complete machine on the use reliability of components.
The embedded multiplier is an important IP hard core in the FPGA and is mainly used for digital signal processing. Compared with a lookup table, the method has the advantages of high speed, low power consumption, less resource occupation and the like. Research shows that the IP hard core of the embedded multiplier is adopted to realize multiplication operation, compared with the realization of the LUT table, the area is about one tenth of the LUT table, and the speed is 5 times of the LUT table. Therefore, the integration of the embedded multiplier has important significance for realizing digital signal processing by adopting the FPGA.
At present, an embedded multiplier module mainly performs a function Test through an ATE (Automatic Test Equipment) tester, and an ATE device diagnoses an internal fault of an FPGA by inputting a Test vector to an FPGA chip and analyzing a Test output result. Two major problems exist in the ATE test method:
(1) expensive costs are required to purchase or lease ATE equipment and to develop specific ATE test programs, which adds to the cost that a user is burdened with.
(2) With the increasing integration level of the FPGA, the functions of the chip are more and more complex, the number of the packaged I/O ports is limited, and the difficulty of comprehensively testing the internal resources of the FPGA by using ATE equipment is more and more increased.
Disclosure of Invention
The invention aims to solve the technical problems that: the defects of the technology are overcome, and the Built-in Self Test (BIST) -based FPGA embedded multiplier screening Test method is provided.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a screening test method of an FPGA embedded multiplier comprises the following steps:
(1) designing an IP core function of the embedded multiplier; adopting the working modes of sign number, input register, output pipeline register and 18 bx 18 b;
(2) designing a pseudo-random sequence test vector; the pseudo-random sequence is generated by a seed, a clock and a reset signal through a deterministic algorithm;
(3) RTL level code emulation; obtaining an expected correct output result through ModelSim simulation, and further generating an initialization ROM file required by the FPGA embedded memory module; the storage of correct output nodes is completed by instantiating the corresponding BRAM IP core module;
(4) analyzing the circuit design by using the test result; when the test is started, generating a corresponding address signal through a clock and a reset signal, and further reading the storage data of a corresponding address in the BRAM module; judging whether the function is correct or not by comparing the calculation result with the calculation result of the embedded multiplier, and further outputting the state;
(5) module copying and output logic design; each test module comprises 4 multiplication arithmetic units of 18b multiplied by 18b, 2 pseudorandom sequences of 18b, a memory, a test result comparator and a control signal consisting of a zero clearing signal and a sign bit; and carrying out XOR operation on the output result of each test module, when a certain test module is wrong and the output signal is changed from low to high, sending an alarm signal to remind a user.
The scheme is further improved in that: in the step (4), if the calculation result of the embedded multiplier in a certain period is wrong and the state signal changes from low to high, an alarm signal is sent out to remind a user.
The screening test method of the FPGA embedded multiplier adopts a test method based on BIST, and overcomes the defects of high test cost and high test technical difficulty of ATE; meanwhile, the pseudo-random sequence is used as excitation input, so that the test time is reduced, and the test efficiency is improved. The method makes full use of the programmable characteristic of the FPGA chip and abundant programmable logic units and embedded Memory units (BRAMs) in the chip. The method has the advantages of simple implementation steps, strong transportability and certain engineering application value.
Drawings
The invention will be further explained with reference to the drawings.
FIG. 1 is a flow chart of a screening test implementation according to a preferred embodiment of the present invention.
Fig. 2 is a schematic block diagram of pseudo-random sequence generation.
FIG. 3 is a functional block diagram of a test circuit.
Detailed Description
Examples
The performance test method of the FPGA embedded multiplier of the embodiment, as shown in fig. 1, includes the following steps:
(1) designing an IP core function of the embedded multiplier;
(2) designing a pseudo-random sequence test vector;
(3) RTL level code emulation;
(4) analyzing the circuit design by using the test result;
(5) and copying the module and outputting the logic design.
The ergodic test is a test method which inputs all possible test stimuli to a tested circuit and observes the output result of the tested circuit. If the circuit under test is a combinational logic circuit, assuming that there are n data input pins in total, there are 2n test vectors. Assuming that the unit time for completing each test and observation is t, the total time required for completing the test is 2n · t. For sequential circuits, the total test time is still longer. Thus, the traversal test is generally applicable to circuits with fewer inputs. For the embedded multiplier, the test method consumes a lot of test time and is expensive.
In view of the reconfigurable characteristic of the FPGA chip, a Built-in Self Test (BIST) method can be used to detect and diagnose the fault of the FPGA. Through programming, a part of logic resources of the FPGA are used as a Test Pattern Generation (TPG), the TPG can provide excitation input for a module Under Test (BUT), another part of logic resources are used as an Output Response Analyzer (ORA), and the ORA can analyze and compare Output results of the BUT to further judge whether the BUT has a fault. The present invention therefore introduces a BIST-based testing concept.
For a common FPGA chip, the embedded multiplier can realize multiplication operations of 9b multiplied by 9b, 18b multiplied by 18b and 36b multiplied by 36b bits. According to different data bit widths, one embedded multiplier module can process a plurality of multiplication operations in parallel. An embedded multiplier module can accomplish simultaneously: 8 multiplications of 9b × 9 b; or 4 multiplications of 18b x 18 b; or 1 multiplication of 36b by 36 b.
Operands for multiplication can be unsigned and signed numbers, signa and signb are used to indicate whether two operands are signed numbers, respectively, typically a logical 1 for signed numbers and a 0 for unsigned numbers. If any of the operands is a signed number, the result is also a signed number. These two signals affect the entire embedded multiplier module, i.e., all operands (a or B) in the embedded multiplier module have the same sign number characteristic.
The data input mode of the FPGA embedded multiplier can be configured into a registered mode and a non-registered mode, and the non-registered mode is included in the registered mode in terms of testing, so that only the registered mode needs to be tested and verified. The whole embedded multiplier is equivalent to a combinational logic block, and the change of A, B value is reflected in the output OUT, and the output result can be sent to a pipeline register or directly bypassed.
In summary, in order to improve the testing efficiency and the testing coverage, the operation mode of 18 bx 18b with signed number, input register, output pipeline register and output register can be adopted in the step (1).
As shown in fig. 2, the pseudo-random sequence is generated by a deterministic algorithm from a seed, a clock, and a reset signal. By using a pseudo-random sequence, all possible test vectors may not be tested one by one, which may reduce the time required for testing.
After the working mode of the embedded multiplier and the pseudo-random sequence are determined, an expected correct output result can be obtained through ModelSim simulation, and then an initialization ROM file required by the FPGA embedded memory module is generated. The storage of correct results can be completed by instantiating the corresponding BRAM IP core module.
When the test is started, the corresponding address signal is generated through the clock and the reset signal, and then the storage data of the corresponding address in the BRAM module is read. By comparing with the calculation result of the embedded multiplier, whether the function is correct or not can be judged, and then the state (correct/wrong) is output. Once the calculation result of the embedded multiplier in a certain period is wrong, the state signal is changed from low to high, and the state indicator lamp is lightened to remind a user.
Since one embedded multiplier module can complete 4 bx 18b multiplications at the same time, each test module includes 4 bx 18b multiplications, 2 pseudorandom sequences of 18b, a memory, a test result comparator, and a control signal composed of a clear signal and a sign bit, as shown in fig. 3. Generally speaking, each FPGA chip includes a plurality of embedded multiplier modules, the test modules need to be copied, the resource utilization rate of the embedded multipliers is guaranteed to reach 100%, and the output result of each test module is subjected to exclusive or operation, so that once a certain test module has an error, the output signal changes from low to high, and the status indicator lamp is turned on to remind a user.
The present invention is not limited to the above-described embodiments. All technical solutions formed by equivalent substitutions fall within the protection scope of the claims of the present invention.
Claims (2)
1. A screening test method of an FPGA embedded multiplier is characterized by comprising the following steps:
(1) designing an IP core function of the embedded multiplier; adopting the working modes of sign number, input register, output pipeline register and 18 bx 18 b;
(2) designing a pseudo-random sequence test vector; the pseudo-random sequence is generated by a seed, a clock and a reset signal through a deterministic algorithm;
(3) RTL level code emulation; obtaining an expected correct output result through ModelSim simulation, and further generating an initialization ROM file required by the FPGA embedded memory module; the storage of correct output results is completed by instantiating the corresponding BRAM IP core module;
(4) analyzing the circuit design by using the test result; when the test is started, generating a corresponding address signal through a clock and a reset signal, and further reading the storage data of a corresponding address in the BRAM module; judging whether the function is correct or not by comparing the calculation result with the calculation result of the embedded multiplier, and further outputting the state; (5) module copying and output logic design; each test module comprises 4 multiplication arithmetic units of 18b multiplied by 18b, 2 pseudorandom sequences of 18b, a memory, a test result comparator and a control signal consisting of a zero clearing signal and a sign bit; and carrying out XOR operation on the output result of each test module, when a certain test module is wrong and the output signal is changed from low to high, sending an alarm signal to remind a user.
2. The method for testing the performance of the FPGA embedded multiplier according to claim 1, characterized in that: in the step (4), if the calculation result of the embedded multiplier in a certain period is wrong and the state signal changes from low to high, an alarm signal is sent out to remind a user.
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