CN101515020B - Built-in self-test method of FPGA logical resource - Google Patents
Built-in self-test method of FPGA logical resource Download PDFInfo
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Abstract
The invention provides a built-in self-test method of FPGA logical resource. The internal logical module of FPGA is alternately divided into a left half part and a right half part according to row. In the test process, the logical module array of the right half part is firstly configured as a to-be-tested circuit, and the rest logical module arrays are configured as a test vector generating circuit and an output response analyzing circuit, and then the logical module array of the left half part is configured as the to-be-tested circuit, and the rest logical module arrays are configured as the test vector generating circuit and the output response analyzing circuit. The circuit structure is not changed in each process. The logical resource is covered by multiple configurations and the test result is output by a built-in scan register chain. All configurations in the invention are as follows: all logical modules configured as the response analyzing circuits are in cascade connection end to end according to one-dimensional array, so as to simplify the self-test result retrieval manner. Provided that the test coverage is 100%, the built-in self-test method reduces times of the configurations of FPGA logical resource, reduces test cost and increases test flexibility, so as to improve test efficiency.
Description
Technical field
The present invention relates to a kind of method of testing of fpga chip, particularly based on the build-in self-test method of scan register fpga logic resource.
Background technology
But the FPGA test utilizes its overprogram characteristic, covers all resources to be measured by repeatedly disposing.Its test is mainly contained outer test and two kinds of methods of built-in self-test, during outer the test, the FPGA device is configured to corresponding test circuit, uses external unit to apply test vector and TEA output result, this method takies a large amount of pins, causes test to depend on encapsulation; Compare with outer test, the build-in self-test method vector applies with response analysis and all finishes in inside, does not need special test equipment and a large amount of pin, has promptly reduced testing cost, has increased the test dirigibility again.
Configurable logic blocks is basic functions unit among the FPGA, and the full test of logical resource is in crucial status in the FPGA measuring technology.At present, abroad the test of fpga logic resource is studied, built-in self-test theory based on the storer retaking of a year or grade has been proposed, but these Design Theory complexity, test result retaking of a year or grade, diagnosis expend the extra test duration again, the test logic resource needs a lot of configurations fully, has increased the difficulty of test implementation.Domestic research in this field also is in the starting stage, be close to blank at main flow built-in self-test Study on Technology, in August, 2004 " Harbin Institute of Technology's journal ", the 36th volume the 8th device was delivered " based on the fpga logic unit test method of BIST ", introduced a kind of method of test site programmable gate array (FPGA) logical block based on built-in self-test (BIST) in the literary composition, the problem and the solution that occur in configuration structure, fault coverage and the test of test have been discussed.But only simply introduced the basic structure of fpga logic BIST in the literary composition, provided the general general procedure of BIST test structure, but this method has not been done further deep introduction.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of build-in self-test method of fpga logic resource is provided, the present invention has made up the built-in self-test structure based on scan chain architecture, simplify the self-test result and fetched mode, adopt method of testing of the present invention can reduce the configured number of fpga logic resource, thereby improve testing efficiency.
Technical solution of the present invention is: a kind of build-in self-test method of fpga logic resource comprises the following steps:
(a) with the logic module in the FPGA device by row alternately be divided into about two parts, logic module after dividing is configured and tests, each configuration of logic module is finished test by two test processs, wherein the collocation method of first test process is: the left column logic module is configured to test vector produces circuit, right half part logic module array configurations is a plurality of circuit under test, and the logic module array configurations between the adjacent circuit under test is the output response analysis circuit of scan chain architecture; The collocation method of second test process is: the right column logic module is configured to test vector produces circuit, left-half logic module array configurations is a plurality of circuit to be tested, and the logic module array configurations is the output response analysis circuit of scan chain architecture between the adjacent circuit under test;
(b) output port that test vector is produced circuit is connected with the input port of each circuit under test, each input port of the output response analysis circuit of scan chain architecture is connected with the output port of two adjacent circuit under test, thereby forms the built-in self-test structure;
(c) test according to the configuration result of first test process: produce circuit generation pseudorandom exhaustive testing vector by test vector and apply resolution chart to circuit under test, after test vector applies and finishes, the scan chain work that startup is made of the output response analysis circuit of scan chain architecture, under the control of test clock, the output response analysis circuit of scan chain architecture is exported the built-in self-test test result of first test process; Configuration result according to second test process repeats first test process then, and the output response analysis circuit of scan chain architecture is exported the built-in self-test test result of second test process;
(d) keep the built-in self-test structure of step (b) constant, repeated execution of steps (c) all logic modules in test covers FPGA.
Principle of work of the present invention is: FPGA internal logic module alternately is divided into left and right sides two halves by row, be circuit under test at first during test with right half part logical block array configurations, all the other logical block array configurations are that test vector produces circuit and output response analysis circuit, be circuit under test with left-half logical block array configurations then, all the other logical block array configurations are that test vector produces circuit and output response analysis circuit, each test process needs the holding circuit structure constant, cover all logical resources by repeatedly disposing, test result is by the scan register chain output of internal build.
The present invention's advantage compared with prior art is: the method for testing of existing configurable logic blocks is outer test and based on the build-in self-test method of config memory retaking of a year or grade, it is tested at home and abroad needs expensive special test equipment and takies a large amount of IO pins, has limited type of device and has been not suitable for promoting the use of; Secondly, existing build-in self-test method based on the config memory retaking of a year or grade need grab register value in the config memory during test, and then by the config memory read-back approach is taken out test result, so not only design realizes difficulty, and has increased the extra test duration.Among the present invention, a kind of build-in self-test method that adopts based on scan chain architecture is proposed, make up the scan register chain circuit at device inside, to be latched in the scan value output in the scan chain register during test, with compare based on config memory retaking of a year or grade mode, simplify the built-in self-test test result and fetched mode, and solved the test result retaking of a year or grade, the problem that diagnosis expends extra time, and then improved testing efficiency, by utilizing build-in self-test method of the present invention to the Spartan II/Virtex of Xilinx company Series FPGA, simplified the configuration structure of circuit under test, the observation port of each configuration is significantly reduced, testing time is compressed to 24 times from 42 times fully, and reached 100% test coverage, thereby reduced testing cost, increased the test dirigibility, effectively improved testing efficiency.
Description of drawings
Fig. 1 is the structural representation of FPGA;
Fig. 2 is the structural representation of FPGA configurable logic blocks;
Fig. 3 is the built-in self-test structure that the present invention disposed, and Fig. 3 (a) is the structure of first test process, and Fig. 3 (b) is the structure of second test process;
Fig. 4 is the output response analysis circuit of the scan chain architecture of the present invention's configuration;
Fig. 5 is the circuit under test structural drawing of embodiment of the invention configuration;
Fig. 6 is the output response analysis circuit structure diagram of the scan chain architecture of embodiment of the invention configuration;
Fig. 7 is the 1st configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Fig. 8 is the 2nd configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Fig. 9 is the 3rd configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 10 is logic module the 4th configuration circuit under test structural drawing in the embodiment of the invention;
Figure 11 is logic module the 5th configuration circuit under test structural drawing in the embodiment of the invention;
Figure 12 is the 6th configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 13 is the 7th configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 14 is the 8th configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 15 is the 9th configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 16 is the 10th configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 17 is the 11st configuration of a logic module circuit under test structural drawing in the embodiment of the invention;
Figure 18 is the 12nd configuration of a logic module circuit under test structural drawing in the embodiment of the invention.
Embodiment
The FPGA basic circuit structure as shown in Figure 1, mainly form by TITLE array 001 and input/output module 005, programmed logical module 002 is the logical block in one of them TITLE array 001, it realizes and the interconnection between the programmed logical module on every side that by IMUX003 and switch matrix 004 user can be by 002 configuration realizes various functions flexibly to programmed logical module.Configurable logic blocks 002 is the logical block in the TITLE array 001, configurable logic blocks 002 mainly is made of two identical SLICE unit as shown in Figure 2, it realizes and the interconnection between the programmed logical module on every side that by IMUX003 and switch matrix 004 user can be by 002 configuration realizes various functions flexibly to configurable logic blocks.
Built-in self-test structure of the present invention as shown in Figure 3, The built-in self-test process is specific as follows:
(a) configurable logic blocks is divided into left and right sides two parts by row, according to the first row circuit under test position, all odd number array logic module are defined as left-half, all even arrays logic modules are defined as right half part, logic module after dividing is configured, each configuration of logical resource is finished whole tests by two test processs, being configured to of first test process: the left column logical block is configured to test vector produces circuit 1, this circuit adopts the linear feedback shift register structure, produce pseudorandom exhaustive testing vector, wherein linear feedback shift register is made up of d type flip flop and linear XOR gate, little because of taking hardware area, in the built-in self-test circuit, produce pseudorandom exhaustive testing vector and be used to apply resolution chart, right half part logical block array configurations is a circuit under test 2, logical block is configured to export response analysis circuit 3 between the adjacent circuit under test, output response analysis circuit 3 adopts integrated ORA (the output corresponding analysis device) structure based on scan register, is used for the output data of more adjacent circuit under test 2; Being configured to of second test process: the right column logical block is configured to test vector produces circuit 1, left-half logical block array configurations is a circuit 2 to be tested, and logical block is configured to export response analysis circuit 3 between the adjacent circuit under test;
(b) output port that test vector is produced circuit 1 is connected with the input port of each circuit under test 2, thereby the input port of the output response analysis circuit 3 of scan chain architecture is connected with the output port of adjacent two circuit under test 2 and forms the built-in self-test structure;
(c) test according to the configuration result of first test process: produce circuit 1 generation pseudorandom exhaustive testing vector by test vector and apply resolution chart to each circuit under test 2, after test vector applies and finishes, scan chain 4 work that startup is made of output response analysis circuit 3, the output response analysis circuit 3 of scan chain architecture is exported the built-in self-test test result 5 of first test process under the control of test clock; Configuration result according to second test process repeats first test process then, the built-in self-test test result 5 of output response analysis circuit 3 outputs second test process of scan chain architecture; Half logic module of each test procedure test, first, second two test processs are finished once whole tests of configuration;
(d) keep the built-in self-test structure of step (b) constant, repeated execution of steps (c) all logic modules in test covers FPGA.
Its inner structure of output response analysis circuit of scan chain architecture as shown in Figure 4, form by N level ORA structure, N level ORA structure is according to the one-dimensional array composition scan chain architecture that cascades up from beginning to end, every grade of ORA structure includes XOR 41, or logic 42, Port Multiplier 43, register 46, the XOR 41 of each grade ORA structure connects the output of adjacent two circuit under test 2, after XOR 41 is judged, be transferred to again or logic 42, and then process Port Multiplier 43 is connected to register 46, and judged result is latched in the register 46 via feedback path 44, at last by 45 outputs of register output port, wherein first order ORA Port Multiplier input port 47 connects high level signal, first order ORA register 46 output ports 45 are connected to Port Multiplier 43 input ports 47 of second level ORA, the output port 45 of register 46 connects the input port 47 of Port Multiplier 43 in the third level ORA structure in the ORA structure of the second level, and the like, the output port 45 of register 46 is connected to the input port 47 of Port Multiplier 43 in the N level ORA structure in the N-1 level ORA structure, during test in every grade of ORA structure the scan control port 48 of Port Multiplier 43 connect high level, after test vector applies and finishes, the scan control port 48 of Port Multiplier 43 connects low level in every grade of ORA structure, under the control of test clock signals clock, the value that latchs in all ORA registers output port 45 outputs of register 46 from N level ORA structure successively, wherein N is the number of ORA structure, is integer.
Be that example is described in detail test of the present invention and collocation method with Xilinx company Spartan II/Virtex Series FPGA below.
Logic module in the Spartan II/Virtex Series FPGA is configured to circuit under test, as shown in Figure 5, because each logic module comprises two SLICE unit, mainly be made up of function generator, arithmetic logic, Port Multiplier and sequential logic the circuit under test that each SLICE configuration of cells becomes, its circuit structure specifically describes as follows: function generator G101 output is connected respectively to Port Multiplier CYSELG120, XOR XORG, Port Multiplier F5MUX129 and Port Multiplier GYMUX130; Function generator F102 output is connected respectively to Port Multiplier CYSELF121, XOR XORF, Port Multiplier F5MUX129 and Port Multiplier FXMUX119; Port Multiplier BYMUX109 output is connected to DGEN114, INITY106, INITX107 and Port Multiplier F6MUX130; Port Multiplier BXMUX110 output is connected respectively to DGEN114, WSGEN115, Port Multiplier CYINIT122, Port Multiplier DXMUX126 and Port Multiplier F5MUX129; G2 and G1 can be via being connected to Port Multiplier CY0G116 with door GAND; F2 and F1 can be via being connected to Port Multiplier CY0F117 with door FAND; Port Multiplier CEMUX111 output is connected respectively to the Enable Pin of register FFY104 and register FFX105; Clock signal can be connected respectively to WSGEN115, register FFY104 and register FFX105 via Port Multiplier CKINV112; Port Multiplier SRMUX113 output is connected respectively to INITY106 and INITX107; Port Multiplier CYSELG120 output is connected to the Enable Pin of carry logic CYMUXG127; Port Multiplier CYSELF121 output is connected to the Enable Pin of carry logic CYMUXF128; Carry input CIN is connected to Port Multiplier CYINTI122; Port Multiplier CYINIT122 output is connected respectively to arithmetic logic CYMUXF128 and XOR XORF again, and arithmetic logic CYMUXF128 is connected to arithmetic logic CYMUXG127 or is directly connected to output port XB; Port Multiplier CY0G116 output is directly connected to output port COUT or is connected to output port YB via Port Multiplier YBMUX124 via arithmetic logic CYMUXG127; XOR XORG output is connected to Port Multiplier GYMUX118; XOR XORF is connected to Port Multiplier FXMUX119; Port Multiplier F5MUX129 output is connected to Port Multiplier FXMUX119 or is directly connected to output port F5, Port Multiplier F6MUX output is connected to Port Multiplier GYMUX, and Port Multiplier GYMUX118 is connected to register FFY104 data input pin or is directly connected to output port Y via Port Multiplier DYMUX125; Port Multiplier FXMUX119 is connected to register FFX105 data input pin or is directly connected to output port X via Port Multiplier DXMUX126; Register FFY104 output is connected to output port YQ; Register FFX105 output is connected to output port XQ; Config option RAMCONFIG100 can work 16 * 1,16 * 2,32 * 1,16 * 1DP, 1SHIFT and 2SHIFT isotype, and reset options SYNC_ATTR108 can be provided with synchronous SYNC and asynchronous ASYNC dual mode.
Logic module in the Spartan II/Virtex Series FPGA is configured to the output response analysis circuit structure of scan chain architecture, because the circuit under test of each the logic module configuration in the Spartan II/Virtex Series FPGA comprises the circuit under test of two identical SLICE configurations, the circuit under test of each SLICE configuration of cells comprises two output signals, and an output response analysis circuit connects the circuit under test that two adjacent logic modules dispose, so each output response analysis circuit connects eight outputs of the circuit under test of 4 SLICE configuration of cells, therefore need adjust circuit shown in Figure 4 according to the principle of work of output response analysis circuit, concrete structure as shown in Figure 6, form by N level ORA structure, N level ORA structure is according to the one-dimensional array composition scan chain architecture that cascades up from beginning to end, each ORA structure includes 4 XOR 61, two or logic 62, one or logic 63, Port Multiplier 65, register 67, eight output ports of adjacent two circuit under test are connected to i.e. 4 XOR 61 of output response analysis circuit input end mouth, judge through XOR 61, again through two or logic 62 and or logic 63 judge, and then process Port Multiplier 65 is connected to register 67, and judged result is latched in the register 67 via feedback path 64, at last by 66 outputs of register port, the input port 68 of Port Multiplier 65 connects high level signal in the first order ORA structure, the output port 66 of register 67 is connected to the input port 68 of Port Multiplier 65 in the ORA structure of the second level in the first order ORA structure, the output port 66 of register 67 is connected to the input port 68 of Port Multiplier 65 in the next stage ORA structure equally in the ORA structure of the second level, test result Pass/Fail is by output port 66 outputs of register 67 in the afterbody ORA structure, during test in every grade of ORA structure the scan control port 69 of Port Multiplier 65 connect high level, after test vector applies and finishes, the scan control port 69 input low level signals of Port Multiplier 65 in the ORA structure, the work of gated sweep chain of registers, under the control of test clock signals, the value that latchs in all ORA registers output port 66 outputs of register 65 from afterbody ORA structure successively.
According to above-mentioned build-in self-test method, test common 12 configurations totally 24 tests that need to divide fully to the logic module of Virtex/Spartan II Series FPGA, two test processs of each configuration are identical.A test process to wherein each configuration is described in detail below:
Dispose and test as shown in Figure 7 for the 1st time: configurable logic blocks shown in Figure 5 is configured, each is configured to pattern ram with function generator G101 and function generator F102, config option 100 is operated in the 2SHIFTS pattern, function generator G101 is connected to port Y output via Port Multiplier GYMUX118, and function generator F102 is connected to port x output via Port Multiplier FXMUX119; The C3 end of gating Port Multiplier BYMUX109 and the C3 end of Port Multiplier BXMUX110 are connected to DGEN114, and the C2 end of gating Port Multiplier CLKINV112 and the C3 end of Port Multiplier SRMUX113 are connected to WSGEN115.All logic module input end G1, G2, G3, G4, F1, F2, F3, F4 are connect high level, left column or right column logic module are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C3 end of the C3 of Port Multiplier BYMUX109 end, Port Multiplier BXMUX110, the C3 end of Port Multiplier SRMUX113, the C2 end of Port Multiplier CLKINV112 is connected to global clock.8 ports of 4 SLICE of adjacent two logic modules are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and register 67 output ports 66 are connected to the scan data input terminal mouth 68 of next stage ORA, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, to the public input end 69 input low level signals of all ORA structures, start the built-in self-test circuit working, through N (N represents ORA structure number) Clock cycle, test result is by output port 66 outputs of afterbody ORA register 67.
Dispose and test as shown in Figure 8 for the 2nd time: function generator G101 and function generator F102 are configured to equate logic, their output is connected to Port Multiplier F5MUX129, F5MUX1297 output terminal and F5IN are connected to Port Multiplier F6MUX130, and Port Multiplier F6MUX130 output terminal is connected to YB via Port Multiplier GYMUX124; Port Multiplier F5MUX129 output is connected to F5, and the C3 end of gating Port Multiplier BYMUX109 also is connected to Port Multiplier F6MUX130 control end, and the C3 end of gating Port Multiplier BXMUX110 also is connected to Port Multiplier F5MUX129 control end.Output port F5 is connected to adjacent S LICE input port F5IN; Left column or right column logical block are configured to linear feedback shift register LFSR, apply the exhaustive testing vector to the C3 end of G1 end, F1 end, F5IN end, Port Multiplier BYMUX109 and the C3 end of Port Multiplier BXMUX110.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA; After test vector applies and finishes, to the public input end 69 input low level signals of all ORA, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of register 67 in the afterbody ORA structure.
Dispose and test as shown in Figure 9 for the 3rd time: function generator G101 and function generator F102 are configured to equate logic, wherein function generator G101 inputs to Port Multiplier GYMUX118 after via XOR and is connected to register 104 by Port Multiplier DYMUX125 again, and function generator F102 inputs to Port Multiplier GXMUX119 after via XOR and is connected to register 105 by Port Multiplier DXMUX126 again; Register 104 and register 105 are configured to the FF pattern, and INITY106 and INITX107 are configured to the HIGH pattern, and SYNC_ATTR108 is configured to SYNC; The C2 end of the C1 end of gating Port Multiplier BYMUX109, the C1 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C4 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107; CIN is inserted Port Multiplier CYINIT122 and exports the COUT end to via arithmetic logic 128 and arithmetic logic 127, and the C1 of gating Port Multiplier CYSELG120 and Port Multiplier CYSELF121 also is connected respectively to arithmetic logic 127 and arithmetic logic 128.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C1 end of G1 end, F1 end, Port Multiplier BYMUX109, the C1 end of Port Multiplier CEMUX111, the C2 end of Port Multiplier CLKINV112 and the C4 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA connects high level, and register output port 66 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of register 67 in the afterbody ORA structure.
The 4th disposes and tests as shown in figure 10: function generator G101 and function generator F102 are configured to equate logic, their output terminal is connected to Port Multiplier F5MUX129 and is connected to register 105 via Port Multiplier GXMUX119 and Port Multiplier DXMUX126 again, wherein function generator G101 output terminal is connected to register 104 via Port Multiplier GYMUX118 and Port Multiplier DYMUX125 again, and gating Port Multiplier BXMUX110 end also is connected to the F5MUX129 control end; Register 104 and register 105 are configured to the FF pattern, and INITY106 and INITX107 are configured to the LOW pattern, and SYNC_ATTR108 is configured to SYNC; The C2 end of the C2 end of gating Port Multiplier BYMUX109, the C4 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C2 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C2 end of G1 end, F1 end, Port Multiplier BYMUX109, the C3 end of Port Multiplier BXMUX110, the C4 end of Port Multiplier CEMUX111, the C2 end of Port Multiplier CLKINV112 and the C2 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA connects high level, and the output port 66 of register is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of register 67 in the afterbody ORA structure.
The 5th disposes and tests as shown in figure 11: function generator G101 and function generator F102 are configured to XOR, wherein function generator G101 is connected to register 104 by Port Multiplier DYMUX125 again via Port Multiplier GYMUX118, and function generator F102 is connected to register 105 by Port Multiplier DXMUX126 again via Port Multiplier GXMUX119; Register 104 and register 105 are configured to the FF pattern, and INITY106 and INITX107 are configured to the HIGH pattern, and SYNC_ATTR108 is configured to ASYNC; The C2 end of the C1 end of gating Port Multiplier BYMUX109, the C4 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C1 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C1 end of G1, G2, G3, G4, F1, F2, F3, F4 end, Port Multiplier BYMUX109, the C1 end of Port Multiplier CEMUX111, the C2 end of Port Multiplier CLKINV112 and the C4 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA connects high level, and register output port 66 is connected to the scan data input terminal mouth 68 of next stage ORA, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, to the public input end 69 input low level signals of all ORA, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of register 67 in the afterbody ORA structure.
Dispose and test as shown in figure 12 for the 6th time: function generator G101 and function generator F102 are configured to together or logic, wherein function generator G101 is connected to register 104 by Port Multiplier DYMUX125 again via Port Multiplier GYMUX118, and function generator F102 is connected to register 105 by Port Multiplier DXMUX126 again via Port Multiplier GXMUX119; Register 104 and register 105 are configured to the FF pattern, and INITY106 and INITX107 are configured to the LOW pattern, and SYNC_ATTR108 is configured to ASYNC; The C2 end of the C1 end of gating Port Multiplier BYMUX109, the C3 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C1 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C1 end of G1, G2, G3, G4, F1, F2, F3, F4 end, Port Multiplier BYMUX109, the C3 end of Port Multiplier CEMUX111, the C2 end of Port Multiplier CLKINV112 and the C1 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA connects high level, and register output port 66 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, to the public input end 69 input low level signals of all ORA, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of register 67 in the afterbody ORA structure.
Dispose and test as shown in figure 13 for the 7th time: function generator G101 and function generator F102 are configured to together or logic, wherein function generator G101 is connected to register 104 by Port Multiplier DYMUX125 again via Port Multiplier GYMUX118, and function generator F102 is connected to register 105 by Port Multiplier DXMUX126 again via Port Multiplier GXMUX119; Register 104 and register 105 are configured to the LATCH pattern, and INITY106 and INITX107 are configured to the LOW pattern, and SYNC_ATTR108 is configured to ASYNC; The C1 end of the C3 end of gating Port Multiplier BYMUX109, the C2 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C1 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C3 end of G1, G2, G3, G4, F1, F2, F3, F4 end, Port Multiplier BYMUX109, the C2 end of Port Multiplier CEMUX111, the C1 end of Port Multiplier CLKINV112 and the C1 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Dispose and test as shown in figure 14 for the 8th time: register 104 and register 105 are configured to the LATCH pattern, and INITY106 and INITX107 are configured to the HIGH pattern, and SYNC_ATTR108 is configured to ASYNC; The C1 end of the C4 end of gating Port Multiplier BYMUX109, the C2 end of Port Multiplier CEMUX111, Port Multiplier CLKINV112 and the C3 end of Port Multiplier SRMUX113 also are connected to INITY106 and INITX107.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C2 end of the C4 of Port Multiplier BYMUX109 end, Port Multiplier CEMUX111, the C1 end of Port Multiplier CLKINV112 and the C3 end of Port Multiplier SRMUX113.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Dispose and test as shown in figure 15 for the 9th time: function generator G101 and function generator F102 are configured to equate logic that their output terminals are connected to arithmetic logic 127 and arithmetic logic 128 via Port Multiplier CYSELG120 and Port Multiplier CYSELF121 respectively; With port G1 and G2 and operation after be connected to arithmetic logic 127 by Port Multiplier CY0G116, with port F1 and F2 and operation after be connected to arithmetic logic 128 by Port Multiplier CY0F117; The C4 end of gating Port Multiplier BXMUX110 is connected to arithmetic logic 128 via Port Multiplier CYINIT, and arithmetic logic 128 output terminals are connected to XB, and arithmetic logic 127 output terminals are connected to YB via Port Multiplier YBMUX124.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C4 of G1, G2, F1, F2 end and Port Multiplier BXMUX110 end.8 ports of 4 S LICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Dispose and test as shown in figure 16 for the 10th time: function generator G101 and function generator F102 are configured to equate logic that their output terminals are connected to arithmetic logic 127 and arithmetic logic 128 via Port Multiplier CYSELG120 and Port Multiplier CYSELF121 respectively; Port G1 is connected to arithmetic logic 127 via Port Multiplier CY0G116, port F1 is connected to arithmetic logic 128 via Port Multiplier CY0F117; The C3 end of gating Port Multiplier BXMUX110 is connected to arithmetic logic 128 via Port Multiplier CYINIT, and arithmetic logic 128 output terminals are connected to XB, and arithmetic logic 127 output terminals are connected to YB via Port Multiplier YBMUX124.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to G1, F1 end and Port Multiplier BXMUX110C3 end.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Dispose and test as shown in figure 17 for the 11st time: function generator G101 and function generator F102 are configured to equate logic that their output terminals are connected to arithmetic logic 127 and arithmetic logic 128 via Port Multiplier CYSELG120 and Port Multiplier CYSELF121 respectively; The C2 of Port Multiplier CY0G116 end is connected to arithmetic logic 127, the C2 end of Port Multiplier CY0F117 is connected to arithmetic logic 128; The C2 end of gating Port Multiplier BXMUX110 is connected to arithmetic logic 128 via Port Multiplier CYINIT, and arithmetic logic 128 output terminals are connected to XB, and arithmetic logic 127 output terminals are connected to YB via Port Multiplier YBMUX124.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C2 of G1, F1 end and Port Multiplier BXMUX110 end.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Dispose and test as shown in figure 18 for the 12nd time: function generator G101 and function generator F102 are configured to equate logic that their output terminals are connected to arithmetic logic 127 and arithmetic logic 128 via Port Multiplier CYSELG120 and Port Multiplier CYSELF121 respectively; The C1 of Port Multiplier CY0G116 end is connected to arithmetic logic 127, the C1 end of Port Multiplier CY0F117 is connected to arithmetic logic 128; The C1 end of gating Port Multiplier BXMUX110 is connected to arithmetic logic 128 via Port Multiplier CYINIT, and arithmetic logic 128 output terminals are connected to XB, and arithmetic logic 127 output terminals are connected to YB via Port Multiplier YBMUX124.Left column or right column logical block are configured to linear feedback shift register LFSR apply the exhaustive testing vector to the C1 of G1, F1 end and Port Multiplier BXMUX110 end.8 ports of 4 SLICE of adjacent two logical blocks are connected to XOR 61; The scan data input terminal 68 of first order ORA structure connects high level, and the output port 66 of register 67 is connected to the scan data input terminal mouth 68 of next stage ORA structure, and the like all registers are coupled together.During test, at first, comparative result is latching to register 67 to the public input end 69 input high level signals of all ORA structures; After test vector applies and finishes, public input end 69 input low level signals to all ORA structures, start the BIST circuit working, through N (N represents the ORA number) Clock cycle, test result is by output port 66 outputs of afterbody ORA structure register 67.
Logical resource build-in self-test method of the present invention is equally applicable to the built-in self-test of other model fpga logic resources, the circuit under test difference of logic module configuration just, thus can carry out different layoutprocedures and test covers all logical resources fully according to the circuit under test structure that the fpga logic unit will dispose.The present invention not detailed description is a technology as well known to those skilled in the art.
Claims (3)
1. the build-in self-test method of a fpga logic resource is characterized in that comprising the following steps:
(a) with the logic module in the FPGA device by row alternately be divided into about two parts, logic module after dividing is configured and tests, each configuration of logic module is finished test by two test processs, wherein the collocation method of first test process is: the left column logic module is configured to test vector produces circuit (1), right half part logic module array configurations is a plurality of circuit under test (2), and the logic module array configurations between the adjacent circuit under test is the output response analysis circuit (3) of scan chain architecture; The collocation method of second test process is: the right column logic module is configured to test vector produces circuit (1), left-half logic module array configurations is a plurality of circuit to be tested (2), and the logic module array configurations is the output response analysis circuit (3) of scan chain architecture between the adjacent circuit under test;
(b) output port that test vector is produced circuit (1) is connected with the input port of each circuit under test (2), each input port of the output response analysis circuit (3) of scan chain architecture is connected with the output port of adjacent two circuit under test (2), thereby forms the built-in self-test structure;
(c) test according to the configuration result of first test process: produce circuit (1) generation pseudorandom exhaustive testing vector by test vector and apply resolution chart to circuit under test (2), after test vector applies and finishes, startup is by scan chain (4) work of output response analysis circuit (3) formation of scan chain architecture, under the control of test clock, the built-in self-test test result (5) of the output response analysis circuit (3) of scan chain architecture output first test process; Configuration result according to second test process repeats first test process then, the built-in self-test test result (5) of output response analysis circuit (3) output second test process of scan chain architecture;
(d) keep the built-in self-test structure of step (b) constant, repeated execution of steps (c) all logic modules in test covers FPGA.
2. the build-in self-test method of a kind of fpga logic resource according to claim 1 is characterized in that: described test vector produces circuit (1) and adopts the linear feedback shift register structure to produce pseudorandom exhaustive testing vector.
3. the build-in self-test method of a kind of fpga logic resource according to claim 1, it is characterized in that: the output response analysis circuit (3) of described scan chain architecture is made up of N level ORA structure, each grade ORA structure includes XOR (41), or logic (42), Port Multiplier (43) and register (46), the XOR (41) of each grade ORA structure connects the output of adjacent two circuit under test (2), after judging, XOR connects or logic (42), the data input pin that connects register (46) then through Port Multiplier (43), via feedback path (44) the logic determines result is latched in the register (46), wherein Port Multiplier input port (47) connects high level in the first order ORA structure, the output port (45) of register (46) connects the input port (47) of Port Multiplier (43) in the ORA structure of the second level, the output port (45) of register (46) connects the input port (47) of Port Multiplier (43) in the third level ORA structure in the ORA structure of the second level, and the like, in the N-1 level ORA structure output port (45) of register (46) be connected to the input port (47) of Port Multiplier (43) in the N level ORA structure thus form scan chain, during test in every grade of ORA structure the scan control port (48) of Port Multiplier (43) connect high level, after test vector applies and finishes, the scan control port (48) of Port Multiplier (43) connects low level in every grade of ORA structure, under the control of test clock signals clock, the value that latchs in all the ORA registers output port (45) of register (46) output from N level ORA structure successively, wherein N is an integer.
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| CN102736023A (en) * | 2011-08-31 | 2012-10-17 | 深圳市国微电子股份有限公司 | FPGA (field-programmable gate array) interconnection line test method |
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