CN109428589B

CN109428589B - 3D FPGA with non-uniform distribution channel structure

Info

Publication number: CN109428589B
Application number: CN201710751526.7A
Authority: CN
Inventors: 高丽江
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2017-08-28
Filing date: 2017-08-28
Publication date: 2023-09-22
Anticipated expiration: 2037-08-28
Also published as: CN109428589A

Abstract

The present disclosure provides a channel structure non-uniformly distributed 3D FPGA, comprising: and the 3D switch box units comprise one or more 3D switch boxes, and the 3D switch boxes in the 3D switch box units are unevenly distributed on the XY plane of the 3D FPGA. The 3D FPGA with the unevenly distributed channel structures has flexible channel structure arrangement, and the uneven distribution of the channel structures is realized by adjusting the density, the type and the distribution of the through silicon vias, so that the power consumption and the temperature of different areas are adjusted; through adopting the heat dissipation through silicon via hole, play the effect of effective equilibrium temperature distribution, strengthened 3 DFPGA's stability and reliability.

Description

3D FPGA with non-uniform distribution channel structure

Technical Field

The disclosure relates to the technical field of microelectronics, in particular to a 3D FPGA with a non-uniformly distributed channel structure.

Background

As process nodes develop forward, the proportion of interconnect delay in the total delay of the integrated circuit is increased, the power consumption problem is increased in proportion to the increase of capacitance on a long line, the characteristic size of the traditional two-dimensional integrated circuit approaches a physical limit, and moore's law is difficult to maintain and goes beyond moore's law. 3D integrated circuits have attracted tremendous attention as an important research direction beyond the moore's law era. The 3D integrated circuit transfers the long line of the planar integrated circuit into the short line in the local vertical direction, so that the three-dimensional integrated circuit has the characteristics of reduced delay and reduced power consumption. Although 3D integrated circuits have many advantages, they are also subject to the limitations of difficult heat dissipation, complex clock network design, large through-silicon via size and large footprint.

The FPGA Chinese name is a field programmable gate array, and is widely applied to the fields of communication base stations, aerospace, automobile electronics, intelligent control and the like due to high parallelism and programmability. The FPGA comprises modules such as programmable logic resources, programmable interconnection resources, programmable IO, embedded IP and the like on a hardware structure. The advantages and disadvantages of the programmable interconnection resources are critical to the performance of the FPGA. The programmable interconnection is mainly composed of a channel line with a certain length and a switch box for realizing the jump between channels on hardware, and the two together with a connection box for realizing the connection of the channels and logic resources form a main channel structure of the FPGA.

Fig. 1 shows a 3D FPGA stacked from four layers of FPGA slices.

The existing 3D FPGA, its switch box (SWB) distribution mainly includes the following two cases:

(1) The 3D FPGA includes only one type of switch box (SWB), as shown in fig. 2, a plurality of 3D switch boxes are uniformly distributed on each row/column channel of the FPGA plane. Specifically, the 3D switches are uniformly distributed on each physical plane of the 3D FPGA. Each 3D switch box has the same topological structure and the same switch number in each direction, namely the 3D grid or the torus.

(2) The simultaneous use of 2d,3d switchboxes in the network, the position distribution of the switchboxes in each plane is determined by the following conditions:

a. a first 3D switch box is placed at (X, Y, Z) of each layer.

Specifically, 4 2D switch boxes adjacent thereto are placed at (X+r+1, Y, Z), (X-r-1, Y, Z), (X, Y+r+1, Z) and (X, Y-r-1, Z), respectively. Where the parameter r represents the repetition period of the 2D switchbox in each plane. Thus, in each direction in the plane, one 2D switchbox is inserted per r 3D switchboxes, which is the solution shown in fig. 3.

b. A first 2D switch box is placed at (X, Y, Z) of each layer.

Specifically, 4 3D switch boxes adjacent thereto are placed at (X+r+1, Y, Z), (X-r-1, Y, Z), (X, Y+r+1, Z) and (X, Y-r-1, Z), respectively. Where the parameter r represents the repetition period of the 3D switchbox in each plane. Thus, in each direction in the plane, one 3D switchbox is inserted per r 2D switchboxes, which is the solution shown in fig. 4.

The two conditions are 3D FPGA with uniformly distributed switch boxes.

Fig. 5 is a temperature distribution diagram of layers of a conventional FPGA structure comprising four layers of CMOS circuits, each layer having a size of 1/4 of the total size of the FPGA, depending on through-silicon vias to conduct heat. And the heating value and the total heating value of each layer of FPGA are obtained by counting the power consumption value of each module, the layers are fixedly connected by means of through silicon vias, and the external environment temperature is 25 degrees. As can be seen from a combination of fig. 5 and table 1, the temperature distribution of each layer varies depending on the location, the temperature of the uppermost layer is highest, the temperature of the lowermost layer is lowest, and the temperature of each layer gradually increases from the center to the periphery. Wherein the FPGA structural material settings are shown in table 3. Analyzing the reasons for this, it is not difficult to find that each layer of chips exhibits different temperature characteristics depending on the distance from the heat sink. For each layer, the ambient temperature is higher than the center temperature because of the large power consumption of the circumferentially distributed IOs.

TABLE 1 statistical results of thermal distribution

	Minimum temperature	Maximum temperature	Average temperature
				Slice 1	44.11℃	48.27℃	46.56℃
Slice 2	46.14℃	49.29℃	47.87℃
				Slice 3	47.34℃	49.98℃	48.73℃
Slice 4	47.92℃	50.32℃	49.17℃

Fig. 6 is a temperature distribution diagram of each layer of a 3D integrated circuit with uniformly distributed power consumption at each position, wherein the FPGA structure comprises four layers of CMOS circuits and relies on through silicon vias to conduct heat, and as can be seen in combination with fig. 6 and table 2, the ambient temperature is lower than the central temperature, unlike the case of fig. 5. The FPGA structural material settings are also shown in table 3. From the analysis it can be concluded that: the central position of the 3D FPGA with evenly distributed power consumption at each position can not well dissipate heat, so that the temperature is higher than four sides.

TABLE 2 statistical results of thermal distribution

	Minimum temperature	Maximum temperature	Average temperature
				Slice 4	80.02	87.57	83.52
Slice 3	78.47	86.16	82.22
				Slice 2	75.72	83.61	79.66
Slice 1	72.76	79.76	75.26
				Exopy	30.97	71.63	50.11
PCB	25	25	25

Table 3FPGA structural material setup

To sum up, the existing FPGA mainly has the following heat dissipation problems: (1) The 3D FPGA switch box is single in distribution, and the temperature of each layer is unevenly distributed. (2) The internal temperature of each layer is unevenly distributed, and the heat dissipation effect is not ideal; the heat dissipation problem has certain influence on the stability, reliability and service life of the 3D FPGA.

Disclosure of Invention

First, the technical problem to be solved

In view of the above technical problems, the present disclosure provides a three-dimensional (3D) FPGA with unevenly distributed channel structures, which is flexible to set, and the channel structures are unevenly distributed by adjusting the density, type and distribution of through-silicon vias, so as to reduce power consumption in hotter areas; through adopting the heat dissipation through silicon via hole, play effective equilibrium temperature distribution's effect, strengthened 3D FPGA's stability and reliability.

(II) technical scheme

According to one aspect of the present disclosure, there is provided a 3D FPGA with a non-uniformly distributed channel structure, comprising: and the 3D switch box units comprise one or more 3D switch boxes, and the 3D switch boxes in the 3D switch box units are unevenly distributed on the XY plane of the 3D FPGA.

In some embodiments, the 3D FPGA comprises: a first 3D switchbox unit including one or more first 3D switchboxes including signal through-silicon vias of a first density in a Z direction; and a second 3D switchbox unit including one or more second 3D switchboxes including signal through-silicon vias of a second density in the Z direction; the first density is greater than the second density.

In some embodiments, the non-uniform distribution is a peripheral-center combined distribution, wherein a first 3D switch box of the first 3D switch box unit is distributed in a central area of the XY plane of the 3D FPGA, and a second 3D switch box of the second 3D switch box unit is distributed in a peripheral area of the XY plane of the 3D FPGA.

In some embodiments, the non-uniform distribution is a center-periphery combined distribution, wherein a first 3D switch box of the first 3D switch box unit is distributed in a peripheral area of the 3D FPGA XY plane, and a second 3D switch box of the second 3D switch box unit is distributed in a center area of the 3D FPGA XY plane.

In some embodiments, the non-uniform distribution is an alternating distribution, and the first 3D switch boxes of the first 3D switch box unit and the second 3D switch boxes of the second 3D switch box unit are alternately distributed on the XY plane of the 3D FPGA.

In some embodiments, the second 3D switch box includes a plurality of heat dissipating through silicon vias in the Z direction.

In some embodiments, the first 3D switch box includes one or more heat dissipating through-silicon vias, and the first 3D switch box includes a smaller number of heat dissipating through-silicon vias than the second 3D switch box.

In some embodiments, the 3D FPGA includes a plurality of planar layers along the Z-direction, the heat dissipating through-silicon vias span from a topmost layer to a bottommost layer of the plurality of planar layers along the Z-direction, the signal through-silicon vias span different numbers of planar layers depending on the channel length.

In some embodiments, the 3D FPGA with unevenly distributed channel structures further includes: a third 3D switchbox unit including one or more third 3D switchboxes including signal through-silicon vias of a third density in the Z direction; the second density is greater than the third density, and the first 3D switch box, the second 3D switch box and the third 3D switch box are alternately distributed on the XY plane of the 3D FPGA.

In some embodiments, the 3D FPGA with unevenly distributed channel structures further includes: a 2D switchbox unit comprising one or more 2D switchboxes, the 2D switchboxes being unevenly distributed with the 3D switchboxes.

(III) beneficial effects

From the above technical scheme, the non-uniformly distributed 3D FPGA with the channel structure of the present disclosure has at least one of the following beneficial effects:

(1) The channel structure of the 3D FPGA is unevenly distributed, the channel structure is flexible to set, and uneven temperature distribution of each slice caused by the existing single-form 3D FPGA channel structure is avoided.

(2) The density, the type and the distribution of the through silicon vias of the 3D switch box are adjusted, so that the channel structure is unevenly distributed, and the power consumption of a hotter area is reduced.

(3) Through adopting the through-silicon via hole of heat dissipation, reach balanced temperature distribution's effect, strengthened 3D FPGA's stability and reliability.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the accompanying drawings. Like reference numerals designate like parts throughout the drawings, and the drawings are not intended to be drawn to scale, such as to actual dimensions, with emphasis instead being placed upon illustrating the principles of the disclosure.

Fig. 1 is a schematic structural diagram of a 3D FPGA stacked by four layers of FPGA slices.

Fig. 2 is a schematic diagram of a switch distribution of one layer of a conventional 3D FPGA.

Fig. 3 is another switch distribution diagram of one layer of the conventional 3D FPGA.

Fig. 4 is another switch distribution diagram of one layer of the conventional 3D FPGA.

Fig. 5 is a schematic diagram of temperature distribution of layers of a 3D integrated circuit in an FPGA structure of a conventional four-layer CMOS circuit relying on through-silicon vias for thermal conduction.

Fig. 6 is a schematic diagram of temperature distribution of each layer of a 3D integrated circuit in an FPGA structure formed by four layers of CMOS circuits with uniformly distributed power consumption at each position according to heat conduction through silicon vias.

Fig. 7 is a schematic diagram of a peripheral-center distribution combination of a 3D FPGA channel structure according to an embodiment of the disclosure.

Fig. 8 is a schematic diagram of a 3D FPGA channel structure center-periphery distribution combination according to an embodiment of the disclosure.

Fig. 9 is a schematic diagram of alternate distribution of channel structure columns of a 3D FPGA according to an embodiment of the disclosure.

Fig. 10 is a schematic diagram of thermal profiles of two types of through silicon vias according to an embodiment of the present disclosure.

Detailed Description

For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.

In the drawings or description, like or identical parts are provided with the same reference numerals. Implementations not shown or described in the drawings are forms known to those of ordinary skill in the art. Additionally, although examples of parameters including particular values may be provided herein, it should be appreciated that the parameters need not be exactly equal to the corresponding values, but may be approximated to the corresponding values within acceptable error margins or design constraints. Directional terms such as "upper", "lower", "front", "rear", "left", "right", etc. mentioned in the embodiments are merely directions referring to the drawings. Accordingly, the directional terminology is used for purposes of illustration and is not intended to limit the scope of the disclosure.

The utility model provides a non-evenly distributed 3D FPGA of channel structure, comprehensive consideration power consumption distribution and heat distribution, through adjustment 3D switch box and the density, the type and the distribution of through-silicon via for the non-evenly distributed of channel structure, thereby reach the consumption that reduces hotter region, simultaneously through adopting the heat dissipation through-silicon via to dispel the heat, reach the effect of balanced temperature distribution, and the balanced distribution of temperature is favorable to reinforcing 3D FPGA's stability and reliability.

The utility model discloses a 3D FPGA of non-evenly distributed of channel structure, include: including a plurality of slices (slice plane, i.e., XY plane layer) along the Z direction, including a plurality of 3D switch box units on each slice, each 3D switch box unit including one or more 3D switch boxes, the 3D switch boxes in the plurality of 3D switch box units being unevenly distributed in the 3D FPGA XY plane.

Specifically, the 3D FPGA may include two types of 3D switch box units: a first 3D switch box unit including one or more first 3D switch boxes including signal through-silicon vias in a Z direction, the density of the signal through-silicon vias of the first 3D switch box in the Z direction being a first density; and a second 3D switch box unit including one or more second 3D switch boxes including signal through-silicon vias in a Z direction, the density of the signal through-silicon vias of the second 3D switch boxes in the Z direction being a second density; wherein the first density is greater than the second density.

More specifically, the 3D FPGA with unevenly distributed channel structures may further include: the third 3D switch box unit comprises one or more third 3D switch boxes, the third 3D switch boxes comprise signal through silicon through holes in the Z direction, and the density of the signal through silicon through holes of the third 3D switch boxes in the Z direction is third density; the second density is greater than the third density.

Preferably, the second 3D switch box includes a plurality of heat dissipation through silicon vias in the Z direction; the first 3D switch box includes one or more heat dissipation through silicon vias, and the number of heat dissipation through silicon vias included in the first 3D switch box is less than the number of heat dissipation through silicon vias included in the second 3D switch box.

The non-uniformly distributed 3D FPGA of the channel structure of the present disclosure is described in detail below with reference to the accompanying drawings and specific embodiments.

In one embodiment, as shown in fig. 7, the channel structure of the 3D FPGA is a peripheral-center distribution combination: the center of the Z-direction high-density switch box SWB (i.e. the density of the Z-direction signal through silicon vias is high) is distributed, and the periphery of the Z-direction low-density switch box (i.e. the density of the Z-direction signal through silicon vias is low) is distributed; the high-density switch boxes SWB in the Z direction are distributed in the center of each layer of XY plane of the 3D FPGA, the low-density switch boxes SWB are distributed at the periphery of each layer of XY plane of the 3D FPGA, and the high-density switch boxes SWB and the low-density switch boxes SWB can be complementary. Since the high density 3D switch box is only present in the central region of the planes, only the low density (with fewer signal through silicon vias) 3D switch box is placed in the peripheral region along each plane. The non-uniform channel structure and the heat dissipation structure are suitable for the situation that the periphery is hotter than the center; preferably, the high-density switch box with the center distribution can comprise one or more heat dissipation through silicon through holes; and/or the peripherally distributed low-density switch box Z direction can comprise a plurality of heat dissipation through silicon vias; the quantity of the heat dissipation through silicon through holes included in the low-density switch boxes distributed at the periphery is larger than that of the heat dissipation through silicon through holes included in the high-density switch boxes distributed at the center.

In a specific embodiment, the channel structure of the 3D FPGA is a center-periphery distribution combination: as shown in fig. 8, the Z-direction high-density switch boxes SWB are peripherally distributed, and the Z-direction low-density switch boxes SWB are centrally distributed; the Z-direction low-density 3D switch boxes are distributed on the periphery of each layer of plane of the 3D FPGA, the Z-direction high-density 3D switch boxes are distributed on the central area of each layer of plane of the 3D FPGA, and the Z-direction low-density 3D switch boxes and the Z-direction high-density 3D switch boxes can be complementary. The non-uniform channel structure and the heat dissipation structure are suitable for the condition that the center is hotter than the periphery. Preferably, the peripherally distributed high-density switch box can comprise one or more heat dissipation through silicon vias; and/or the centrally distributed low density switch box Z direction may include a plurality of heat dissipating through silicon vias. The quantity of the heat dissipation through silicon through holes included in the low-density switch boxes distributed in the center is larger than that of the heat dissipation through silicon through holes included in the high-density switch boxes distributed in the periphery.

In a specific embodiment, as shown in fig. 9, the channel structure of the 3D FPGA is a column alternating structure, the Z-direction density of the 3D switch boxes is determined according to the proportional relationship between the power consumption of the IP module and the power consumption of the programmable logic block CLB, and the channel structure includes three types of switch boxes, i.e., a high-density switch box, a medium-density switch box, and a low-density switch box, which are alternately arranged. The non-uniform channel structure and the heat dissipation structure are suitable for the situation that heat distribution is in a row alternation. Preferably, the high-density switch box, the medium-density switch box and the low-density switch box can selectively comprise heat dissipation through silicon vias in the Z direction.

In a specific embodiment, the channel structure of the 3D FPGA is a fully customized design based on the application program, and the number of Z-direction switches in the fully customized distributed 3D switch box is based on the application program. While such a layout may result in design irregularities to some extent that do not better accommodate the variations in function and application, the non-uniform channel structure and heat dissipation structure are well suited for use in situations where the heat distribution is custom-made.

The heat dissipation through silicon vias span as many planar layers as possible along the Z direction according to the condition of the spare area, and preferably span from the topmost layer to the bottommost layer of the plurality of planar layers. The signal through silicon vias span different numbers of planar layers depending on the channel length.

In order to further verify that the heat dissipation through-silicon vias have a better heat dissipation effect than the signal through-silicon vias, the following detailed description is given with reference to the experiment and the accompanying drawings. In the experiment, the through silicon vias of each layer are aligned to represent heat dissipation through silicon vias (thermal vias), and the through silicon vias of each layer are not aligned to represent signal through silicon vias (signal vias). Fig. 10 shows thermal profiles in two cases (where (a) is a heat dissipating through-silicon via and (b) is a signal through-silicon via). Table 4 shows the heat distribution statistics.

TABLE 4 statistical results of thermal distribution

As can be seen from the thermal profile statistics of table 4 and the thermal profiles of the two types of vias in fig. 10, the thermal vias (heat dissipating through-silicon vias) have a better heat dissipation effect.

Therefore, the effect of balancing the heat distribution can be effectively achieved by adopting the heat dissipation through silicon via. If the number of the signal through silicon vias in the hotter area is reduced in the FPGA, the heat dissipation through silicon vias can be placed in the empty space, so that the hotter area can be well dissipated, and the effect of balancing the heat distribution of the 3D FPGA is achieved.

Because the channel structure of the 3D FPGA is set, the special through silicon via hole which does not transmit signals is adopted to conduct heat, namely, the heat is dissipated through silicon via hole (thermal via hole or pseudo via hole), the layout mode of a plurality of thermal via holes can reduce the temperature of each plane of the upper layer of the 3D FPGA, the heat dissipation effect is improved, and the stability and the reliability of the 3D FPGA are enhanced.

In addition, the 3D FPGA of the present disclosure may further include a 2D switch box unit, the 2D switch box unit may include one or more 2D switch boxes, and the 2D switch boxes may be unevenly distributed with the 3D switch boxes.

Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. From the above description, it should be clear to those skilled in the art that the channel structure of the present disclosure is unevenly distributed 3D FPGA.

It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be modified or replaced simply by one skilled in the art, for example:

(1) The types of the switch box units are not limited to two or three, but may be more, and do not affect the implementation of the present disclosure as well.

(2) The 3D FPGA includes a plurality of slices, but the specific number of slices is not limited, and the present disclosure may be implemented.

Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.

The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present disclosure is not directed to any particular programming language. It will be appreciated that the disclosure described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present disclosure.

Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A channel structure non-uniformly distributed 3D FPGA comprising:

a plurality of 3D switch box units, each 3D switch box unit comprising one or more 3D switch boxes, the 3D switch boxes in the plurality of 3D switch box units being unevenly distributed in a 3D FPGA XY slice plane;

wherein, 3D FPGA includes:

a first 3D switchbox unit including one or more first 3D switchboxes including signal through-silicon vias of a first density in a Z direction; and

a second 3D switchbox unit including one or more second 3D switchboxes including signal through-silicon vias of a second density in the Z direction;

the first density is greater than the second density, the second 3D switch box comprises a plurality of heat dissipation through silicon through holes in the Z direction, the first 3D switch box comprises one or a plurality of heat dissipation through silicon through holes, the number of the heat dissipation through silicon through holes in the first 3D switch box is smaller than that in the second 3D switch box, the 3D FPGA comprises a plurality of plane layers along the Z direction, the heat dissipation through silicon through holes span from the topmost layer to the bottommost layer of the plurality of plane layers along the Z direction, and the signal through silicon through holes span plane layers with different numbers according to different channel lengths.

2. The channel structure non-uniformly distributed 3D FPGA of claim 1, wherein,

the non-uniform distribution is peripheral-center combined distribution, wherein the first 3D switch boxes of the first 3D switch box unit are distributed in the center area of the XY plane of the 3D FPGA, and the second 3D switch boxes of the second 3D switch box unit are distributed in the peripheral area of the XY plane of the 3D FPGA.

3. The channel structure non-uniformly distributed 3D FPGA of claim 1, wherein,

the non-uniform distribution is center-periphery combined distribution, wherein a first 3D switch box of the first 3D switch box unit is distributed in a peripheral area of the XY plane of the 3D FPGA, and a second 3D switch box of the second 3D switch box unit is distributed in a center area of the XY plane of the 3D FPGA.

4. The channel structure non-uniformly distributed 3D FPGA of claim 1, wherein,

the non-uniform distribution is alternating distribution, and the first 3D switch boxes of the first 3D switch box unit and the second 3D switch boxes of the second 3D switch box unit are alternately distributed on the XY plane of the 3D FPGA.

5. The channel structure non-uniformly distributed 3D FPGA of claim 1, further comprising:

a third 3D switchbox unit including one or more third 3D switchboxes including signal through-silicon vias of a third density in the Z direction;

the second density is greater than the third density, and the first 3D switch box, the second 3D switch box and the third 3D switch box are alternately distributed on the XY plane of the 3D FPGA.

6. The channel structure non-uniformly distributed 3D FPGA of claim 1, further comprising:

a 2D switchbox unit comprising one or more 2D switchboxes, the 2D switchboxes being unevenly distributed with the 3D switchboxes.