CN109428480B - Low current and low noise charge pump circuit and frequency synthesizer - Google Patents

Abstract

A low current and low noise charge pump circuit includes an output capacitor, first and second current source units, a charging switch, a discharging switch and a bypass switch. The charging switch is turned on in the conduction interval of the switching signal in response to the switching signal, so that the charging current from the first current source unit charges the output capacitor. The discharge switch is turned on in the off interval of the switch signal in response to the switch signal to discharge the output capacitor through the second current source unit. Among them, the switch signal controls the conduction of the charging switch before and after the conduction interval, and the bypass signal controls the conduction of the bypass switch so that the charging current flows to the ground terminal. During the period when the switch signal controls the charging switch to be conductive in the conduction interval, the bypass signal controls the bypass switch not to conduct.

Description

Low current and low noise charge pump circuit and frequency synthesizer

technical field

The present invention relates to a charge pump circuit, in particular to a charge pump circuit with low current and low noise and a frequency synthesizer.

Background technique

A frequency synthesizer is generally provided in a wireless communication system. Such frequency synthesizers supply high frequency signals within a determined frequency band to cover telecommunication frequency bands such as the US ISM band (902 to 928 MHz).

Generally speaking, when the frequency synthesizer is running, the phase detector in the frequency synthesizer detects the phase difference between the output of the crystal oscillator and the output of the voltage-controlled oscillator after the frequency reduction. The phase difference signal is sent to the charge pump to control the charge pump to charge and discharge the capacitor. Then, the output terminal of the capacitor is filtered to form a voltage signal to further control the voltage-controlled oscillator. The loop is thus formed to provide a stable frequency.

Among them, when the early phase detector control is used to drive the switching charge pump circuit, the entire charge pump circuit will be turned off. This causes a transient voltage to develop at the drain of the current source. This in turn causes jitter at the output of the current source, resulting in a nonlinear relationship between phase and output current. This nonlinearity then folds the high frequency noise of the charge pump circuit to low frequencies.

Therefore, a widely used charge pump circuit currently has an additional bypass for the supply voltage of the routing amplifier (as shown in FIG. 1A ). When the charge pump 900 charges and discharges the capacitor 901, a schematic diagram of the waveform of the current of the current source of the charge pump 900 is shown in FIG. 1B. The waveform diagram of the output current of the capacitor is shown in 1C. When the charge pump 900 does not charge or discharge the capacitor 901, the bypass is turned on. That is, when the switch of the charge pump 900 is switched so that the current source does not charge and discharge the capacitor 901, the current of the current source will be diverted to the bypass path. This allows the current output by the current source to keep flowing to avoid transient voltages at the drain of the current source. However, when the frequency synthesizer is locked, when the charge pump 900 only charges and discharges the capacitor 901 for a short time, the charge and discharge time only occupies a small part of the crystal oscillation period. This causes the current source's current to be discarded through the bypass path most of the time. In other words, this design leads to unnecessary energy waste.

In view of this, it is necessary to propose a feasible solution to solve the aforementioned problems, so as to reduce unnecessary waste.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a low-current and low-noise charge pump circuit, including an output capacitor, a first current source unit, a second current source unit, a charging switch, a discharging switch, and a bypass switch. The first current source unit provides the charging current according to the rated voltage. The second current source unit is coupled between the output capacitor and the ground. The charging switch is coupled between the output capacitor and the first current source unit, and is controlled by the switch signal. The charging switch receives the switching signal and conducts in the conduction period of the switching signal so that the charging current charges the output capacitor. The discharge switch is coupled between the output capacitor and the second current source unit and controlled by the switch signal. The discharge switch receives the switch signal and conducts in the off interval of the switch signal to discharge the output capacitor. The bypass switch is coupled between the first current source unit and the ground terminal and controlled by the bypass signal. Wherein, before and after the switch signal controls the conduction of the charging switch in the conduction interval, the bypass signal controls the conduction of the bypass switch so that the charging current flows to the ground terminal. The bypass signal controls the bypass switch to be non-conductive during the period when the switch signal controls the charging switch to be turned on in the conduction interval.

Another embodiment of the present invention provides a frequency synthesizer, which includes a charge pump circuit, a phase frequency detection circuit, a phase shift pulse width modulation circuit, and a logic operation circuit. The charge pump circuit includes an output capacitor, a first current source unit, a second current source unit, a charging switch, a discharging switch, and a bypass switch. The first current source unit provides the charging current according to the rated voltage. The second current source unit is coupled between the output capacitor and the ground. The charging switch is coupled between the output capacitor and the first current source unit, and is controlled by the switch signal. The charging switch receives the switching signal and conducts in the conduction period of the switching signal so that the charging current charges the output capacitor. The discharge switch is coupled between the output capacitor and the second current source unit and controlled by the switch signal. The discharge switch receives the switch signal and conducts in the off interval of the switch signal to discharge the output capacitor. The bypass switch is coupled between the first current source unit and the ground terminal and controlled by the bypass signal. The phase frequency detection circuit is coupled to the charging switch and the discharging switch. The phase frequency detection circuit outputs the switch signal according to the frequency signal and the frequency division signal. The phase-shifted pulse width modulation circuit outputs the phase-shifted pulse signal according to the frequency signal. The time when the phase-shifted pulse signal is at a high level covers the conduction period of the switching signal. The logic operation circuit is coupled between the phase frequency detection circuit, the phase shift circuit and the bypass switch. The logic operation circuit generates the bypass signal according to the switch signal and the phase-shifted pulse signal.

According to the foregoing embodiment, the charge pump circuit is turned off when not in use, and before the charge and discharge switch is to be turned on and the charge and discharge switch is to be turned off, the bypass switch is first turned on so that the drain of the current source unit reaches After the steady-state voltage, the bypass switch is switched to be non-conductive, and the charging and discharging switch is switched. In this way, the steady-state voltage between the current source unit and the charge-discharge switch can be maintained. In addition, the voltage generated between the first current source unit and the charging switch due to the charging current accumulation can be avoided. It also reduces the current discarded by the bypass switch to save current. It is also possible to maintain a linear relationship between phase and output current to avoid the high frequency noise of the charge pump circuit from folding into low frequencies. Furthermore, when applied to a frequency synthesizer, it does not interfere with the operation of the frequency synthesizer.

Description of drawings

FIG. 1A is a schematic diagram of a structure of the prior art.

FIG. 1B is a schematic diagram of a waveform of an output current of a current source in the prior art.

FIG. 1C is a schematic diagram of a waveform of an output current of a capacitor in the prior art.

FIG. 2 is a schematic structural diagram of an embodiment of a charge pump circuit of the present invention.

FIG. 3A is a schematic waveform diagram of the frequency signal of FIG. 2 according to an embodiment.

FIG. 3B is a schematic diagram of waveforms of the switching signal of FIG. 2 according to an embodiment.

FIG. 3C is a schematic diagram of waveforms of the bypass signal of FIG. 2 according to an embodiment.

FIG. 3D is a schematic waveform diagram of an embodiment of the phase-shifted pulse signal of FIG. 2 .

FIG. 3E is a schematic waveform diagram of an output voltage of the first current source unit of FIG. 2 according to an embodiment.

FIG. 3F is a schematic diagram of waveforms of an output voltage of the output capacitor of FIG. 2 according to an embodiment.

FIG. 3G is a schematic waveform diagram of an output current of the first current source unit of FIG. 2 according to an embodiment.

FIG. 3H is a schematic diagram of a waveform of an output current of the output capacitor of FIG. 2 according to an embodiment.

FIG. 4 is a schematic structural diagram of another embodiment of the charge pump circuit of the present invention.

The reference numerals are:

10 Output capacitor 20 First current source unit

30 Second current source unit 40 Charge switch

50 discharge switch 60 bypass switch

61 Bypass Switch 62 Amplifier

70 phase frequency detection circuit 80 phase shift pulse width modulation circuit

90 logic operation circuit 900 charge pump

901 capacitor SS-U, SS-D, S-switch switch signal

SB-U, SB-D, S-bypass bypass signal

t11, t21, t22 conduction interval

t12, t23, t24 disconnection interval

S-clk frequency signal

S-div frequency division signal

S-shift phase-shifted pulse signal

Vi1, Vcout output voltage

Ii1, Icout output current

Detailed ways

FIG. 2 is a schematic structural diagram of an embodiment of a charge pump circuit of the present invention. Referring to FIG. 2 , the charge pump circuit includes: an output capacitor 10 , a first current source unit 20 , a second current source unit 30 , a charging switch 40 , a discharging switch 50 and a bypass switch 60 . The charging switch 40 is coupled between the first current source unit 20 and the output capacitor 10 . The discharge switch 50 is coupled between the second current source unit 30 and the output capacitor 10 . The bypass switch 60 is coupled between the first current source unit 20 and the ground terminal. The first current source unit 20 is coupled to the charging switch 40 and the bypass switch 60 . The second current source unit 30 is coupled between the discharge switch 50 and the ground terminal.

In one embodiment, the other end of the first current source unit 20 relative to the charging switch 40 is coupled to a rated voltage circuit (which provides a rated voltage). That is, the input terminal of the first current source unit 20 is coupled to the rated voltage circuit and receives the rated voltage supplied by the rated voltage circuit. The output terminal of the first current source unit 20 is coupled to the first terminal of the charging switch 40 and to the first terminal of the bypass switch 60 . The second terminal of the charging switch 40 is coupled to the output capacitor 10 . The first current source unit 20 is used for providing a charging current of a fixed value according to the rated voltage, and the charging current can charge the output capacitor 10 through the charging switch 40 . Among them, the rated voltage is a fixed value.

In one embodiment, the other end of the second current source unit 30 relative to the discharge switch 50 is coupled to the ground. That is, the input terminal of the second current source unit 30 is coupled to the first terminal of the discharge switch 50 . The output terminal of the second current source unit 30 is coupled to the ground terminal. The second terminal of the discharge switch 50 is coupled to the output capacitor 10 . When the discharge switch 50 is turned on, the output capacitor 10 can be discharged through the discharge switch 50 and the second current source unit 30 with a discharge current of a fixed value. Here, the charging switch 40 and the discharging switch 50 are not turned on at the same time.

The current value of the charging current and the discharging current may be the same or different, but the current value of the charging current and the current value of the discharging current are not limited in the present invention.

In one embodiment, the switch signal SS-U or SS-D (hereinafter collectively referred to as S-switch) has an on interval and an off interval.

The control terminal of the charging switch 40 receives the switching signal SS-U, and the charging switch 40 is turned on in the conduction interval t11 according to the switching signal SS-U, so that the charging current charges the output capacitor 10 through the charging switch 40 . In other words, the charging switch 40 is turned off in response to the switch signal SS-U in the off interval t12.

The control terminal of the discharge switch 50 receives the switch signal SS-D, and the discharge switch 50 is turned on in the conduction interval according to the switch signal SS-D, so that the output capacitor 10 is set to the rated current value (discharge current) of the second current source unit 30 . ) to discharge. In other words, the discharge switch 50 is non-conductive in response to the switch signal SS-U in the off interval.

In one embodiment, the time when the switch signal S-switch is maintained at a high level is an on period, and the time when the switch signal S-switch is maintained at a low level is an off period. In other words, when the control terminal of the charging switch 40 receives the switch signal SS-U with a high potential, the charging switch 40 is switched to be turned on, and the charging switch 40 is maintained at a high potential during the period when the switching signal SS-U is at a high potential (that is, the charging switch 40 is turned on). ON interval) will maintain the ON state. When the charging switch 40 is turned on, the charging current output by the first current source unit 20 will flow through the charging switch 40 and then flow to the output capacitor 10 to charge the output capacitor 10 .

Similarly, when the control terminal of the discharge switch 50 receives the switch signal SS-D with a high potential, the discharge switch 50 is switched to be turned on, and the discharge switch 50 is maintained at a high potential during the period of the switch signal SS-D (that is, the discharge switch is turned on). interval) will remain on. When the discharge switch 50 is turned on, the output capacitor 10 is coupled to the second current source unit 30 through the discharge switch 50, and is coupled to the ground terminal through the discharge switch 50 and the second current source unit 30, so that the second current source unit 30 rated current value (discharge current) to discharge.

In some embodiments, the charging switch 40 and the discharging switch 50 may be switch components such as NMOS, PMOS, CMOS, transistor, etc., respectively, but the present invention is not limited thereto.

For example, if the charging switch 40 is a MOS switch element, and the charging switch 40 has a gate, a source and a drain. The source is connected to the rated voltage circuit to receive the rated voltage. The drain is connected to the charge switch 40 . The gate receives the switch signal S-switch, and according to the switch signal S-switch, the source and the drain can be turned on or off.

In one embodiment, the bypass signal S-bypass (SB-D or SB-U) has an on interval and an off interval.

In one embodiment, the control terminal of the bypass switch 60 receives a bypass signal SB-D, and the bypass switch 60 is turned on or off according to the bypass signal SB-D. In other words, the bypass switch 60 is turned on in response to the bypass signal SB-D during the ON period of the bypass signal SB-D, and the bypass switch 60 is turned on in response to the bypass signal SB-D during the OFF period of the bypass signal SB-D U is not conducting. When the bypass switch 60 is turned on, the charging current drawn by the first current source unit 20 can flow to the ground terminal through the bypass switch 60 .

Here, before the charging switch 40 is turned on according to the switch signal SS-U and after the charging switch 40 is switched from conducting to non-conducting according to the switching signal SS-U, the bypass switch 60 is turned on according to the bypass signal SB-D Pass. In addition, during the period when the charging switch 40 is turned on according to the switch signal SS-U, the bypass switch 60 is turned off according to the bypass signal SB-U. In other words, before and after the conduction period of the switch signal SS-U occurs, the bypass signal SB-D will have a conduction period of a predetermined time respectively. While the ON period of the switch signal SS-U occurs, the OFF period of the bypass signal SB-D occurs. In this way, the voltage generated by the charge pump circuit can be prevented from accumulating between the first current source unit 20 and the charging switch 40 due to the charging current. It also reduces the current discarded through the bypass switch 60 to save current, and also maintains a linear relationship between phase and output current to avoid the high frequency noise of the charge pump circuit from collapsing to low frequencies.

In some embodiments, the charge pump circuit may further include another bypass switch 61 . The bypass switch 61 is coupled to the discharge switch 50 and the second current source unit 30 . The bypass switch 61 is turned on or off according to the bypass signal SB-D. Here, the bypass switch 60 and the bypass switch 61 are not turned on at the same time.

Here, before the discharge switch 50 is turned on according to the switch signal SS-D and after the discharge switch 50 is switched from on to off according to the switch signal SS-D, the bypass switch 61 is turned on according to the bypass signal SB-U Pass. In addition, during the period when the discharge switch 50 is turned on according to the switch signal SS-D, the bypass switch 61 is turned off according to the bypass signal SB-D. In this way, the charge pump circuit does not accumulate voltage between the second current source unit 30 and the discharge switch 50 . And it can maintain a linear relationship between the phase and the output current, and can avoid the problem of high-frequency noise folding.

In some embodiments, the bypass switches 60 and 61 may be switch components such as NMOS, PMOS, CMOS, transistors, etc., but the present invention is not limited thereto. FIG. 3A is a schematic waveform diagram of the switch signal S-switch of FIG. 2 according to an embodiment. Referring to FIG. 3A , the switch signal S-switch includes an on interval t11 and an off interval t12 . Here, the switch signal S-switch is at a high level in the conduction period t11 , and the switch signal S-switch is about 1 volt (V) as shown in FIG. 3A . In addition, the switch signal S-switch is at a low level in the off interval t12, and the switch signal S-switch is about 0V as shown in FIG. 3B.

FIG. 3B is a schematic waveform diagram of the bypass signal S-bypass of FIG. 2 according to an embodiment. Referring to FIG. 3B , the bypass signal S-bypass includes on intervals t21 and t22 and off intervals t23 and t24 . Here, the bypass signal S-bypass is at a high level during the conduction periods t21 and t22, and the bypass signal S-bypass is about 1 volt (V) as shown in FIG. 3B . In addition, the bypass signal S-bypass is at a low level in the off periods t23 and t24, and the bypass signal S-bypass is about 0V as shown in FIG. 3C.

Referring to FIGS. 3A and 3B , in the conduction period t11 of the switch signal S-switch, the switch signal S-switch drives the charging switch 40 (or the discharge switch 50 ) to conduct, and the bypass signal S-bypass drives the bypass switch 60 (or 61) is not turned on (that is, the bypass signal S-bypass is in the off interval t23). That is to say, the bypass signal S-bypass will be pulled to a high level first (into the conduction period t21 ) before the switch signal S-switch enters the conduction interval t11 for a predetermined time (the time length of t21 ). When the switch signal S-switch enters the conduction interval t11, the bypass signal S-bypass is instantly pulled to a low level (the time boundary between t21 and t23). And the time length of the bypass signal S-bypass at the low level (the off interval t23 ) is approximately equal to the time length of the on interval t11 of the switch signal S-switch. In addition, when the ON period t11 of the switch signal S-switch ends and will enter the OFF period t12 (the time boundary between t23 and t12), the bypass signal S-bypass will be instantly pulled to a high level (into the ON period t22) And maintain for a preset time (the time length of t22), and then pull back to the low level (the time boundary between t22 and t24). In other words, the on period t21, the off period t23 and the on period t22 of the bypass signal S-bypass occur in sequence, and the off period t23 of the bypass signal S-bypass and the on period t11 of the switch signal S-switch occur in sequence. roughly in sync.

In other words, the conduction period t11 of the switch signal S-switch is the time period when the voltage is 1V as shown in FIG. 3A . At the same time as this time interval (on interval t11 ), the bypass signal S-bypass in FIG. 3B is at a low level (off interval t23 ). At this time, the charging switch 40 (or the discharging switch 50 ) is turned on, and the bypass switch 60 (or 61 ) is not turned on. In the preset time before and after the conduction interval t11 of the switch signal S-switch, that is, in the preset time before and after the time interval in which the voltage of the switch signal S-switch is 1V, the bypass signal S-bypass is located at High potential (conduction interval t21, t22). At this time, the charge switch 40 (or the discharge switch 50) is not turned on, but the bypass switch 60 (or 61) is turned on, so as to allow the current source unit (20 or 30) and the charge and discharge switch (the charge switch 40 or discharge The voltage between switches 50) is allowed to flow to ground. In this way, before the charge-discharge switch is turned on, the steady-state voltage between the current source unit and the charge-discharge switch can be reached in advance. Further, the high voltage at the moment when the charging switch 40 is turned on can be prevented from flowing to the output capacitor 10 . This maintains a linear relationship between phase and output current and is more immune to high frequency noise folding problems. Wherein, the time length of the preset time is not limited in the present invention. In addition, the preset time period of the bypass signal S-bypass before and after the conduction period t11 of the switch signal S-switch may be the same (that is, the time length of the conduction period t21 is the same as the conduction period t22 ), or may be different ( That is, the time length of the conduction interval t21 is different from that of the conduction interval t22), which can be adjusted according to requirements.

In an embodiment, please refer back to FIG. 2 , when the charge pump circuit is applied to the frequency synthesizer, the charge pump circuit is further coupled with a phase frequency detection circuit 70 , a phase shift pulse width modulation circuit 80 and a logic operation circuit. 90. The output terminal of the phase frequency detection circuit 70 is coupled to the input terminal of the logic operation circuit 90 , the control terminal of the charging switch 40 and the control terminal of the discharging switch 50 . The input terminal of the phase-shifted PWM circuit 80 receives the frequency signal S-clk. The output terminal of the phase-shifted PWM circuit 80 is coupled to the input terminal of the logic operation circuit 90 . The output terminal of the logic operation circuit 90 is coupled to the control terminal of the bypass switch 60 (and the control terminal of the bypass switch 61 ).

The phase frequency detection circuit 70 receives the frequency signal S-clk and the frequency division signal S-div, and outputs a switch signal SS-U (or SS-D) according to the frequency signal S-clk and the frequency division signal S-div. The phase-shift pulse width modulation circuit 80 receives the frequency signal S-clk, and performs phase shift and pulse width modulation on the frequency signal S-clk to generate a phase-shifted pulse signal S-shift. The logic operation circuit 90 generates the bypass signal SB-U (or SB-D) according to the switch signal SS-U (or SS-D) and the phase-shifted pulse signal S-shift.

In one embodiment, the logic operation circuit 90 includes a mutually exclusive OR gate. The input ends of the mutually exclusive OR gate are respectively coupled to the phase frequency detection circuit 70 and the phase shift pulse width modulation circuit 80, and respectively receive the switch signal S-switch and the phase shift pulse signal S-shift. The output terminal of the mutual exclusive OR gate is coupled to the control terminal of the bypass switch 60 (and the control terminal of the bypass switch 61 ), and outputs the bypass signal S-bypass. That is to say, when there is a potential difference between the switch signal S-switch and the phase-shifted pulse signal S-shift, the bypass signal S-bypass output by the mutually exclusive OR gate is at a low potential. When the switch signal S-switch and the phase-shifted pulse signal S-shift have the same potential, the bypass signal S-bypass output by the mutually exclusive OR gate is at a high potential. In this way, the conduction period of the switch signal S-switch can drive the charging switch 40 to be turned on, so that the bypass switch 60 is not turned on.

For example, when the charge pump circuit adopts two bypass switches 60 and 61, the logic operation circuit 90 can use two mutually exclusive OR gates to generate the bypass signals SB-U and SB-D. In other words, one of the exclusive OR gates receives the switch signal SS-U and the phase-shifted pulse signal S-shift and outputs the bypass signal SB-U, while the other one of the exclusive OR gates receives the switch signal SS- D and the phase-shifted pulse signal S-shift and output the bypass signal SB-D.

In some embodiments, the frequency signal S-clk can be generated by an oscillator circuit (not shown). The frequency dividing signal S-div can be generated by a frequency dividing circuit (not shown).

FIG. 3C is a schematic waveform diagram of the frequency signal S-clk of FIG. 2 according to an embodiment. Referring to FIG. 3C , the phase frequency detection circuit 70 uses the frequency signal S-clk as a reference signal to detect the phase of the frequency division signal S-div, and generates a corresponding signal when the frequency division signal S-div and the frequency signal S-clk are not synchronized The switch signal SS-U or SS-D. In this embodiment, the frequency signal S-clk has a duty cycle of about 50%.

3A to 3C , when the phase frequency detection circuit 70 detects that the frequency signal S-clk is ahead of the frequency division signal S-div, the phase frequency detection circuit 70 outputs a high-level switching signal SS-U (on interval t11 ) until The frequency signal S-clk is synchronized with the frequency division signal S-div, and the switching signal SS-D (or the switching signal SS-D maintained at a low level) is not output. At this time, the switch signal S-switch shown in FIG. 3A is the representative switch signal SS-U, and the bypass signal S-bypass shown in FIG. 3B is the representative bypass signal SB-U.

When the phase frequency detection circuit 70 detects that the frequency division signal S-div leads the frequency signal S-clk, the phase frequency detection circuit 70 outputs a high-level switching signal SS-D (on interval t11 ) until the frequency signal S-clk and the frequency signal S-clk are The frequency dividing signal S-div is synchronized without outputting the switching signal SS-U (or the switching signal SS-U maintained at a low level). At this time, the switch signal S-switch shown in FIG. 3A is the representative switch signal SS-D, and the bypass signal S-bypass shown in FIG. 3B is the representative bypass signal SB-D.

When the phase frequency detection circuit 70 detects that the frequency signal S-clk is synchronized with the frequency division signal S-div, the phase frequency detection circuit 70 does not output the switching signals SS-U, SS-D (or the switching signals that are both maintained at low levels) SS-U, SS-U). At this time, the bypass signals SB-U and SB-D are also maintained at a low level.

FIG. 3D is a schematic waveform diagram of an embodiment of the phase-shifted pulse signal S-shift of FIG. 2 . In an embodiment, referring back to FIGS. 3A to 3D , the phase-shifted pulse width modulation circuit 80 shifts a phase difference and a pulse width difference of the frequency signal S-clk to output a phase-shifted pulse signal S- shift. Here, the time during which the phase-shifted pulse signal S-shift is at a high level is the time that covers the conduction period t11 of the switch signal S-switch. That is, during the period in which the phase-shifted pulse signal S-shift is maintained at a high potential, the conduction period t11 of the switching signal S-switch occurs. In addition, the conduction period t11 of the switch signal S-switch is shorter than the period during which the phase-shifted pulse signal S-shift is maintained at a high potential.

In one embodiment, the period of the phase-shifted pulse signal S-shift is equal to the period of the bypass signal S-bypass, and the time period during which the phase-shifted pulse signal S-shift is at a high level is approximately equal to the period of the bypass signal S-bypass. The time length of the conduction intervals t21 and t22 is added to the time length of the conduction interval t11 of the switch signal S-switch.

Here, the time lengths (predetermined time) of the conduction intervals t21 and t22 of the bypass signal S-bypass can be determined by adjusting the time point and time length when the phase-shifted pulse signal S-shift is at a high level. Wherein, the length of time that the phase-shifted pulse signal S-shift is at a high level is not limited in the present invention, and can be adjusted according to requirements.

FIG. 3E is a schematic waveform diagram of an embodiment of the output voltage Vi1 of the first current source unit 20 of FIG. 2 . FIG. 3F is a schematic waveform diagram of the output voltage Vcout of the output capacitor 10 of FIG. 2 according to an embodiment. FIG. 3G is a schematic waveform diagram of the output current Ii1 of the first current source unit 20 of FIG. 2 according to an embodiment. FIG. 3H is a schematic waveform diagram of the output current Icout of the output capacitor 10 of FIG. 2 according to an embodiment. Referring to FIGS. 3A to 3H , the bypass signal S-bypass is used to drive the bypass switch 60 to be turned on and off, so that the charging current does not accumulate voltage between the first current source unit 20 and the charging switch 40 . And it can maintain a linear relationship between the phase and the output current, and can avoid the problem of high-frequency noise folding.

In one embodiment, the charge pump circuit may not use an amplifier. In this case, the second terminal of the bypass switch 60 is coupled to the ground terminal. Therefore, when the bypass switch 60 is turned on, the charging current provided by the first current source unit 20 can flow to the ground terminal through the bypass switch 60 . In addition, when the charge pump circuit is provided with the bypass switch 61, the first end of the bypass switch 61 is coupled to the discharge switch 50 and the second current source unit 30, and the second end of the bypass switch 61 is coupled to the rated voltage circuit.

In one embodiment, the charge pump circuit may employ an amplifier. FIG. 4 is a schematic structural diagram of another embodiment of the charge pump circuit of the present invention. Referring to FIG. 4 , the charge pump circuit may further include an amplifier 62 . The input terminal of the amplifier 62 is coupled to the second terminal of the charging switch 40 and the output capacitor 10 . The output terminal of the amplifier 62 is coupled to the second terminal of the bypass switch 60 (and the second terminal of the other bypass switch 61 ). That is, the second terminal of the other bypass switch 61 is coupled to the second terminal of the bypass switch 60 and the output terminal of the amplifier 62 at the same time. The first end of the bypass switch 61 is coupled to the second current source unit 30 and the first end of the discharge switch 50 . In this way, the bypass switch 61 can also be turned on during the period before and after the discharge switch 50 is turned on, and is not turned on during the turn on of the discharge switch 50 . In addition, the bypass switch 61 is non-conductive during the conduction period of the charging switch 40 .

According to the above-mentioned embodiments, the charge pump circuit is turned off when not in use, and then the bypass is turned on before the charge and discharge switch (the charge switch 40 or the discharge switch 50 ) is to be turned on and the charge and discharge switch is turned off. The bypass switch 60 (or 61) makes the drain of the current source unit (20 or 30) reach the steady-state voltage, and then switches the bypass switch 60 (or 61) to non-conducting, and switches the charging and discharging switch. In this way, the steady-state voltage between the current source unit and the charge-discharge switch can be maintained. It is also possible to avoid the accumulation of voltages generated between the first current source unit 20 and the charging switch 40 due to the charging current. Also, the current discarded through the bypass switch 60 (or 61 ) can be reduced to save current. It is also possible to maintain a linear relationship between phase and output current to avoid the high frequency noise of the charge pump circuit from folding into low frequencies. Furthermore, when applied to a frequency synthesizer, it does not interfere with the operation of the frequency synthesizer.

Claims (9)

1. A charge pump circuit with low current and low noise, characterized in that, comprising: an output capacitor; a first current source unit, providing a charging current according to a rated voltage; a second current source unit, coupled between the output capacitor and the ground; A charging switch, coupled between the output capacitor and the first current source unit, is controlled by a switch signal, wherein the charging switch receives the switch signal and conducts in a conduction interval of the switch signal to make the switch signal The charging current charges the output capacitor; A discharge switch, coupled between the output capacitor and the second current source unit, is controlled by the switch signal, wherein the discharge switch receives the switch signal and conducts in an off interval of the switch signal to make the switch signal output capacitor discharge; and a bypass switch, coupled between the first current source unit and the ground terminal, controlled by a bypass signal; Wherein, before and after the switch signal controls the charging switch to be turned on in the conduction interval, the bypass signal controls the bypass switch to be turned on so that the charging current flows to the ground terminal; and Wherein, during the period when the switch signal controls the charging switch to be turned on in the conduction interval, the bypass signal controls the bypass switch to be turned off; the switch signal is generated based on a frequency signal and a frequency division signal, and the bypass signal is generated based on a frequency signal and a frequency division signal. The path signal is based on the switch signal and a phase-shifted pulse signal, and there is a phase difference and a pulse width difference between the phase-shifted pulse signal and the frequency signal. 2 . The charge pump circuit with low current and low noise as claimed in claim 1 , further comprising another bypass switch, and the other bypass switch is coupled to the discharge switch and the second current source unit. 3 . 3. The low current and low noise charge pump circuit as claimed in claim 2, further comprising an amplifier, the input end of the amplifier is coupled to the output capacitor, and the output end of the amplifier is coupled to the bypass switch and the other bypass switch. 4 . The charge pump circuit with low current and low noise as claimed in claim 1 , wherein the time when the phase-shifted pulse signal is at a high level covers the conduction interval of the switch signal. 5 . 5 . The charge pump circuit with low current and low noise as claimed in claim 4 , wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the phase-shifted pulse signal is located at the high potential. 6 . The time is equal to the sum of the time that the bypass signal is at a high level and the time of the conduction interval of the switch signal. 6 . The charge pump circuit with low current and low noise as claimed in claim 5 , further comprising a logic operation circuit, the logic operation circuit is coupled to the bypass switch, and the logic operation circuit receives the phase-shifted pulse wave. 7 . The bypass signal is generated from the signal and the switch signal according to the switch signal and the phase-shifted pulse signal. 7 . The charge pump circuit with low current and low noise as claimed in claim 6 , wherein the logic operation circuit comprises a mutually exclusive OR gate, and an input end of the mutually exclusive OR gate receives the switch signal and the phase-shift pulse. 8 . wave signal, the output terminal of the mutually exclusive OR gate outputs the bypass signal. 8. A frequency synthesizer, characterized in that, comprising: The charge pump circuit with low current and low noise as claimed in any one of claims 1 to 3; a phase frequency detection circuit, coupled to the charging switch and the discharging switch, and outputting the switching signal according to a frequency signal and a frequency dividing signal; a phase-shifted pulse width modulation circuit that outputs a phase-shifted pulse signal according to the frequency signal, wherein the time when the phase-shifted pulse signal is at a high level covers the conduction interval of the switch signal; and a logic operation circuit coupled between the phase frequency detection circuit, the phase-shifted pulse width modulation circuit and the bypass switch, the logic operation circuit generates the bypass according to the switch signal and the phase-shifted pulse signal Signal. 9 . The frequency synthesizer of claim 8 , wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the time that the phase-shifted pulse signal is at the high level is equal to the bypass signal. 10 . The time that the signal is at a high level is the sum of the time of the conduction interval of the switch signal.

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