CN109428480A

CN109428480A - low-current low-noise charge pump circuit and frequency synthesizer

Info

Publication number: CN109428480A
Application number: CN201710778829.8A
Authority: CN
Inventors: 陈瑞斌
Original assignee: Holtek Semiconductor Inc
Current assignee: Holtek Semiconductor Inc
Priority date: 2017-08-29
Filing date: 2017-09-01
Publication date: 2019-03-05
Anticipated expiration: 2037-09-01
Also published as: TWI645660B; TW201914188A; CN109428480B

Abstract

A low current and low noise charge pump circuit includes an output capacitor, first and second current source units, a charging switch, a discharging switch and a bypass switch. The charging switch is turned on in the conduction interval of the switching signal in response to the switching signal, so that the charging current from the first current source unit charges the output capacitor. The discharge switch is turned on in the off interval of the switch signal in response to the switch signal to discharge the output capacitor through the second current source unit. Among them, the switch signal controls the conduction of the charging switch before and after the conduction interval, and the bypass signal controls the conduction of the bypass switch so that the charging current flows to the ground terminal. During the period when the switch signal controls the charging switch to be conductive in the conduction interval, the bypass signal controls the bypass switch not to conduct.

Description

The charge pump circuit and frequency synthesizer of low current low noise

Technical field

The present invention relates to charge pump circuit, the charge pump circuit of especially a kind of low current low noise and frequency synthesis Device.

Background technique

Can generally have frequency synthesizer in wireless communication system.These frequency synthesizers are supplied in determined frequency band High-frequency signal, to cover telecom band, such as U.S.'s ISM band (902 to 928MHz).

In general, frequency synthesizer, when operation, phase detectors therein are after crystal oscillator output and frequency reducing Voltage controlled oscillator output phase difference detection.This phase signal can be sent to charge pump, with control charge pump to capacitor into Row charge and discharge.Then voltage signal is formed through filtering in the output end of capacitor, further to control voltage controlled oscillator.Such shape At circuit, to provide stable frequency.

Wherein, when the phase detectors of early stage are controlled with driving switch charge pump circuit, entire charge pump circuit can be closed It closes.This will lead to instantaneous voltage and is formed at the drain electrode of current source.And then make current source output shake, will cause phase with The relationship presentation exported between electric current is non-linear.Then this nonlinear phenomenon can allow the high-frequency noise of charge pump circuit to fold into Low frequency.

Therefore, the existing charge pump circuit being widely used, the bypass of its more routing amplifier supply voltage (are such as schemed at present Shown in 1A).When charge pump 900 is to 901 charge and discharge of capacitor, the waveform diagram of the electric current of current source is as shown in Figure 1B.Its The waveform diagram of the output electric current of capacitor is as shown in 1C.When charge pump 900 is not to 901 charge and discharge of capacitor, bypass can be led It is logical.That is, when the switching of charge pump 900 switch is switched and makes current source not to 901 charge and discharge of capacitor, current source Electric current can change by-passing path.The electric current that current source can be allowed to export whereby keeps flowing, produces to avoid at the drain electrode of current source Raw instantaneous voltage.But when frequency synthesizer locking, when charge pump 900 only does charge and discharge in short-term to capacitor 901, charge and discharge Time only accounts for the sub-fraction in crystal oscillation period.This will cause the electric current of most of the time current source all through bypass path and by It throws aside.In other words, this design will lead to unnecessary energy waste.

In view of this, again necessary propose that a kind of feasible solution is aforementioned to solve the problems, such as, it is unnecessary to reduce Waste.

Summary of the invention

One embodiment of the invention provides a kind of charge pump circuit of low current low noise, includes output capacitance, the first electric current Source unit, the second current source cell, charge switch, discharge switch and by-pass switch.First current source cell is according to specified electricity Pressure provides charging current.Second current source cell couples between output capacitance and ground terminal.Charge switch is coupled to output capacitance Between the first current source cell, and it is controlled by switching signal.Charge switch receives switching signal and leading in switching signal Logical section is connected and charging current is made to charge output capacitance.Discharge switch be coupled to output capacitance and the second current source cell it Between and be controlled by switching signal.Wherein discharge switch receives switching signal and is connected and makes defeated in the disconnect interval of switching signal Capacitor discharges out.By-pass switch is coupled between the first current source cell and ground terminal and is controlled by by-passing signal.Wherein, it is opening OFF signal in conducting range restraint charge switch conducting before and after, by-passing signal control by-pass switch conducting and make charging current It flow to ground terminal.Wherein, in switching signal during the conducting of range restraint charge switch is connected, by-passing signal control bypass is opened Pass is not turned on.

Another embodiment of the present invention provides a kind of frequency synthesizers, include charge pump circuit, phase frequency detection circuit, phase Shifting formula wide pulse width power transformation road and logical operation circuit.Charge pump circuit includes output capacitance, the first current source cell, second Current source cell, charge switch, discharge switch and by-pass switch.First current source cell provides charging electricity according to voltage rating Stream.Second current source cell couples between output capacitance and ground terminal.Charge switch is coupled to output capacitance and the first current source Between unit, and it is controlled by switching signal.Charge switch receive switching signal and in the conducting section of switching signal conducting and Charging current is set to charge output capacitance.Discharge switch is coupled between output capacitance and the second current source cell and is controlled by out OFF signal.Wherein discharge switch receives switching signal and is connected in the disconnect interval of switching signal and output capacitance is made to discharge. By-pass switch is coupled between the first current source cell and ground terminal and is controlled by by-passing signal.The coupling of phase frequency detection circuit Charge switch and discharge switch.Phase frequency detection circuit output switching signal according to frequency signal and frequency elimination signal.Phase shift Formula wide pulse width power transformation road exports phase shift pulse wave signal according to frequency signal.The time that phase shift pulse wave signal is located at high potential is to contain The conducting section of lid switching signal.Logical operation circuit couples between phase frequency detection circuit, phase-shift circuit and by-pass switch. Logical operation circuit generates by-passing signal according to switching signal and phase shift pulse wave signal.

According to previous embodiment, charge pump circuit is closed in when not in use, and to switch to conducting in charge and discharge switch Before and charge and discharge switch will switch to before being not turned on, and by-pass switch, which is first connected, makes the drain electrode of current source cell reach stable state Switching by-pass switch after voltage again is to be not turned on, and carry out the switching of charge and discharge switch.So current source cell can be maintained and filled Steady state voltage between discharge switch.And it is avoided that between the first current source cell and charge switch and accumulates institute because of charging current The voltage of generation.And it can be reduced the electric current thrown aside through by-pass switch also to save electric current.In addition it can also make phase and output electricity Linear relationship is kept to fold into low frequency to avoid the high-frequency noise of charge pump circuit between stream.Furthermore it is applied to frequency synthesizer When, interfering frequency synthesizer does not work.

Detailed description of the invention

Figure 1A is a configuration diagram of the prior art.

Figure 1B is the waveform diagram of the output electric current of the current source of the prior art.

Fig. 1 C is the waveform diagram of the output electric current of the capacitor of the prior art.

Fig. 2 is a configuration diagram of one embodiment of charge pump circuit of the invention.

Fig. 3 A is the waveform diagram of one embodiment of frequency signal of Fig. 2.

Fig. 3 B is the waveform diagram of one embodiment of switching signal of Fig. 2.

Fig. 3 C is the waveform diagram of one embodiment of by-passing signal of Fig. 2.

Fig. 3 D is the waveform diagram of one embodiment of phase shift pulse wave signal of Fig. 2.

Fig. 3 E is the waveform diagram of one embodiment of output voltage of the first current source cell of Fig. 2.

Fig. 3 F is the waveform diagram of one embodiment of output voltage of the output capacitance of Fig. 2.

Fig. 3 G is the waveform diagram of output one embodiment of electric current of the first current source cell of Fig. 2.

Fig. 3 H is the waveform diagram of output one embodiment of electric current of the output capacitance of Fig. 2.

Fig. 4 is the configuration diagram of another embodiment of charge pump circuit of the invention.

Wherein appended drawing reference are as follows:

10 output capacitance, 20 first current source cell

30 second current source cell, 40 charge switch

50 discharge switch, 60 by-pass switch

61 by-pass switch, 62 amplifier

70 phase frequency detection circuit, 80 phase-shift type wide pulse width power transformation road

90 logical operation circuit, 900 charge pump

901 capacitor SS-U, SS-D, S-switch switching signals

SB-U, SB-D, S-bypass by-passing signal

Section is connected in t11, t21, t22

T12, t23, t24 disconnect interval

S-clk frequency signal

S-div frequency elimination signal

S-shift phase shift pulse wave signal

Vi1, Vcout output voltage

Ii1, Icout export electric current

Specific embodiment

Fig. 2 is a configuration diagram of one embodiment of charge pump circuit of the invention.Referring to Fig. 2, charge pump circuit packet Contain: output capacitance 10, the first current source cell 20, the second current source cell 30, charge switch 40, discharge switch 50 and bypass Switch 60.Charge switch 40 is coupled between the first current source cell 20 and output capacitance 10.Discharge switch 50 is coupled to second Between current source cell 30 and output capacitance 10.By-pass switch 60 is coupled between the first current source cell 20 and ground terminal.The One current source cell 20 couples charge switch 40 and by-pass switch 60.Second current source cell 30 is coupled to discharge switch 50 and connects Between ground terminal.

In an embodiment, the first current source cell 20 is coupled to a voltage rating relative to the another end of charge switch 40 Circuit (it provides a voltage rating).That is, the first current source cell 20 input terminal coupling voltage rating circuit and Receive the voltage rating that voltage rating circuit is supplied.The output end of first current source cell 20 is coupled to the of charge switch 40 One end and the first end for being coupled to by-pass switch 60.The second end of charge switch 40 is coupled to output capacitance 10.First electric current Source unit 20 to according to voltage rating provide fixed value charging current, and this charging current can via charge switch 40 and It charges to output capacitance 10.Wherein, voltage rating is a fixed value.

In an embodiment, the second current source cell 30 is coupled to ground terminal relative to the another end of discharge switch 50.? That is the first end of the input terminal coupling discharge switch 50 of the second current source cell 30.The output of second current source cell 30 End is coupled to ground terminal.The second end of discharge switch 50 is coupled to output capacitance 10.When discharge switch 50 is connected, output capacitance 10 can be discharged with the discharge current of fixed value via discharge switch 50 and the second current source cell 30.In this, charge switch 40 will not simultaneously turn on discharge switch 50.

Wherein, charging current and the current value of discharge current can be identical, can also be difference, but the electric current of charging current Value and the current value of discharge current are not limitation in the present invention.

In an embodiment, there is a conducting section to break with one by switching signal SS-U or SS-D (hereinafter referred to as S-switch) Open interval.

The control terminal of charge switch 40 receives switching signal SS-U, and charge switch 40 according to switching signal SS-U in leading Logical section t11 is conducting, so that charging current charges to output capacitance 10 via charge switch 40.In other words, charge switch 40 It is to be not turned in disconnect interval t12 responding to switch signal SS-U.

The control terminal of discharge switch 50 receives switching signal SS-D, and discharge switch 50 according to switching signal SS-D in leading Logical section is conducting, and then puts output capacitance 10 with the load current value (discharge current) of the second current source cell 30 Electricity.In other words, discharge switch 50 is to be not turned in disconnect interval responding to switch signal SS-U.

In an embodiment, switching signal S-switch maintains the time of high potential as conducting section, and switchs letter The time that number S-switch maintains low potential is disconnect interval.In other words, the control terminal of charge switch 40 receives high electricity When the switching signal SS-U of position, charge switch 40 can be switched to conducting, and charge switch 40 is maintained in switching signal SS-U (i.e. conducting section) can maintain on state during high potential.When charge switch 40 is conducting, the first current source cell 20 The charging current of output can flow through charge switch 40, then pass to output capacitance 10 to charge to output capacitance 10.

Similarly, when the control terminal of discharge switch 50 receives the switching signal SS-D of high potential, discharge switch 50 can be cut It is changed to conducting, and discharge switch 50 (i.e. conducting section) during switching signal SS-D maintains high potential can maintain to be connected State.When discharge switch 50 is conducting, output capacitance 10 couples the second current source cell 30 via discharge switch 50, and passes through Ground terminal is coupled to by discharge switch 50 and the second current source cell 30, to show the load current value of the second current source cell 30 (discharge current) discharges.

In some embodiments, charge switch 40 and discharge switch 50 can be respectively NMOS, PMOS, CMOS, transistor Deng switching switch block, the present invention is non-as limitation.

For example, if charge switch 40 be MOS switching switch block, and charge switch 40 have grid, source electrode with Drain electrode.Source electrode is to be connected to voltage rating circuit, to receive voltage rating.Drain electrode is to be connected to charge switch 40.Grid is then Switching signal S-switch is received, and can make to form conducting between source electrode and drain electrode according to switching signal S-switch or not lead It is logical.

In an embodiment, by-passing signal S-bypass (SB-D or SB-U) has a conducting section and a disconnect interval.

In an embodiment, the control terminal of by-pass switch 60 receives a by-passing signal SB-D, and 60 basis of by-pass switch By-passing signal SB-D and be connected or be not turned on.In other words, by-pass switch 60 responds bypass in the conducting section of by-passing signal SB-D Signal SB-D is conducting, and it is not lead that by-pass switch 60, which responds by-passing signal SB-U in the disconnect interval of by-passing signal SB-D, It is logical.When by-pass switch 60 is conducting, the charging current that the first current source cell 20 is mentioned can be flow to via by-pass switch 60 to be connect Ground terminal.

In this, according to switching signal before charge switch 40 is according to switching signal SS-U conducting and in charge switch 40 SS-U is switched to from conducting be not turned on after, by-pass switch 60 according to by-passing signal SB-D be conducting.Also, in charge switch 40 According to during switching signal SS-U conducting, by-pass switch 60 is to be not turned on according to by-passing signal SB-U.In other words, switching signal SS-U Conducting section occur before and after, the conducting section of a given time can occur respectively for by-passing signal SB-D.And switching signal SS- While the conducting section of U occurs, the disconnect interval of by-passing signal SB-D occurs.So it is avoided that charge pump circuit in the first electricity Voltage generated is accumulated because of charging current between stream source unit 20 and charge switch 40.And it also can be reduced through by-pass switch 60 electric currents thrown aside can also make to keep linear relationship to avoid charge pump electricity between phase and output electric current to save electric current The high-frequency noise on road folds into low frequency.

In some embodiments, charge pump circuit can further include an another by-pass switch 61.The coupling of by-pass switch 61 is put Electric switch 50 and the second current source cell 30.By-pass switch 61 is connected or is not turned on according to by-passing signal SB-D.It is other in this Way switch 60 will not be simultaneously turned on by-pass switch 61.

In this, according to switching signal before discharge switch 50 is according to switching signal SS-D conducting and in discharge switch 50 SS-D is switched to from conducting be not turned on after, by-pass switch 61 according to by-passing signal SB-U be conducting.Also, in discharge switch 50 According to during switching signal SS-D conducting, by-pass switch 61 is to be not turned on according to by-passing signal SB-D.It can so allow charge pump circuit Voltage will not be accumulated between the second current source cell 30 and discharge switch 50.And it can make to keep between phase and output electric current Linear relationship can more be generated from the problem of high-frequency noise folding.

In some embodiments, by-pass switch 60,61 can switch switching group for NMOS, PMOS, CMOS, transistor etc. Part, the present invention are non-as limitation.Fig. 3 A is the waveform diagram of mono- embodiment of switching signal S-switch of Fig. 2.It please refers to Fig. 3 A, switching signal S-switch include conducting section t11 and disconnect interval t12.In this, switching signal S-switch is being connected Section t11 is high potential, during switching signal S-switch as shown in Figure 3A is about 1 volt (V).Also, switching signal S-switch is low potential in disconnect interval t12, during switching signal S-switch as shown in Figure 3B is about 0V.

Fig. 3 B is the waveform diagram of mono- embodiment of by-passing signal S-bypass of Fig. 2.Refering to Fig. 3 B, by-passing signal S- Bypass includes comprising conducting section t21, t22 and disconnect interval t23, t24.In this, by-passing signal S-bypass is in conducting area Between t21, t22 be high potential, during by-passing signal S-bypass as shown in Figure 3B is about 1 volt (V).Also, it bypasses Signal S-bypass is low potential in disconnect interval t23, t24, and by-passing signal S-bypass as shown in Figure 3 C is about 0V Period.

Fig. 3 A and 3B are please referred to, in the conducting section t11 of switching signal S-switch, switching signal S-switch driving is filled The process of electric switch 40 (or discharge switch 50) conducting, by-passing signal S-bypass driving by-pass switch 60 (or 61) are not turned on (i.e. by-passing signal S-bypass is disconnect interval t23).That is, switching signal S-switch will enter conducting section t11 A preceding preset time (time span of t21), by-passing signal S-bypass can first be pulled to high potential and (enter conducting section t21).And when switching signal S-switch enters conducting section t11 instantly, by-passing signal S-bypass can be pulled to low electricity moment Position (the time point of interface of t21 and t23).And by-passing signal S-bypass is located at the time span (disconnect interval of this low potential T23) it is approximately equal to the time span of the conducting section t11 of switching signal S-switch.In addition, the conducting of switching signal S-switch When section t11 terminates and will enter disconnect interval t12 (the time point of interface of t23 and t12), by-passing signal S-bypass again can wink Between be pulled to high potential (enter conducting section t22) and retracted down again after maintaining a preset time (time span of t22) in low electricity Position (the time point of interface of t22 and t24).In other words, conducting section t21, the disconnect interval t23 of by-passing signal S-bypass with lead Logical section t22 sequentially occurs, and the conducting area of the disconnect interval t23 and switching signal S-switch of by-passing signal S-bypass Between t11 it is generally synchronous.

In other words, the conducting section t11 of switching signal S-switch is as voltage is the time interval of 1V in Fig. 3 A.And While this time section (conducting section t11), the by-passing signal S-bypass in Fig. 3 B is to be located at low potential (to disconnect area Between t23).At this point, charge switch 40 (or discharge switch 50) is connected, and by-pass switch 60 (or 61) is not turned on.And believe in switch In the front and back preset time of the conducting section t11 of number S-switch, i.e., in the time that the voltage of switching signal S-switch is 1V In the preset time of the front and back in section, by-passing signal S-bypass is allowed to be to be located at high potential (conducting section t21, t22).At this point, Charge switch 40 (or discharge switch 50) is not turned on, but by-pass switch 60 (or 61) be connected, with allow whereby current source cell (20 or 30) voltage between charge and discharge switch (charge switch 40 or discharge switch 50) is able to flow to ground terminal.It can so allow and fill Discharge switch makes to reach steady state voltage between current source cell and charge and discharge switch in advance before conducting.It is further able to avoid High voltage when moment is connected in charge switch 40 is flowed to output capacitance 10.It can so make to keep line between phase and output electric current Sexual intercourse can more be generated from the problem of high-frequency noise folding.Wherein, the time span of preset time is not in the present invention Limitation.In addition, preset time of the by-passing signal S-bypass in the front and back of the conducting section t11 of switching signal S-switch can be with For identical (i.e. the time span of conducting section t21 is identical to conducting section t22), (it can also be connected section t21's to be different Time span is different from conducting section t22), visual demand adjustment.

In an embodiment, please referring back to Fig. 2, when charge pump circuit is applied to frequency synthesizer, charge pump circuit Further it is coupled with phase frequency detection circuit 70, phase-shift type wide pulse width power transformation road 80 and logical operation circuit 90.Phase frequency The input terminal of output end couples logic computing circuit 90, the control terminal of charge switch 40 and the discharge switch 50 of rate detection circuit 70 Control terminal.The input terminal on phase-shift type wide pulse width power transformation road 80 receives frequency signal S-clk.Phase-shift type wide pulse width power transformation road The input terminal of 80 output end couples logic computing circuit 90.The output end of logical operation circuit 90 is coupled to by-pass switch 60 Control terminal (control terminal with by-pass switch 61).

Phase frequency detection circuit 70 receives frequency signal S-clk and frequency elimination signal S-div, and according to frequency signal S- Clk and frequency elimination signal S-div output switching signal SS-U (or SS-D).Phase-shift type wide pulse width power transformation road 80 receives frequency signal S-clk, and phase-shifted and wide pulse width change are carried out to frequency signal S-clk and generate phase shift pulse wave signal S-shift.It patrols Volume computing circuit 90 according to switching signal SS-U (or SS-D) and phase shift pulse wave signal S-shift generate by-passing signal SB-U (or SB-D)。

In an embodiment, logical operation circuit 90 includes mutual exclusion or door.The input terminal of mutual exclusion or door is respectively coupled to phase Bit frequency detection circuit 70 and phase-shift type wide pulse width power transformation road 80, and switching signal S-switch and phase shift arteries and veins are received respectively Wave signal S-shift.The output end of mutual exclusion or door couples the control terminal (control terminal with by-pass switch 61) of by-pass switch 60, and And output by-passing signal S-bypass.That is, having electricity between switching signal S-switch and phase shift pulse wave signal S-shift When position is different, the by-passing signal S-bypass of mutual exclusion or door output is low potential.Switching signal S-switch and phase shift pulse wave are believed Between number S-shift when same potential, the by-passing signal S-bypass of mutual exclusion or door output is then high potential.It can so get out of the way In conducting section driving 40 turn on process of charge switch of OFF signal S-switch, by-pass switch 60 is caused to be not turned on.

For example, when charge pump circuit uses two by-pass switch 60,61, logical operation circuit 90 is using two mutual exclusions Or door generates by-passing signal SB-U, SB-D.In other words, one of mutual exclusion or door person receive switching signal SS-U and phase shift pulse wave Signal S-shift simultaneously exports by-passing signal SB-U, and the other of mutual exclusion or door then receive switching signal SS-D and phase shift arteries and veins Wave signal S-shift simultaneously exports by-passing signal SB-D.

In some embodiments, frequency signal S-clk is to generate (not shown) by oscillating circuit.Wherein, frequency elimination signal S-div is can to generate (not shown) by frequency eliminating circuit.

Fig. 3 C is the waveform diagram of mono- embodiment of frequency signal S-clk of Fig. 2.Please refer to Fig. 3 C, phase frequency detection Circuit 70 can carry out the phase-detection of frequency elimination signal S-div using frequency signal S-clk as reference signal, and in frequency elimination signal S- Corresponding switching signal SS-U or SS-D is generated when div and frequency signal S-clk asynchronous.In this embodiment, frequency signal S-clk has about 50% responsibility cycle.

Referring to Fig. 3 A to 3C, when phase frequency detection circuit 70 detects the advanced frequency elimination signal S-div of frequency signal S-clk When, phase frequency detection circuit 70 can export the switching signal SS-U (conducting section t11) of high potential until frequency signal S-clk It is synchronous with frequency elimination signal S-div, without output switching signal SS-D (or the switching signal SS-D for maintaining low potential).At this point, Switching signal S-switch shown in Fig. 3 A is representation switch signal SS-U, and by-passing signal S-bypass shown in Fig. 3 B is Represent by-passing signal SB-U.

When phase frequency detection circuit 70 detects the advanced frequency signal S-clk of frequency elimination signal S-div, phase frequency inspection Slowdown monitoring circuit 70 can export the switching signal SS-D (conducting section t11) of high potential until frequency signal S-clk and frequency elimination signal S- Div is synchronous, without output switching signal SS-U (or the switching signal SS-U for maintaining low potential).At this point, being opened shown in Fig. 3 A OFF signal S-switch is representation switch signal SS-D, and by-passing signal S-bypass shown in Fig. 3 B is to represent by-passing signal SB-D。

When phase frequency detection circuit 70 detects that frequency signal S-clk is synchronous with frequency elimination signal S-div, phase frequency Then not output switching signal SS-U, SS-D (or switching signal SS-U, SS-U for being kept at low potential) of detection circuit 70.This When, by-passing signal SB-U, SB-D are also kept at low potential.

Fig. 3 D is the waveform diagram of mono- embodiment of phase shift pulse wave signal S-shift of Fig. 2.In an embodiment, it please return For head refering to Fig. 3 A to 3D, phase-shift type wide pulse width power transformation road 80 is a phase difference and a pulse wave of displacement frequency signal S-clk Wide difference is to export phase shift pulse wave signal S-shift.In this, the time that phase shift pulse wave signal S-shift is located at high potential is to cover The time of the conducting section t11 of switching signal S-switch.That is, maintaining high electricity in phase shift pulse wave signal S-shift During position, there is the conducting section t11 of switching signal S-switch.Also, the conducting area of switching signal S-switch Between t11 be less than during phase shift pulse wave signal S-shift maintains high potential.

In an embodiment, the period of phase shift pulse wave signal S-shift is equal to the period of by-passing signal S-bypass, and moves The time span that phase pulse wave signal S-shift is located at high potential be substantially equal to by-passing signal S-bypass conducting section t21, Time span of the time span of t22 plus the conducting section t11 of switching signal S-switch.

In this, the time span (preset time) of conducting section t21, t22 of by-passing signal S-bypass can be by adjustment Phase shift pulse wave signal S-shift be located at high potential time point and time span and determine.Wherein, phase shift pulse wave signal S- The time span that shift is located at high potential is not limitation, visual demand tune etc. in the present invention.

Fig. 3 E is the waveform diagram of mono- embodiment of output voltage Vi1 of the first current source cell 20 of Fig. 2.Fig. 3 F is figure The waveform diagram of mono- embodiment of output voltage Vcout of 2 output capacitance 10.Fig. 3 G is the first current source cell 20 of Fig. 2 Output mono- embodiment of electric current Ii1 waveform diagram.Fig. 3 H is that the output electric current Icout mono- of the output capacitance 10 of Fig. 2 is implemented The waveform diagram of example.Please refer to Fig. 3 A to Fig. 3 H, via by-passing signal S-bypass driving by-pass switch 60 conducting with not Conducting, can allow charging current not accumulate voltage between the first current source cell 20 and charge switch 40.And phase can be made The problem of keeping linear relationship between output electric current, capable of folding from high-frequency noise generates.

In an embodiment, charge pump circuit can not use amplifier, at this point, the second end of by-pass switch 60 is coupled to and connects Ground terminal.Therefore, when by-pass switch 60 is connected, charging current provided by the first current source cell 20 can be via by-pass switch 60 It flow to ground terminal.In addition, the first end of by-pass switch 61 couples discharge switch when charge pump circuit is provided with by-pass switch 61 50 and second current source cell 30, and the second end of by-pass switch 61 couples voltage rating circuit.

In an embodiment, amplifier is can be used in charge pump circuit.Fig. 4 is another embodiment of charge pump circuit of the invention Configuration diagram.Referring to Fig. 4, charge pump circuit can further include amplifier 62.The input terminal and charge switch of amplifier 62 40 second end and output capacitance 10 coupling.The second end of the output end coupling by-pass switch 60 of amplifier 62 is (with another bypass The second end of switch 61).That is, the second end of another by-pass switch 61 be coupled to simultaneously the second end of by-pass switch 60 with The output end of amplifier 62.The first end of by-pass switch 61 is then coupled to the second current source cell 30 and the first of discharge switch 50 End.So can also allow by-pass switch 61 is conducting during the front and back that discharge switch 50 is connected, and is connected in discharge switch 50 It is to be not turned in journey.In addition, by-pass switch 61 is to be not turned on during charge switch 40 is connected.

According to the various embodiments described above, charge pump circuit is closed in when not in use, then in charge and discharge switch (charge switch 40 Or discharge switch 50) to switch to conducting before and charge and discharge switch to switch to before being not turned on, by-pass switch is first connected 60 (or 61) switch by-pass switch 60 (or 61) again after so that the drain electrode of current source cell (20 or 30) is reached steady state voltage be not lead It is logical, and carry out the switching of charge and discharge switch.The steady state voltage between current source cell and charge and discharge switch can so be maintained.It can also It avoids accumulating voltage generated because of charging current between the first current source cell 20 and charge switch 40.And it also can be reduced The electric current thrown aside through by-pass switch 60 (or 61) is to save electric current.In addition can also make to keep linear pass between phase and output electric current System folds into low frequency to avoid the high-frequency noise of charge pump circuit.Furthermore when being applied to frequency synthesizer, interfering frequency is not closed It grows up to be a useful person work.

Claims

1. A charge pump circuit with low current and low noise, characterized in that, comprising:

an output capacitor;

a first current source unit, providing a charging current according to a rated voltage;

a second current source unit, coupled between the output capacitor and the ground;

A charging switch, coupled between the output capacitor and the first current source unit, is controlled by a switch signal, wherein the charging switch receives the switch signal and conducts in a conduction interval of the switch signal to make the switch signal The charging current charges the output capacitor;

A discharge switch, coupled between the output capacitor and the second current source unit, is controlled by the switch signal, wherein the discharge switch receives the switch signal and conducts in an off interval of the switch signal to make the switch signal output capacitor discharge; and

a bypass switch, coupled between the first current source unit and the ground terminal, controlled by a bypass signal;

Wherein, before and after the switch signal controls the charging switch to be turned on in the conduction interval, the bypass signal controls the bypass switch to be turned on so that the charging current flows to the ground terminal; and

Wherein, during the period when the switch signal controls the charging switch to be turned on in the conduction interval, the bypass signal controls the bypass switch to be turned off.

2 . The charge pump circuit with low current and low noise as claimed in claim 1 , further comprising another bypass switch, and the other bypass switch is coupled to the discharge switch and the second current source unit. 3 .

3. The low current and low noise charge pump circuit as claimed in claim 2, further comprising an amplifier, the input end of the amplifier is coupled to the output capacitor, and the output end of the amplifier is coupled to the bypass switch and the other bypass switch.

4 . The charge pump circuit with low current and low noise as claimed in claim 1 , wherein the switching signal is generated based on a frequency signal and a frequency dividing signal, and the bypass signal is generated based on the switching signal and a phase-shifting pulse 4 . There is a phase difference and a pulse width difference between the phase-shifted pulse signal and the frequency signal.

5 . The charge pump circuit with low current and low noise as claimed in claim 4 , wherein the time when the phase-shifted pulse signal is at a high level covers the conduction interval of the switch signal. 6 .

6 . The charge pump circuit with low current and low noise as claimed in claim 5 , wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the phase-shifted pulse signal is located at the high potential. 7 . The time is equal to the sum of the time that the bypass signal is at a high level and the time of the conduction interval of the switch signal.

7 . The charge pump circuit with low current and low noise as claimed in claim 6 , further comprising a logic operation circuit, the logic operation circuit is coupled to the bypass switch, and the logic operation circuit receives the phase-shifted pulse wave. 8 . The bypass signal is generated from the signal and the switch signal according to the switch signal and the phase-shifted pulse signal.

8 . The charge pump circuit with low current and low noise as claimed in claim 7 , wherein the logic operation circuit comprises a mutually exclusive OR gate, and an input end of the mutually exclusive OR gate receives the switching signal and the phase-shift pulse. 9 . wave signal, the output terminal of the mutually exclusive OR gate outputs the bypass signal.

9. A frequency synthesizer, characterized in that, comprising:

The charge pump circuit with low current and low noise as claimed in any one of claims 1 to 3;

a phase frequency detection circuit, coupled to the charging switch and the discharging switch, and outputting the switching signal according to a frequency signal and a frequency dividing signal;

a phase-shifted pulse width modulation circuit that outputs a phase-shifted pulse signal according to the frequency signal, wherein the time when the phase-shifted pulse signal is at a high level covers the conduction interval of the switch signal; and

A logic operation circuit is coupled between the phase frequency detection circuit, the phase shift circuit and the bypass switch, and the logic operation circuit generates the bypass signal according to the switch signal and the phase shift pulse signal.

10 . The frequency synthesizer of claim 9 , wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the time that the phase-shifted pulse signal is at the high level is equal to the bypass signal. 11 . The sum of the time the signal is at a high level and the time of the conduction interval of the switch signal.