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CN109427649B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109427649B
CN109427649B CN201710734652.1A CN201710734652A CN109427649B CN 109427649 B CN109427649 B CN 109427649B CN 201710734652 A CN201710734652 A CN 201710734652A CN 109427649 B CN109427649 B CN 109427649B
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opening
forming
dielectric layer
mask
interconnect
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CN109427649A (en
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袁可方
王梓
周俊卿
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein a first dielectric layer is arranged on the substrate, and a first opening is formed in the first dielectric layer; forming a first interconnection and a third opening on the first interconnection within the first opening; forming a second interconnect within the third opening, the second interconnect material having a reducibility that is less than a reducibility of the first interconnect material; forming a second dielectric layer on the first dielectric layer and the second interconnect; and removing part of the second dielectric layer, and forming a second opening in the second dielectric layer, wherein the bottom of the second opening is exposed out of the second interconnection part. The method can improve the controllability of the second opening morphology.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor technology has advanced, semiconductor devices have been provided with deep sub-micron structures, containing a vast number of semiconductor elements in a semiconductor integrated circuit IC. In such a large scale integrated circuit, not only a single-layer interconnect structure but also a multilayer interconnect structure is protected. Wherein the multilayer interconnection structures are stacked on each other and are isolated by dielectric layers between the multilayer interconnection structures. In particular, when a multi-level interconnect structure is formed using a dual-damascene (dual-damascene) process, it is necessary to form trenches and vias for interconnects in a dielectric layer in advance and then fill the trenches and vias with a conductive material such as copper.
The dual damascene process can be divided into two types according to the difference of the sequential implementation modes of the process: trench First (trench First) and Via First (Via First) processes. The groove first process comprises the following steps: firstly, etching a groove pattern on a deposited dielectric layer, and then etching a through hole pattern; the through hole first process comprises the following steps: firstly, etching a through hole pattern on the dielectric layer, and then etching a groove pattern.
However, the contact resistance of the semiconductor device formed by the prior art is large.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to reduce the contact resistance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a first dielectric layer is arranged on the substrate, and a first opening is formed in the first dielectric layer; forming a first interconnection and a third opening on the first interconnection within the first opening; forming a second interconnect within the third opening, the second interconnect material having a reducibility that is less than a reducibility of the first interconnect material; forming a second dielectric layer on the first dielectric layer and the second interconnect; and removing part of the second dielectric layer, and forming a second opening in the second dielectric layer, wherein the bottom of the second opening is exposed out of the second interconnection part.
Optionally, the forming of the first interconnect, the third opening, and the second interconnect includes: forming a first interconnection film in the first opening and on the first dielectric layer, wherein a third opening is formed in the first dielectric layer on the first interconnection film; forming a second interconnect film on the first interconnect film, a portion of the second interconnect film filling the third opening; the second interconnect film and the first interconnect film are planarized until a top surface of the first dielectric layer is exposed.
Optionally, the process for forming the first interconnect film includes: electroplating; before forming the first interconnect film, the method further includes: and forming a first seed crystal layer in the first opening and on the first dielectric layer.
Optionally, the depth of the third opening is: 50 to 150 nanometers; the distance from the bottom of the third opening to the top of the first medium layer is as follows: 10 to 100 angstroms.
Optionally, the material of the first interconnect includes: copper.
Optionally, the material of the second interconnect includes: gold, silver, platinum-cobalt alloys, cobalt or tungsten.
Optionally, the thickness of the second interconnect is: 10 to 100 angstroms.
Optionally, the first opening comprises: the first through hole is communicated with the first groove; before forming the first opening, the forming method further includes: forming a first mask layer on the first dielectric layer, wherein the first mask layer is internally provided with a first mask opening; and forming a second mask layer in the first mask opening and on the first mask layer, wherein the second mask layer is internally provided with a second mask opening, the size of the second mask opening in the direction parallel to the surface of the substrate is smaller than that of the first mask opening, and the projection of the second mask opening on the substrate is at least partially overlapped with the projection of the first mask opening on the substrate.
Optionally, the step of forming the first via hole and the first trench includes: etching the part of the first dielectric layer by taking the second mask layer as a mask, and forming a first initial through hole in the first dielectric layer; after the first initial through hole is formed, removing the second mask layer; and after the second mask layer is removed, etching a part of the first dielectric layer around the top of the first initial through hole by taking the first mask layer as a mask, forming the first groove in the first dielectric layer, etching the first dielectric layer at the bottom of the first initial through hole, and forming the first through hole in the first dielectric layer.
Optionally, the second opening comprises: the second through hole is communicated with the second groove; before forming the second opening, the forming method further includes: forming a third mask layer on the second dielectric layer, wherein the third mask layer is provided with a third mask opening; and forming a fourth mask layer in the third mask opening and on the third mask layer, wherein the fourth mask layer is internally provided with a fourth mask opening, the size of the fourth mask opening in the direction parallel to the surface of the substrate is smaller than that of the third mask opening, and the projection of the fourth mask opening on the substrate is at least partially overlapped with the projection of the third mask opening on the substrate.
Optionally, the step of forming the second via hole and the second trench includes: etching the part of the second dielectric layer by taking the fourth mask layer as a mask, and forming a second initial through hole in the second dielectric layer; after the second initial through hole is formed, removing the fourth mask layer; and after the fourth mask layer is removed, etching a second groove of a part of the second dielectric layer around the top of the second initial through hole in the second dielectric layer by taking the third mask layer as a mask, etching the second dielectric layer at the bottom of the second initial through hole, and forming a second through hole in the second dielectric layer.
Optionally, the process of etching the second dielectric layer around the top of the second initial through hole and the second dielectric layer at the bottom of the second initial through hole by using the third mask layer as a mask includes: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: the etching gas includes fluorocarbon gas, hydrogen gas, oxygen gas, and nitrogen gas.
Optionally, after forming the second opening, the forming method further includes: and forming a second interconnection structure in the second opening.
The present invention also provides a semiconductor structure, comprising: the semiconductor device comprises a substrate, a first dielectric layer and a second dielectric layer, wherein the substrate is provided with a first dielectric layer which is internally provided with a first opening; a first interconnect within the first opening and a third opening on the first interconnect; a second interconnect located within the third opening; and the second dielectric layer is positioned on the first dielectric layer and the second interconnection part, a second opening is formed in the second dielectric layer, and the bottom of the second opening is exposed out of the second interconnection part.
Optionally, the material of the first interconnect includes: copper.
Optionally, the material of the second interconnect includes: gold, silver, platinum-cobalt alloys, cobalt or tungsten.
Optionally, the depth of the third opening is: 50 to 150 nanometers; the distance from the bottom of the third opening to the top of the first medium layer is as follows: 10 to 100 angstroms.
Optionally, the thickness of the second interconnect is: 10 to 100 angstroms.
Optionally, the semiconductor structure further includes a second interconnect structure located within the second opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, the first interconnection and the third opening positioned on the first interconnection are formed in the first opening, and the third opening is used for accommodating the second interconnection. And forming a second opening in the second dielectric layer on the second interconnection part, wherein the second interconnection part covers part of the top surface of the first interconnection part, so that the second interconnection part protects part of the top of the first interconnection part. In addition, the reducibility of the second interconnection material is weaker than that of the first interconnection material, so that the bonding capability of the oxygen-containing gas and the second interconnection is weaker in the process of forming the second opening, and the loss of the oxygen-containing gas is reduced, thereby being beneficial to improving the efficiency of forming the second opening and improving the controllability of the appearance of the second opening.
Further, the process for etching the second dielectric layer at the bottom of the second initial through hole by using the third mask layer as a mask comprises the following steps: an anisotropic dry etching process in which the etching gas comprises oxygen. Since the second interconnect material is weak in reducing property, the second interconnect has weak bonding ability with oxygen, so that the content of oxygen is high. The etching gas further comprises a fluorocarbon gas, which is prone to generate a polymer during the anisotropic dry etching process, and oxygen is capable of consuming the polymer. When the content of oxygen is higher, the consumption of the polymer formed on the side wall of the second through hole is faster, the included angle between the side wall and the bottom of the formed second through hole is closer to a right angle, the difference between the size of the bottom and the size of the top of the formed second through hole is smaller, and the size of the bottom of the second through hole is larger. The second through hole is used for subsequently accommodating a second interconnection structure, so that the contact area between the second interconnection structure and the second interconnection part is larger, and the reduction of the contact resistance between the second interconnection structure and the second interconnection part is facilitated.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background art, the contact resistance of the semiconductor device is large.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 has a first dielectric layer 101 thereon; forming a first opening (not shown) in the first dielectric layer 101; forming a first interconnect structure 102 within the first opening; forming a stop layer 103 on the first dielectric layer 101 and the first interconnect structure 102; forming a second dielectric layer 104 on the stop layer 103, wherein the second dielectric layer 104 has a first mask layer 105 thereon, and the first mask layer 105 has a first mask opening (not shown); the second mask layer 140 is provided in the first mask opening and on the first mask layer 105, the second mask opening 150 is provided in the second mask layer 140, the dimension of the second mask opening 150 along the direction parallel to the surface of the substrate 100 is smaller than that of the first mask opening, and the projection of the second mask opening 150 on the substrate 100 is at least partially overlapped with the projection of the first mask opening on the substrate 100.
Referring to fig. 2, the second mask layer 140 is used as a mask to etch the portion of the second dielectric layer 104, and an initial through hole 106 is formed in the second dielectric layer 104; after the initial via 106 is formed, the second mask layer 140 is removed.
Referring to fig. 3, after removing the second mask layer 140, etching a portion of the second dielectric layer 104 around the top of the initial through hole 106 by using the first mask layer 105 as a mask, forming a trench 108 in the second dielectric layer 104, and etching the second dielectric layer 104 and the stop layer 103 at the bottom of the initial through hole 106 until the top surface of the first interconnection structure 102 is exposed, forming a through hole 107 in the second dielectric layer 104 and the stop layer 103, wherein the through hole 107 is communicated with the trench 108.
In the above method, the via 107 and the trench 108 are subsequently used to accommodate a second interconnect structure, which is used to make an electrical connection with the first interconnect structure 102. The step of forming the via hole 107 includes: forming the initial via 106; the second dielectric layer 104 and the stop layer 103 at the bottom of the initial via 106 are removed.
The process for removing the second dielectric layer 104 and the stop layer 103 at the bottom of the initial via hole 106 includes: the anisotropic dry etching process comprises the following parameters: the etching gas includes a fluorocarbon gas and an oxygen gas. During the anisotropic dry etching process, the fluorocarbon gas is liable to react to form a polymer, and oxygen can consume the polymer.
However, during the anisotropic dry etching process, a portion of the first interconnect structure 102 is exposed. Since the material of the first interconnect structure 102 includes: copper. Copper has strong reducibility, so that copper is easy to react with oxygen, the content of oxygen is reduced, the capability of oxygen for consuming polymers is reduced, and the thickness of polymers generated by the reaction of fluorocarbon gas is thick. The polymer covers the side wall of the through hole 107, and the polymer can block the second dielectric layer 104 on the side wall of the through hole 107 from being etched, so that the bottom size of the formed through hole 107 is smaller than the top size, that is: the through holes 107 have poor topography controllability. And a second interconnection structure is formed in the through hole 107 subsequently, and the contact resistance between the second interconnection structure in the through hole 107 and the first interconnection structure 102 is larger due to the smaller bottom size of the through hole 107, which is not beneficial to improving the performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: the first dielectric layer is internally provided with a first opening; forming a first interconnection and a third opening on the first interconnection within the first opening; forming a second interconnection within the third opening, the second interconnection having a reducibility that is weaker than that of the first interconnection; and forming a second opening in the second dielectric layer on the second interconnection part, wherein the bottom of the second opening is exposed out of the second interconnection part. The method can improve the controllability of the second opening morphology.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, wherein the substrate 200 has a first dielectric layer 201 thereon.
In this embodiment, the base 200 is a silicon substrate. In other embodiments, the base may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator, a germanium-on-insulator, or a silicon germanium-on-insulator.
In other embodiments, the substrate has semiconductor devices, such as MOS transistors, therein.
In this embodiment, the first dielectric layer 201 has a single-layer structure, and the first dielectric layer 201 is made of a low-K dielectric material. The low-K dielectric material refers to a dielectric material with a relative dielectric constant less than 3.9. The low-K dielectric material is a porous material.
In this embodiment, the first dielectric layer 201 is made of fluorine-doped silicon dioxide (FSG).
In other embodiments, the first dielectric layer is a single-layer structure, and the material of the first dielectric layer includes: SiCOH, boron doped silicon dioxide (BSG), phosphorous doped silicon dioxide (PSG), boron phosphorous doped silicon dioxide (BPSG); or, the first dielectric layer is a laminated structure, and the first dielectric layer includes: a stop layer on the top surface of the substrate and a low-K dielectric layer on the stop layer.
And forming a first interconnection structure in the first dielectric layer 201 subsequently, wherein the first dielectric layer 201 is made of a low-K dielectric material, and the low-K dielectric material can reduce capacitance between the first interconnection structures, reduce time constants of the first interconnection structures in the interconnection structures, and reduce delay of circuit signals.
Before forming the first interconnection structure, the method further comprises: a first opening is formed in the first dielectric layer 201.
In this embodiment, taking the first opening as a dual damascene opening as an exemplary illustration, the dual damascene opening includes: a via and a trench located over the via. Please refer to fig. 4 specifically.
Referring to fig. 5, a portion of the first dielectric layer 201 is removed, and a first opening 202 is formed in the first dielectric layer 201.
In this embodiment, the first opening 202 is a dual damascene opening.
In other embodiments, the first opening comprises: a single damascene opening.
In this embodiment, the first opening 202 includes: a first via (not shown) in the first dielectric layer 201 and a first trench (not shown) on the first via.
Before forming the first opening 202, the method further includes: forming a first mask layer (not shown) on the first dielectric layer 201, wherein the first mask layer has a first mask opening therein; a second mask layer (not shown) is formed in and on the first mask opening, the second mask layer has a second mask opening (not shown), the dimension of the second mask opening in the direction parallel to the surface of the substrate 200 is smaller than that of the first mask opening, and the projection of the second mask opening on the substrate 200 at least partially overlaps the projection of the first mask opening on the substrate 200.
The material of the first mask layer comprises: silicon oxide, silicon nitride, photoresist or metal materials, wherein the metal materials include: TiN, TaN, WN.
The dimension of the first mask opening in a direction parallel to the surface of the substrate 200 is used to define the dimension of a subsequently formed first trench.
The material of the second mask layer comprises: silicon oxide, silicon nitride, photoresist or metal materials, wherein the metal materials include: TiN, TaN, WN.
The dimension of the second mask opening in a direction parallel to the surface of the substrate 200 is used to define the dimension of the subsequently formed first via.
The forming step of the first opening 202 includes: etching the part of the first dielectric layer 201 by taking the second mask layer as a mask, and forming a first initial through hole in the first dielectric layer 201; after the first initial through hole is formed, removing the second mask layer; after removing the second mask layer, etching a part of the first dielectric layer 201 around the top of the first initial through hole by using the first mask layer as a mask, forming a first groove in the first dielectric layer 201, etching the first dielectric layer 201 at the bottom of the first initial through hole, and forming the first through hole in the first dielectric layer 201.
The process for etching the part of the first dielectric layer 201 by using the second mask layer as a mask comprises the following steps: and (3) an anisotropic dry etching process.
The process for etching the first dielectric layer 201 at the periphery of the top of the first initial through hole and the first dielectric layer 201 at the bottom of the first initial through hole by using the first mask layer as a mask comprises the following steps: and (3) an anisotropic dry etching process.
After the first opening 202 is formed, the method further includes: forming a first interconnect structure within the first opening 202, the first interconnect structure comprising: a first interconnect on the sidewall and bottom surface of the first opening 202 and a second interconnect on a portion of the first interconnect, as shown in fig. 6-8.
Referring to fig. 6, a first interconnection film 250 is formed in the first opening 202 (see fig. 5) and on the first dielectric layer 201, and the first interconnection film 250 has a third opening 230 in the first dielectric layer 201.
In this embodiment, before forming the first interconnect film 250, the method further includes: a first seed layer is formed within the first opening 202 (see fig. 5) and on the first dielectric layer 201.
The first seed layer serves as a nucleus for the first interconnection film 250 and as an electrode for subsequently forming the first interconnection film 250 using an electroplating process.
The material of the first interconnection film 250 is metal, and in this embodiment, the material of the first interconnection film 250 is copper. In other embodiments, the material of the first interconnect film includes: aluminum.
The formation process of the first interconnect film 250 includes: electroplating or electrochemical plating processes.
The first seed layer covers the sidewall and the bottom of the first opening 202, and the first interconnection film 250 is formed along the crystal orientation direction of the first seed layer by an electroplating process. The first interconnect film 250 does not fill the first opening 202, and the third opening 230 is formed on the first interconnect film.
The depth of the third opening 230 is: 50 to 150 nanometers. The third opening 230 is used to subsequently accommodate a second interconnect membrane.
The first interconnect film 250 is used for the subsequent formation of a first interconnect.
Referring to fig. 7, a second interconnection film 260 is formed on the first interconnection film 250, and a portion of the second interconnection film 260 fills the third opening 230 (see fig. 6), and the reducibility of the second interconnection film 260 is weaker than that of the first interconnection film 250.
In the present embodiment, the material of the second interconnect film 260 is platinum-cobalt alloy. In other embodiments, the material of the second interconnect film includes: gold, silver, platinum, cobalt or tungsten.
The formation process of the second interconnect film 260 includes: electroplating or electrochemical plating processes.
The thickness of the second interconnect film 260 is: 10 to 100 angstroms.
The second interconnect film 260 is used for the subsequent formation of a second interconnect. The thickness of the second interconnect film 260 determines the thickness of a subsequently formed second interconnect.
Referring to fig. 8, the second interconnect film 260 and the first interconnect film 250 are planarized until the top surface of the first dielectric layer 203 is exposed, and a first interconnect 203a and a second interconnect 203b on a portion of the first interconnect 203a are formed in the first opening 202 (see fig. 4).
The process of planarizing the second and first interconnection films 260 and 250 includes: and (5) carrying out a chemical mechanical polishing process.
The first interconnect structure 203 includes: a first interconnect 203a and a second interconnect 203b on a portion of the first interconnect 203 a.
Since the first interconnect 250 is used to form the first interconnect 203a, the second interconnect film 260 is used to form the second interconnect 203b, and the reducibility of the second interconnect film 260 is weaker than that of the first interconnect film 250, the reducibility of the second interconnect 203b is weaker than that of the first interconnect 203 a.
A second via is subsequently formed in the second dielectric layer on the second interconnect 203b, where the bottom of the second via exposes the second interconnect 203 b. Since the second via hole is small in size in the direction parallel to the surface of the substrate 200, although the second interconnect 203b covers only a part of the first interconnect 203a, the second interconnect 203b is sufficient to cover the first interconnect 203a at the bottom of the second via hole. In the process of forming the second through hole, since the reducibility of the second interconnection portion 203b is weak, the bonding capability of the oxygen-containing gas and the second interconnection portion 203b is weak, and the loss of the oxygen-containing gas can be reduced, which is beneficial to improving the efficiency of forming the second through hole and improving the controllability of the morphology of the second through hole.
The thickness of the second interconnect 203b is: 10 to 100 angstroms, the thickness of the second interconnect 203b is selected in the sense that: if the thickness of the second interconnection portion 203b is less than 10 angstroms, so that the protection strength of the second interconnection portion 203b on the first interconnection portion 203a is insufficient, during the subsequent formation of the second through hole, the amount of the oxygen-containing gas consumed by the first interconnection portion 203a in the process of forming the second through hole is large and cannot be quantified, so that the amount of the oxygen-containing gas used for forming the second through hole cannot be quantified, and the controllability of the morphology of the formed second through hole is poor; if the thickness of the second interconnect 203b is greater than 100 angstroms, the depth of the third opening 230 for accommodating the second interconnect 203b is greater, and the difficulty in forming the third opening 230 is greater.
Referring to fig. 9, a stop layer 205 and a second dielectric layer 206 on the stop layer 205 are formed on the first dielectric layer 201 and the second interconnect 203 b.
The stop layer 205 is used as an etch stop layer for the subsequent formation of the second opening.
In this embodiment, the material of the stop layer 205 is silicon nitride. In other embodiments, the material of the stop layer comprises: AlN, SiCN or SiCO.
The material and the forming method of the second dielectric layer 206 are the same as those of the first dielectric layer 201, and are not described herein again.
After forming the second dielectric layer 206, the method further includes: a second opening is formed in the second dielectric layer 206.
In this embodiment, taking the second opening as a dual damascene opening as an exemplary illustration, the second opening includes: please refer to fig. 10 to 12 for details of the second via and the second trench on the second via.
Referring to fig. 10, a third mask layer 207 is formed on the second dielectric layer 206, wherein the third mask layer 207 has a third mask opening (not shown); a fourth mask layer 270 is formed in the third mask opening and on the third mask layer 207, a fourth mask opening 280 is formed in the fourth mask layer 270, and a projection of the fourth mask opening 280 on the substrate 200 is at least partially overlapped with a projection of the third mask opening on the substrate 200.
The material of the third mask layer 207 includes: silicon oxide, silicon nitride, photoresist or metal materials, wherein the metal materials include: TiN, TaN, WN.
The dimension of the third mask opening in a direction parallel to the surface of the substrate 200 is used to define the dimension of the subsequently formed second trench.
The material of the fourth mask layer 270 includes: silicon oxide, silicon nitride, photoresist or metal materials, wherein the metal materials include: TiN, TaN, WN.
The dimension of the fourth mask opening 280 in a direction parallel to the surface of the substrate 200 is used to define the dimension of a subsequently formed second via.
Referring to fig. 11, the fourth mask layer 270 is used as a mask to etch the portion of the second dielectric layer 206, and a second initial through hole 204 is formed in the second dielectric layer 206; after the second initial via 204 is formed, the fourth mask layer 270 is removed, exposing the top of the third mask layer 207, and the sidewalls and bottom surfaces of the third mask opening.
The forming process of the second initial through hole 204 comprises the following steps: and (3) an anisotropic dry etching process.
The second initial via 204 is used for subsequent formation of a second via.
The process for removing the fourth mask layer comprises the following steps: one or both of a dry etching process and a wet etching process.
Referring to fig. 12, after removing the fourth mask layer 280, the third mask layer 207 is used as a mask to etch a portion of the second dielectric layer 206 around the top of the second initial via 204, form a second trench 209 in the second dielectric layer 206, and etch the second dielectric layer 206 and the stop layer 205 at the bottom of the second initial via 204, so as to form a second via 208 in the second dielectric layer 206 and the stop layer 205.
The process for etching the second dielectric layer 206 around the top of the second initial via hole 204, and the second dielectric layer 206 and the stop layer 205 at the bottom of the second initial via hole 204 by using the third mask layer 207 as a mask includes: the anisotropic dry etching process comprises the following parameters: the etching gas includes fluorocarbon gas, hydrogen gas, oxygen gas, and nitrogen gas.
In the anisotropic dry etching process, the reducibility of the material of the second interconnect 203b is lower than that of the material of the first interconnect 203a, so that the bonding capability of the second interconnect 203b with oxygen is lower, and the loss of oxygen is reduced, thereby facilitating the improvement of the efficiency of forming the second via 208 and the improvement of the topography controllability of the second via 208.
Also, during the anisotropic dry etching process, fluorocarbon gas is liable to react to generate polymer, and oxygen can consume the polymer. When the oxygen content is higher, the polymer thickness formed on the sidewall of the second via is consumed faster, and the included angle between the sidewall and the bottom of the second via 208 is formed to be more vertical. The difference between the bottom dimension and the top dimension of the second via hole is smaller, so that the bottom dimension of the second via hole 208 is larger. And a second interconnection structure is formed in the second through hole, and the contact resistance between the second interconnection structure and the first interconnection structure 203 is small, so that the performance of the semiconductor device is improved.
Referring to fig. 13, after the second via hole 208 and the second trench 209 are formed, the third mask layer 207 is removed; after removing the third mask layer 207, a second interconnect structure 210 is formed within the second via 208 (see fig. 11) and the second trench 209 (see fig. 11).
The step of forming the second interconnect structure 210 includes: forming a metal layer on the second dielectric layer 206, the second through hole 208 and the second trench 209; the metal layer is planarized until the top surface of the second dielectric layer 206 is exposed, and a second interconnect structure 210 is formed in the second trench 209 and the second via 208.
The metal layer is made of metal. In this embodiment, the metal layer is made of copper. Accordingly, the material of the second interconnect structure 210 is copper. In other embodiments, the material of the metal layer includes: aluminum, and accordingly, the material of the second interconnect structure includes: aluminum.
The forming process of the metal layer comprises the following steps: electroplating or electrochemical plating processes.
The process for planarizing the metal layer includes: and (5) carrying out a chemical mechanical polishing process.
The bottom of the second via 208 has a larger size, so that the contact resistance between the second interconnect structure 210 located in the second via 208 and the first interconnect structure 203 is smaller, which is beneficial to improving the performance of the semiconductor device.
Accordingly, the present embodiment further provides a semiconductor structure formed by the method, with reference to fig. 12, including:
a substrate 200, wherein the substrate 200 has a first dielectric layer 201 thereon, and the first dielectric layer 201 has a first opening 202 therein (see fig. 5);
a first interconnect 203a located within the first opening 202 and a third opening 230 (see fig. 6) located on the first interconnect 203 a;
a second interconnection 203b located within a portion of the third opening 230;
and a second dielectric layer 206 on the first dielectric layer 201 and the second interconnect 203b, wherein the second dielectric layer 206 has a second opening therein, and the bottom of the second opening exposes the top surface of the second interconnect 203 b.
The material of the first interconnect 203a includes: copper.
The material of the second interconnect 203b includes: platinum cobalt alloy, cobalt or tungsten.
The depth of the third opening 230 is: 50 to 150 nanometers.
The thickness of the second interconnect 203b is: 1000 to 3000 angstroms.
The semiconductor structure further includes: a second interconnect structure 210 located within the second opening.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a first dielectric layer is arranged on the substrate, and a first opening is formed in the first dielectric layer;
forming a first interconnection and a third opening on the first interconnection within the first opening;
forming a second interconnect within the third opening, the second interconnect material having a reducibility that is less than a reducibility of the first interconnect material;
forming a second dielectric layer on the first dielectric layer and the second interconnect;
and removing part of the second dielectric layer, and forming a second opening in the second dielectric layer, wherein the bottom of the second opening is exposed out of the second interconnection part.
2. The method of forming a semiconductor structure of claim 1, wherein the forming of the first interconnect, the third opening, and the second interconnect comprises: forming a first interconnection film in the first opening and on the first dielectric layer, wherein a third opening is formed in the first dielectric layer on the first interconnection film; forming a second interconnect film on the first interconnect film, a portion of the second interconnect film filling the third opening; the second interconnect film and the first interconnect film are planarized until a top surface of the first dielectric layer is exposed.
3. The method of forming a semiconductor structure according to claim 2, wherein the process of forming the first interconnect film comprises: electroplating; before forming the first interconnect film, the method further includes: and forming a first seed crystal layer in the first opening and on the first dielectric layer.
4. The method of forming a semiconductor structure of claim 1, wherein a depth of the third opening is: 50 to 150 nanometers; the distance from the bottom of the third opening to the top of the first medium layer is as follows: 10 to 100 angstroms.
5. The method of forming a semiconductor structure of claim 1, wherein a material of the first interconnect comprises: copper.
6. The method of forming a semiconductor structure of claim 1, wherein a material of the second interconnect comprises: gold, silver, platinum-cobalt alloys, cobalt or tungsten.
7. The method of forming a semiconductor structure of claim 1, wherein a thickness of the second interconnect is: 10 to 100 angstroms.
8. The method of forming a semiconductor structure of claim 1, wherein the first opening comprises: the first through hole is communicated with the first groove; before forming the first opening, the forming method further includes: forming a first mask layer on the first dielectric layer, wherein the first mask layer is internally provided with a first mask opening; and forming a second mask layer in the first mask opening and on the first mask layer, wherein the second mask layer is internally provided with a second mask opening, the size of the second mask opening in the direction parallel to the surface of the substrate is smaller than that of the first mask opening, and the projection of the second mask opening on the substrate is at least partially overlapped with the projection of the first mask opening on the substrate.
9. The method of forming a semiconductor structure of claim 8, wherein the step of forming the first via and the first trench comprises: etching part of the first dielectric layer by taking the second mask layer as a mask, and forming a first initial through hole in the first dielectric layer; after the first initial through hole is formed, removing the second mask layer; and after the second mask layer is removed, etching a part of the first dielectric layer around the top of the first initial through hole by taking the first mask layer as a mask, forming the first groove in the first dielectric layer, etching the first dielectric layer at the bottom of the first initial through hole, and forming the first through hole in the first dielectric layer.
10. The method of forming a semiconductor structure of claim 1, wherein the second opening comprises: the second through hole is communicated with the second groove; before forming the second opening, the forming method further includes: forming a third mask layer on the second dielectric layer, wherein a third mask opening is formed in the third mask layer; and forming a fourth mask layer in the third mask opening and on the third mask layer, wherein the fourth mask layer is internally provided with a fourth mask opening, the size of the fourth mask opening in the direction parallel to the surface of the substrate is smaller than that of the third mask opening, and the projection of the fourth mask opening on the substrate is at least partially overlapped with the projection of the third mask opening on the substrate.
11. The method of forming a semiconductor structure of claim 10, wherein the step of forming the second via and the second trench comprises: etching the part of the second dielectric layer by taking the fourth mask layer as a mask, and forming a second initial through hole in the second dielectric layer; after the second initial through hole is formed, removing the fourth mask layer; and after the fourth mask layer is removed, etching a part of the second dielectric layer around the top of the second initial through hole by taking the third mask layer as a mask, forming a second groove in the second dielectric layer, etching the second dielectric layer at the bottom of the second initial through hole, and forming a second through hole in the second dielectric layer.
12. The method for forming a semiconductor structure according to claim 11, wherein the etching of the second dielectric layer around the top of the second initial via hole and the etching of the second dielectric layer at the bottom of the second initial via hole with the third mask layer as a mask comprises: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: the etching gas includes fluorocarbon gas, hydrogen gas, oxygen gas, and nitrogen gas.
13. The method of forming a semiconductor structure of claim 1, wherein after forming the second opening, the method further comprises: and forming a second interconnection structure in the second opening.
14. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a first dielectric layer and a second dielectric layer, wherein the substrate is provided with a first dielectric layer which is internally provided with a first opening;
a first interconnect within the first opening and a third opening on the first interconnect;
a second interconnect located within the third opening;
the second dielectric layer is positioned on the first dielectric layer and the second interconnection part, a second opening is formed in the second dielectric layer, and the bottom of the second opening is exposed out of the second interconnection part;
the second interconnect material has a reducibility that is less than the reducibility of the first interconnect material.
15. The semiconductor structure of claim 14, wherein a material of the first interconnect comprises: copper.
16. The semiconductor structure of claim 14, wherein a material of the second interconnect comprises: gold, silver, platinum-cobalt alloys, cobalt or tungsten.
17. The semiconductor structure of claim 14, wherein a depth of the third opening is: 50 to 150 nanometers; the distance from the bottom of the third opening to the top of the first medium layer is as follows: 10 to 100 angstroms.
18. The semiconductor structure of claim 14, wherein a thickness of the second interconnect is: 10 to 100 angstroms.
19. The semiconductor structure of claim 14, further comprising a second interconnect structure located within a second opening.
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