CN113097127B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN113097127B CN113097127B CN202010022609.4A CN202010022609A CN113097127B CN 113097127 B CN113097127 B CN 113097127B CN 202010022609 A CN202010022609 A CN 202010022609A CN 113097127 B CN113097127 B CN 113097127B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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Abstract
A method for forming a semiconductor structure comprises the steps of providing a semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, forming a plurality of discrete first metal layers in the first dielectric layer, forming a second dielectric layer on the first dielectric layer adjacent to the first metal layers, oxidizing the first metal layers to form metal oxide layers, forming a third dielectric layer on the surfaces of the second dielectric layer and the metal oxide layers, and etching the third dielectric layer until the metal oxide layers are exposed to form through holes. The forming method provided by the invention can form the through hole in a self-aligned way, and the bottom size of the through hole is limited and enlarged, so that the problem of short circuit is avoided.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure.
Background
As integrated circuits are being fabricated into ultra large scale integrated circuits (ULSI), the density of circuits therein is increasing, and the number of devices contained therein is increasing, such that the surface of the wafer does not provide enough area to fabricate the desired Interconnect. In order to meet the increased interconnect demands of the device after shrinking, the design of more than two layers of multi-layer metal interconnect lines realized by using through holes becomes a method necessary for the very large scale integrated circuit technology.
However, as the semiconductor process nodes continue to decrease, metal interconnect lines in semiconductor devices become denser and Critical Dimensions (CD) of the interconnect lines become smaller, a self-aligned via (SAV) process may be employed in forming the via in order to expand the photolithographic process window. However, when the existing self-aligned process forms the through hole, the problem of expansion of the through hole occurs, which causes bridging between the conductive plug and the adjacent metal wire of the connected lower metal wire after the conductive plug is formed by filling metal in the through hole, and short circuit phenomenon occurs.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can limit the expansion of a through hole and avoid the problem of short circuit between the through hole and a metal wire.
In order to solve the technical problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, forming a plurality of discrete first metal layers in the first dielectric layer, wherein the tops of the first metal layers are higher than the top surfaces of the first dielectric layers, forming a second dielectric layer on the first dielectric layers between adjacent first metal layers, oxidizing the first metal layers to form a metal oxide layer, forming a third dielectric layer on the surfaces of the second dielectric layer and the metal oxide layer, and etching the third dielectric layer until the metal oxide layer is exposed to form a through hole.
Optionally, the method for forming the second dielectric layer on the first dielectric layer includes an atomic layer deposition method or a chemical vapor deposition method.
Optionally, the material of the second dielectric layer includes aluminum oxide or aluminum nitride or boron nitride or tin dioxide or titanium dioxide.
Optionally, a cap layer is formed on the first dielectric layer, the first metal layer is located in the cap layer and the first dielectric layer, and the top of the first metal layer is flush with the top of the cap layer.
Optionally, before forming the second dielectric layer, etching to remove the cap layer.
Optionally, a self-assembled monolayer is also formed on the first metal layer prior to forming the second dielectric layer.
Alternatively, the method of forming the self-assembled monolayer is atomic layer deposition.
Optionally, the self-assembled monolayer is made of carbon-containing compound.
Optionally, the method for etching the third dielectric layer comprises the steps of forming a mask layer on the surface of the third dielectric layer, wherein the mask layer is provided with an opening, the opening exposes the third dielectric layer on the top of the metal oxide layer, and etching the third dielectric layer along the opening until the metal oxide layer is exposed.
Optionally, the material of the mask layer includes titanium nitride or boron nitride or aluminum nitride or tantalum nitride.
Optionally, the method for etching the third dielectric layer is dry etching, and the process parameters of the dry etching include CHF 3、C4F6、O2、Ar、C4F2 and H 2, wherein the flow rate of the CHF 3 gas is 10-300 sccm, the flow rate of the C 4F6 gas is 10-300 sccm, the flow rate of the O 2 gas is 0-100 sccm, the flow rate of the Ar gas is 50-500 sccm, the flow rate of the C 4F2 gas is 20-100 sccm, the flow rate of the H 2 gas is 0-100 sccm, the chamber pressure is 5-100 milliTorr, and the radio frequency power is 100-1000 Watts.
Optionally, the first dielectric layer material is a low-K dielectric material or an ultra-low K dielectric material, and the third dielectric layer material is a low-K dielectric material or an ultra-low K dielectric material.
Optionally, after the through hole is formed, the method further comprises removing the metal oxide layer at the bottom of the through hole to expose the surface of the first metal layer, and filling the through hole with a second metal layer to form a conductive plug connected with the first metal layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
Before forming the through hole by etching, forming a second dielectric layer on the first dielectric layer between the adjacent first metal layers, wherein when the through hole is formed by etching, the second dielectric layer can control the bottom size of the through hole, limit the expansion of the through hole and avoid short circuit between the through hole and the adjacent metal layers of the connected first metal layers.
Drawings
FIGS. 1 to 4 are schematic structural views of a method for forming a semiconductor structure according to an embodiment of the prior art;
fig. 5 to 12 are schematic structural views corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As known from the background art, the existing self-aligned via process can cause a problem of via expansion.
Fig. 1 to 4 are schematic structural views of a method for forming a semiconductor structure according to an embodiment of the prior art.
Referring to fig. 1, a semiconductor structure is provided, the semiconductor structure including a first interlayer dielectric layer 100, a capping layer 110 located on a surface of the first interlayer dielectric layer 100, and a first metal layer 120 located within the first interlayer dielectric layer 100 and the capping layer 110, a top of the first metal layer 120 being lower than a top surface of the first interlayer dielectric layer 100.
Referring to fig. 2, a barrier layer 121 and an etch stop layer 122 are sequentially formed on the surface of the first metal layer 120, and the barrier layer 121 and the etch stop layer 122 also cover the surface of the cover layer 110.
Referring to fig. 3, a second interlayer dielectric layer 130 is formed on the etching barrier layer 122, a patterned hard mask layer 140 is formed on the second interlayer dielectric layer 130, the second interlayer dielectric layer 130 is etched to the etching stop layer 122 by taking the patterned hard mask layer 140 as a mask, and then the etching stop layer 122 and the barrier layer 121 are continuously etched until the surface of the first metal layer 120 is exposed, so as to form a through hole 150.
Referring to fig. 4, the patterned hard mask layer 140 is removed, and a second metal layer 160 is formed in the via hole 150, and the second metal layer 160 is connected to the first metal layer 120.
The inventors found that, when the above method is used to form the via hole, if the opening of the patterned hard mask layer 140 is too large, the size of the via hole formed by etching is too large, and when the space between the metal layers is smaller, the bottom of the via hole is too large, bridging with the metal layer below is easy to occur, and the performance of the semiconductor structure is not good.
In order to solve the above problems, the inventors have studied and have provided a method for forming a semiconductor structure, in which a second dielectric layer is formed on the first dielectric layer between adjacent first metal layers, the second dielectric layer and a third dielectric layer to be etched subsequently have a high selectivity, and when the third dielectric layer is etched to form a through hole, the second dielectric layer has a positioning effect on both sides of the first metal layer, so that the through hole can be formed in a completely self-aligned manner, the size of the bottom of the through hole is limited, and the occurrence of a short circuit condition is avoided.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural views corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a semiconductor substrate (not shown) on which a first dielectric layer 200 is formed is provided.
The material of the first dielectric layer 200 is an ultra-low K dielectric material (ultra-low K dielectric material refers to a dielectric material having a relative dielectric material of less than 2.5) or a low K dielectric material (low K dielectric material refers to a dielectric material having a relative dielectric constant of 2.5 or more and less than 3.9). When the material of the first dielectric layer 200 is a low-K dielectric material or an ultra-low K dielectric material, the material of the first dielectric layer 200 is SiOH, siCOH, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), BPSG (boron doped phosphorus doped silicon dioxide), hydrosilsesquioxane (HSQ, (HSiO 1.5)n) or methylsilsesquioxane (MSQ, (CH 3SiO 1.5)n). In this embodiment, the material of the first dielectric layer 200 is an ultra-low K dielectric material, and the ultra-low K dielectric material is sicoh. The ultra-low K dielectric material is used as the dielectric layer, so that RC delay of the metal interconnection structure can be reduced.
With continued reference to fig. 5, a plurality of discrete first metal layers 300 are formed within the first dielectric layer 200, the top of the first metal layers 300 being higher than the top surface of the first dielectric layer 200.
In this embodiment, the method for forming the first metal layer 300 includes forming a plurality of trenches arranged in parallel in the first dielectric layer 200 by using photolithography and etching processes, and then filling the trenches with metal to form the first metal layer 300.
The material of the first metal layer 300 includes copper or cobalt, and in this embodiment, the material of the first metal layer 300 is copper.
Note that, before forming the first metal layer 300, a cap layer 210 is further formed on the first dielectric layer 200. The cap layer 210 and the first dielectric layer 200 are subsequently etched, the first metal layer 300 is formed in the cap layer 210 and the first dielectric layer 200, and the top of the first metal layer 300 is flush with the top of the cap layer 210.
In this embodiment, the material of the cap layer 210 is silicon carbide, and in other embodiments, the material of the cap layer 210 may also be an oxide layer with a higher K value, for example, an oxide with a relative dielectric constant of about 4.
After the first metal layer 300 is formed, a second dielectric layer is formed on the first dielectric layer 200 between adjacent first metal layers 300.
Referring to fig. 6, in this embodiment, the cap layer 210 is removed before the second dielectric layer 400 is formed. The reason for removing the cap layer 210 is that the insufficient compactness of the cap layer 210 may affect the time-dependent breakdown of the formed semiconductor structure, removing the cap layer 210, and subsequently reforming the second dielectric layer with better compactness at the position of the cap layer 210 may enhance the time-dependent breakdown of the semiconductor structure.
In this embodiment, the method for removing the cap layer 210 is a plasma etching process.
With continued reference to fig. 6, a self-assembled monolayer 310 is formed on the first metal layer 300 after removing the cap layer 210 and before forming the second dielectric layer.
In this embodiment, the self-assembled monolayer 310 is selectively deposited on the surface of the first metal layer 300, but not on the surface of the first dielectric layer 200, and then plays a role in protecting the first metal layer 300 when the second dielectric layer is formed on the first dielectric layer 200, so as to avoid damage to the first metal layer 300, thereby affecting the performance of the interconnection structure.
In this embodiment, the self-assembled monolayer 310 is formed by atomic layer deposition.
In this embodiment, the self-assembled monolayer 310 is made of a non-metal compound containing carbon.
Referring to fig. 7, a second dielectric layer 400 is formed on the first dielectric layer 200 between adjacent first metal layers 300.
In this embodiment, the method for forming the second dielectric layer 400 on the first dielectric layer 200 is an atomic layer deposition method. In other embodiments, the second dielectric layer may also be formed by chemical vapor deposition or plasma chemical vapor deposition.
In this embodiment, the second dielectric layer 400 is grown in a directional manner and is formed only on the surface of the first dielectric layer 200, but not on the surface of the self-assembled monolayer 310.
In this embodiment, the material of the second dielectric layer 400 is alumina, and the reason for selecting alumina is that alumina and a third dielectric layer formed subsequently have a higher etching selection ratio, and the alumina is not damaged when the third dielectric layer is etched to form a through hole, so that the size of the bottom of the through hole is ensured.
In other embodiments, the material of the second dielectric layer 400 may be aluminum nitride or boron nitride or tin dioxide or titanium dioxide.
In this embodiment, the top of the second dielectric layer 400 is higher than the top surface of the first metal layer 300.
In this embodiment, the second dielectric layer 400 is formed, on the one hand, the compactness of the formed second dielectric layer 400 is higher, so that the time breakdown of the semiconductor structure can be enhanced, and the performance of the semiconductor structure is improved, on the other hand, the second dielectric layer 400 is located between adjacent first metal layers 300, plays a positioning role in subsequent etching of the third dielectric layer, can form a through hole by self-aligned etching, and reduces the position deviation between the through hole and the first metal layer, on the other hand, the size of the bottom of the through hole is limited, and even if the etching process window is larger, the bottom size of the through hole formed by etching is fixed, so that bridging between the subsequent through hole and the first metal layer which does not need to be connected is avoided, and short circuit is generated.
Referring to fig. 8, after forming the second dielectric layer 400, the self-assembled monolayer 310 is removed.
In this embodiment, the self-assembled monolayer 310 is removed using an ashing process. The ashing process comprises the following process parameters that the adopted gas comprises oxygen, the gas flow of the oxygen is 50-1000 sccm, the chamber pressure is 0.5-5 Torr, and the source power is 500-3000 Watts.
With continued reference to fig. 8, after the self-assembled monolayer 310 is removed, the first metal layer 300 is subjected to an oxidation process, and a metal oxide layer 320 is formed on the surface of the first metal layer 300.
In this embodiment, the metal oxide layer 320 is used to protect the first metal layer 300 from being damaged when the third dielectric layer is etched to form the via hole, and can also be used as an etching stop layer.
In this embodiment, the metal oxide layer 320 is formed using an isotropic plasma oxidation process. The bonding force between the metal oxide layer and the metal matrix formed by the plasma oxidation process is strong, the compactness is better, and the performance of the semiconductor structure is improved.
The material of the metal oxide layer 320 depends on the material of the first metal layer 300. In this embodiment, the metal oxide layer 320 is copper oxide, and in other embodiments, the metal oxide layer 320 may be cobalt oxide.
Referring to fig. 9, a third dielectric layer 500 is formed on the surfaces of the second dielectric layer 400 and the metal oxide layer 320.
The third dielectric layer 500 is made of an ultra-low K dielectric material or a low K dielectric material. When the material of the third dielectric layer 500 is a low-K dielectric material or an ultra-low K dielectric material, the material of the third dielectric layer 500 is SiOH, siCOH, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), BPSG (boron doped phosphorus silicon dioxide), hydrosilsesquioxane (HSQ, (HSiO 1.5)n) or methylsilsesquioxane (MSQ, (CH 3SiO 1.5)n). In this embodiment, the material of the third dielectric layer 500 is an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH.
In this embodiment, the third dielectric layer 500 is etched later to form a via hole.
In this embodiment, the step of forming the through hole specifically includes:
with continued reference to fig. 9, a mask layer 510 is formed on the surface of the third dielectric layer 500, where the mask layer 510 has an opening 511, and the opening 511 exposes the third dielectric layer 500 on top of the metal oxide layer 320.
In this embodiment, the position corresponding to the opening 511 is a position where a through hole is formed subsequently, and the opening 511 exposes the third dielectric layer 500 corresponding to the position of the first metal layer 300.
In this embodiment, the method for forming the mask layer 510 is a chemical vapor deposition method, and in other embodiments, a physical vapor deposition method or an atomic layer deposition method may be used to form the mask layer 510.
In this embodiment, the material of the mask layer 510 is titanium nitride, and in other embodiments, the material of the mask layer 510 may be one or more of aluminum nitride, boron nitride, or tantalum nitride.
Referring to fig. 10, the third dielectric layer 500 is etched along the opening 511 until the metal oxide layer 320 is exposed, forming a via 600.
Since the second dielectric layer 400 and the third dielectric layer 500 have a high etching selectivity, the second dielectric layer 400 is not affected when the third dielectric layer 500 is etched, and therefore, the bottom dimension of the through hole 600 is limited by the adjacent second dielectric layers 400, and the bottom dimension of the through hole 600 is the distance between the adjacent second dielectric layers 400 (d in the figure). Due to the existence of the second dielectric layer 400, the bottom dimension of the through hole is fixed, so that the etching process window can be properly enlarged, and the bottom dimension of the through hole is not affected.
In this embodiment, the method of etching the third dielectric layer 500 is dry etching, and the process parameters of the dry etching include CHF 3、C4F6、O2、Ar、C4F2 and H 2, where the gas flow rate of CHF 3 is 10-300 sccm, the gas flow rate of C 4F6 is 10-300 sccm, the gas flow rate of O 2 is 0-100 sccm, the gas flow rate of Ar is 50-500 sccm, the gas flow rate of C 4F2 is 20-100 sccm, the gas flow rate of H 2 is 0-100 sccm, the chamber pressure is 5-100 mtorr, and the radio frequency power is 100-1000 watts.
Referring to fig. 11, after the via hole 600 is formed, the metal oxide layer 320 at the bottom of the via hole 600 is removed, exposing the surface of the first metal layer 300.
In this embodiment, the method for removing the metal oxide layer 320 is a wet etching process, and the process parameters of the wet etching process include that the etching solution used is a mixed solution of sulfuric acid and hydrogen peroxide.
In this embodiment, the metal oxide layer 320 at the bottom of the via hole 600 is removed to connect the second metal layer with the first metal layer 300 when the second metal layer is filled in the via hole 600 later.
In this embodiment, a wet etching process is also used to remove the mask layer 510.
Referring to fig. 12, after the metal oxide layer 320 is removed, the via hole 600 is filled with a second metal layer 610, so as to form a conductive plug connecting the first metal layer 300.
In this embodiment, the method for forming the conductive plug includes filling a second metal material layer in the via hole 600, where the second metal material layer covers the sidewall, the bottom and the surface of the third dielectric layer 500 of the via hole 600, and performing chemical mechanical polishing on the second metal material layer to make the top of the second metal material layer flush with the top surface of the third dielectric layer 500, so as to form the second metal layer 610, where the second metal layer 610 is in contact connection with the first metal layer 300.
In this embodiment, the second metal material layer is filled in the through hole 600 by electrochemical plating.
The material of the second metal layer 610 may be copper, cobalt, tungsten, or platinum. In this embodiment, the second metal layer 610 is copper.
In this embodiment, the second dielectric layer 400 is provided on both sides of the conductive plug, i.e. on both sides of the second metal layer 610, so that on one hand, the bottom dimension of the conductive plug is fixed, and on the other hand, the metal layer adjacent to the connected first metal layer of the conductive plug is isolated, thereby avoiding occurrence of short circuit and improving the performance reliability of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (12)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;
forming a plurality of discrete first metal layers in the first dielectric layer, wherein the top of the first metal layers is higher than the top surface of the first dielectric layer;
Forming a self-assembled monolayer on the first metal layer;
forming a second dielectric layer on the first dielectric layer between adjacent first metal layers, wherein the top of the second dielectric layer is higher than the top surface of the first metal layer;
removing the self-assembled monolayer;
oxidizing the first metal layer to form a metal oxide layer;
forming a third dielectric layer on the surfaces of the second dielectric layer and the metal oxide layer;
and etching the third dielectric layer until the metal oxide layer is exposed, and forming a through hole.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the second dielectric layer on the first dielectric layer comprises atomic layer deposition or chemical vapor deposition.
3. The method of claim 1, wherein the material of the second dielectric layer comprises aluminum oxide or aluminum nitride or boron nitride or tin dioxide or titanium dioxide.
4. The method of claim 1, further comprising forming a cap layer over the first dielectric layer, the first metal layer being located within the cap layer and the first dielectric layer, and a top of the first metal layer being level with a top of the cap layer.
5. The method of forming a semiconductor structure of claim 4, wherein said cap layer is etched away prior to forming said second dielectric layer.
6. The method of forming a semiconductor structure of claim 1, wherein the method of forming the self-assembled monolayer is atomic layer deposition.
7. The method of claim 1, wherein the self-assembled monolayer is formed of a carbon-containing compound.
8. The method of forming a semiconductor structure of claim 1, wherein the method of etching the third dielectric layer comprises:
Forming a mask layer on the surface of the third dielectric layer, wherein the mask layer is provided with an opening, and the opening exposes the third dielectric layer on the top of the metal oxide layer;
and etching the third dielectric layer along the opening until the metal oxide layer is exposed.
9. The method of claim 8, wherein the mask layer comprises titanium nitride or boron nitride or aluminum nitride or tantalum nitride.
10. The method of claim 1, wherein the third dielectric layer is etched by dry etching, and the process parameters of the dry etching include CHF 3、C4F6、O2、Ar、C4F2 and H 2, wherein the flow rate of CHF 3 is 10-300 sccm, the flow rate of C 4F6 is 10-300 sccm, the flow rate of O 2 is 0-100 sccm, the flow rate of Ar is 50-500 sccm, the flow rate of C 4F2 is 20-100 sccm, the flow rate of H 2 is 0-100 sccm, the chamber pressure is 5-100 millitorr, and the radio frequency power is 100-1000 Watts.
11. The method of claim 1, wherein the first dielectric layer material is a low-K dielectric material or an ultra-low K dielectric material, and the third dielectric layer material is a low-K dielectric material or an ultra-low K dielectric material.
12. The method of forming a semiconductor structure of claim 1, further comprising, after forming the via:
removing the metal oxide layer at the bottom of the through hole to expose the surface of the first metal layer;
and filling the through hole with a second metal layer to form a conductive plug connected with the first metal layer.
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| US6133139A (en) * | 1997-10-08 | 2000-10-17 | International Business Machines Corporation | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof |
| KR20100011799A (en) * | 2008-07-25 | 2010-02-03 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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| US9859208B1 (en) * | 2016-09-18 | 2018-01-02 | International Business Machines Corporation | Bottom self-aligned via |
| CN108281380A (en) * | 2018-01-25 | 2018-07-13 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of contact hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6133139A (en) * | 1997-10-08 | 2000-10-17 | International Business Machines Corporation | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof |
| KR20100011799A (en) * | 2008-07-25 | 2010-02-03 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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