CN109411373A - A method of realizing that multilager base plate is three-dimensional stacked using carrier supported - Google Patents
A method of realizing that multilager base plate is three-dimensional stacked using carrier supported Download PDFInfo
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- CN109411373A CN109411373A CN201811087383.5A CN201811087383A CN109411373A CN 109411373 A CN109411373 A CN 109411373A CN 201811087383 A CN201811087383 A CN 201811087383A CN 109411373 A CN109411373 A CN 109411373A
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- substrate
- carrier
- base plate
- multilager base
- dimensional stacked
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Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000003466 welding Methods 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 26
- 230000005611 electricity Effects 0.000 claims abstract description 9
- 238000013461 design Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 9
- 239000002356 single layer Substances 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 238000003475 lamination Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- -1 chip is installed Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81024—Applying flux to the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Realize that the three-dimensional stacked method of multilager base plate, this method use monolithic substrate as the carrier of circuit and component using carrier supported the invention discloses a kind of；According to radiating requirements and mechanical support demand selection position welding support carrier on substrate, support the material of carrier that need to be matched according to the macroscopic property of the substrate；Then solder is placed on surface on the support carrier, and solder thickness need to cooperate with the deformation quantity after BGA ball bond, is guaranteed while being realized reliable welding, can realize the welding with top substrate layer；By electric demand for interconnection, functional areas isolation requirement and the design BGA soldered ball arrangement of BGA Array Design rule constraint on substrate, BGA soldered ball interconnects as the dividing wall in circuit different function area, the electricity of realizing between laminar substrate up and down, the input and output of electric signal；The substrate that multilayer has above structure is stacked, then forms the three-dimensional stacked circuit of multilager base plate.
Description
Technical field
The invention belongs to the miniaturization integrated technology fields of electronic circuit and system, more particularly to one of which to use carrier
The three-dimensional stacked method of multilager base plate is realized in support.
Background technique
Realize that circuit is three-dimensionally integrated at present, the especially three-dimensionally integrated common method of microwave and millimeter wave circuit includes:
1, chip buried-in technology, which in chip buried-in such as substrate, will be laminated by single layer substrate, chip is installed, cavity is filled out
Fill (or being not filled with), the mode of substrate capping realizes chip buried-in, while secondary or repeatedly proceed as described above, realization chip three
Dimension layout and stacking, form system, and each layer is interconnected by plated-through hole；
The three-dimensional substrate Stack Technology they 2, BGA soldered balls support and be electrically interconnected, the technology support each laminar substrate, each layer using solder ball
Cloth circuits and chip on substrate, the support of BGA soldered ball, space needed for flowing out cloth circuits and chip between substrate uses simultaneously
BGA soldered ball realizes electricity interconnection；
3, it is supported using peripheral frame, the three-dimensional substrate Stack Technology that spun gold/gold ribbon interconnects up and down, which uses gold
Belong to peripheral frame support, is substrate arranged circuit and chip slot milling, realizes that the electricity of upper and lower level interconnects using spun gold/gold ribbon；
4, realize that the density three-dimensional of large scale integrated circuit stacks using TSV technology.
But above-mentioned integrated approach all have the defects that it is different, it is specific as follows:
The shortcomings that method 1, is technology complexity, high to temperature control requirement in the process, and the chip needs inside buried are especially set
Meter, and the thermally matched outstanding problem of chip and substrate；
The shortcomings that method 2 is to be difficult to realize multiple-level stack, and the soldered ball of each laminar substrate needs apparent temperature gradient, and present
Widely used solder is difficult to obtain three temperatures above gradients；
The shortcomings that method 3, is that the electricity interconnection of upper and lower level must be completed at the edge of circuit board, for the more electricity interconnected up and down
There is limitation in road；
There is limitation, and its complex process higher cost for the use of microwave and millimeter wave circuit in method 4, be suitable for extensive life
The circuit of production.
In view of many disadvantages existing for present method, present inventors have proposed a kind of stacked using substrate to realize simulation electricity
Road, digital circuit and microwave and millimeter wave circuit system three-dimensionally integrated packaged type.
Summary of the invention
The three-dimensional stacked method of multilager base plate, this method are realized using carrier supported the purpose of the present invention is to provide a kind of
The interlayer support that support carrier realizes multiple-level stack substrate can be used, support carrier to provide heat dissipation for the substrate of multiple-level stack and lead to
Road solves the problems, such as thermally matched, also improves the ability of the substrate shearing stress of multiple-level stack and provides enough for intervening devices
Space, solve the problems, such as temperature gradient, and can simply freely realize the interconnection of upper and lower circuit, breach significantly more
The technical matters of laminar substrate three stackings.
Technical scheme is as follows:
A method of realizing that multilager base plate is three-dimensional stacked using carrier supported, it is characterised in that: use monolithic substrate as electricity
The carrier on road and component；Carrier is supported according to radiating requirements and mechanical support demand selection position welding on the substrate,
The material of the support carrier need to be matched according to the macroscopic property of the substrate；Then surface is placed on the support carrier
Solder, solder thickness need to cooperate with the deformation quantity after BGA ball bond, guarantee to realize reliable welding simultaneously, can realize and
The welding of top substrate layer；By electric demand for interconnection, functional areas isolation requirement and the design of BGA Array Design rule constraint on the substrate
The arrangement of BGA soldered ball, BGA soldered ball interconnects as the dividing wall in circuit different function area, the electricity of realizing up and down between laminar substrate, electric signal
Input and output；The substrate that multilayer has above structure is stacked, then forms the three-dimensional stacked circuit of a multilager base plate.
The monolithic substrate as support carrier can be multilayer circuit board, such as 6 layers of ltcc substrate etc..
Various passive circuits, pad, welding resistance etc. can be made on the monolithic substrate.
The support carrier is metal or nonmetallic materials, such as molybdenum copper product need to be according to the thermodynamics of the substrate
Matter is matched.
The support carrier itself has good solderability, soldering resistance and weld strength, and solder energy by coating
Face is effectively adhered on the support carrier.
The support carrier should have similar thermal expansion coefficient with substrate.
The height of the support carrier should be higher than that the maximum height on substrate after device assembly.
The support carrier realizes its lower surface by being higher than the welding manner of 20 degrees Celsius of BGA soldered ball melt temperature or more
With the welding of substrate welding upper surface.
The support carrier should be lower than the height of BGA soldered ball plus the height of solder, and difference in height is soldered ball nature herein
Flow back the height collapsed, generally not lower than 0.1mm.
The solder that the support carrier upper surface is placed should have identical melt temperature with BGA soldered ball.
Support carrier height after the placement solder should be with BGA soldered ball height having the same.
The BGA soldered ball should be arranged on substrate after support carrier installation.
The component includes discrete component and bare chip；Further, shown component can use Surface Mount, glue
It connects, upside-down mounting, the modes such as Wire Banding are assembled.The component should be completed to assemble in multilager base plate heap prestack.
It can be real by the methods of laser alignment, infrared alignment or beam splitter optical alignment in the multilager base plate stacking process
Existing upper and lower level alignment.
The multilager base plate heap poststack need to apply the pressure of a direction bottom or by weight to guarantee that welding is reliable
Power supports carrier to guarantee the spacing of interlayer up and down in the welding process of lamination, and BGA soldered ball will not be collapsed, and guarantee soldered ball
And the welding of support carrier is comprehensive.
The multilager base plate, which is stacked, realizes the solder interconnections between each laminar substrate using solder reflow.
The present invention has the advantages that compared with the existing technology
1. the temperature gradient of solder needed for is few, and only there are two temperature, a high-temperature soldering solder realizes support carrier and base
The temperature of the welding of plate and a realization BGA ball bond；
2. the stacking of multilager base plate can be realized once, due to supporting the presence of carrier, do not have since the number of plies excessively leads to lower layer
The problem of soldered ball is collapsed；
3. simple process is mature, the technique of alignment between BGA solder ball technologies and substrate used in this method is highly developed and wide
General use；
4. the BGA soldered ball of smaller size according to actual needs, can be used, the high density interconnection of upper and lower level is realized；
5. by selecting suitable baseplate material, it can be achieved that with the preferable matched coefficients of thermal expansion of bare chip；
6. support carrier can realize good thermal conducting function, the material of high heat conductance is selected, the device of high radiating requirements is mounted on
, it can be achieved that good thermal conducting function below part；
7. supporting the contact area of carrier welding larger, it is possible to provide big shearing stress ability improves soldered ball point thermal cycle life.
8. support carrier can play a part of baffle, when applying pressure to substrate, the collapse height of ball is controlled.
Detailed description of the invention
Fig. 1 is that the present invention stacks the integrated circuit schematic diagram formed.
Fig. 2 is the top view that the present invention completes the single layer substrate that support carrier, BGA soldered ball, component are installed.
Fig. 3 is the single layer substrate lateral plan that the present invention completes that support carrier, BGA soldered ball, component are installed.
Fig. 4 is to realize the schematic diagram of interlayer welding in vacuum back-flow furnace after lamination of the present invention is installed.
Fig. 5 is process flow chart of the invention.
In the figure, it is marked as 1 is BGA soldered ball, 2 be substrate, and 2-1 is underlying substrate, and 2-2 is intermediate laminar substrate, and 2-3 is top layer
Substrate, 3 for support carrier, 4 be Surface Mount discrete component, and 5 be bare chip, and 6 be high-temperature soldering face, and 7 be solder, and 8 be counterweight, 9
For vacuum back-flow furnace.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
As shown in Figure 1, the three-dimensional substrate of multiple-level stack includes underlying substrate 2-1, centre laminar substrate 2-2 and top layer substrate 2-
3, they need to use Al2O3Multilayer ceramic substrate is interconnected using BGA soldered ball 1 between substrate, and support carrier 3 selects the processing of molybdenum copper product,
To guarantee good welding performance, gold-plated processing is done on surface, and support carrier 3 and underlying substrate 2-1, centre laminar substrate 2-2 pass through
280 DEG C of golden solderings are connected together, and BGA soldered ball 1 uses Sn96.5Ag3Cu0.5 soldered ball or Sn63Pb37 ball, while as propped up in Fig. 3
The placement of 4 upper surface of carrier and soldered ball are supportted with the solder sheet 7 of fusing point, BGA Diameter of Solder Ball is designed as 0.5mm, height after welding fabrication
Degree is about 0.4mm, and support carrier height is designed as 0.3mm, then design as in Fig. 3 solder sheet 7 with a thickness of 0.05 or
0.075mm。
As shown in Fig. 2, thereon may include discrete component 4 and bare chip 5, discrete member device for the circuit substrate of single layer
Part 4 need to be completed to weld and clean before bare chip is installed, and conducting resinl can be used to be pasted on corresponding position for bare chip 5, and use gold
The mode of silk bonding is connected with external circuit, and bare chip 5 cannot use the ultrasonic cleaning of single-frequency after installing, but vapour can be used
Mutually cleaning or the other pairs of undamaged modes of bare chip 5 are cleaned.
It is illustrated in figure 4 the signal for realizing interlayer welding after lamination installation in vacuum back-flow furnace 9, welding temperature at this time
It should control and be higher than 20 DEG C of fusion temperature or so, the general 20 ~ 200g of weight of counterweight 8 of solder ball, pressure be provided to stack, if substrate
It itself can provide enough power, counterweight 8 can also not used.
Be illustrated in figure 5 realize the embodiment simple process flow chart, the figure reflection each technical process it is successive
Sequentially, it due to the design of temperature gradient, supports carrier to use the golden tin welding mode of high temperature, should be initially completed, Surface Mount component
The temperature of welding is taken second place, therefore it is subsequently completed, and previous process steps may introduce scaling powder and other pollutions or fifth wheel, therefore
Ultrasonic wave or spray can be used thoroughly to be cleaned, bare chip, which is pasted, uses epoxy conducting, will not introduce pollution, solidification temperature
Degree control is being not higher than 140 DEG C, spun gold/gold ribbon bonding technology of bare chip in followed by each layer circuit, can after the completion of this step
Some verification tests are carried out, BGA is followed by and plants ball and lamination installation, the mainly fixation of the alignment between lamination and stacking, through true
After the welding of empty reflow ovens, scaling powder whether need to be added depending on stacking plant ball and determine whether to clean, if desired, then select vapour phase cleaning
Or the other pairs of undamaged modes of bare chip are cleaned, and the verification test of electrical property is finally carried out.
Claims (13)
1. a kind of realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: use monolithic substrate as
The carrier of circuit and component；It is carried on the substrate according to radiating requirements and the welding support of mechanical support demand selection position
The material of body, the support carrier need to be matched according to the macroscopic property of the substrate；Then surface on the support carrier
Solder is placed, solder thickness need to cooperate with the deformation quantity after BGA ball bond, guarantee while realizing reliable welding, can be real
Now with the welding of top substrate layer；By electric demand for interconnection, functional areas isolation requirement and BGA Array Design rule constraint on the substrate
Design the arrangement of BGA soldered ball, BGA soldered ball as circuit different function area dividing wall, realize the electricity interconnection between laminar substrate up and down, electric
The input and output of signal；The substrate that multilayer has above structure is stacked, then forms the three-dimensional stacked circuit of a multilager base plate.
2. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: make
Monolithic substrate to support carrier is single layer board or multilayer circuit board.
3. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: institute
Stating support carrier is metal or nonmetallic materials, need to be matched according to the macroscopic property of the substrate.
4. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: institute
It states support carrier and substrate has similar thermal expansion coefficient.
5. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: institute
The height of support carrier is stated higher than the maximum height after device assembly on substrate.
6. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: institute
It states support carrier and realizes that its lower surface and substrate are welded by being higher than the welding manner of 20 degrees Celsius of BGA soldered ball melt temperature or more
The welding of upper surface.
7. realizing that the three-dimensional stacked method of multilager base plate, feature exist using carrier supported according to claim 1 or 5
In: the height after the support carrier welding should melt the height after welding lower than BGA soldered ball, and the difference in height of formation is to support
Height after the welding of carrier top solder.
8. according to claim 7 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that: institute
Difference in height is stated not less than 0.1mm.
9. according to claim 1 or 6 realize that the three-dimensional stacked method of multilager base plate, feature exist using carrier supported
In: the solder that the support carrier upper surface is placed should have identical melt temperature with BGA soldered ball.
10. according to claim 9 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that:
Support carrier height after the placement solder should be with BGA soldered ball height having the same.
11. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that:
The BGA soldered ball should be arranged on substrate after support carrier installation.
12. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that:
The component includes discrete component and bare chip；Shown component is using Surface Mount, bonding, upside-down mounting or Wire Banding
Mode is assembled, and the component is completed to assemble in multilager base plate heap prestack.
13. according to claim 1 realize the three-dimensional stacked method of multilager base plate using carrier supported, it is characterised in that:
The multilager base plate, which is stacked, realizes the solder interconnections between each laminar substrate using solder reflow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811087383.5A CN109411373A (en) | 2018-09-18 | 2018-09-18 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811087383.5A CN109411373A (en) | 2018-09-18 | 2018-09-18 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109411373A true CN109411373A (en) | 2019-03-01 |
Family
ID=65464962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811087383.5A Pending CN109411373A (en) | 2018-09-18 | 2018-09-18 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
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| Country | Link |
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| CN (1) | CN109411373A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211884A (en) * | 2019-05-25 | 2019-09-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Density three-dimensional lamination autoregistration integrated encapsulation method |
| CN115206869A (en) * | 2022-07-14 | 2022-10-18 | 广州天极电子科技股份有限公司 | Method for pre-forming and assembling thin-film circuit board by gold and tin |
| US12334468B2 (en) * | 2022-10-04 | 2025-06-17 | Samsung Electronics Co., Ltd. | Solder reflow apparatus |
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| JPH0845982A (en) * | 1994-07-28 | 1996-02-16 | Nec Corp | Structure and method for mounting semiconductor device |
| US6014313A (en) * | 1996-12-19 | 2000-01-11 | Telefonaktiebolgey Lm Ericsson | Packaging structure for integrated circuits |
| US6680532B1 (en) * | 2002-10-07 | 2004-01-20 | Lsi Logic Corporation | Multi chip module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211884A (en) * | 2019-05-25 | 2019-09-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Density three-dimensional lamination autoregistration integrated encapsulation method |
| CN115206869A (en) * | 2022-07-14 | 2022-10-18 | 广州天极电子科技股份有限公司 | Method for pre-forming and assembling thin-film circuit board by gold and tin |
| US12334468B2 (en) * | 2022-10-04 | 2025-06-17 | Samsung Electronics Co., Ltd. | Solder reflow apparatus |
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