CN109390275B - Manufacturing method of polycrystalline silicon fuse structure - Google Patents
Manufacturing method of polycrystalline silicon fuse structure Download PDFInfo
- Publication number
- CN109390275B CN109390275B CN201811011462.8A CN201811011462A CN109390275B CN 109390275 B CN109390275 B CN 109390275B CN 201811011462 A CN201811011462 A CN 201811011462A CN 109390275 B CN109390275 B CN 109390275B
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- China
- Prior art keywords
- shallow trench
- isolation structure
- trench isolation
- groove
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a polycrystalline silicon fuse structure, which comprises the following steps: providing a substrate, and forming a shallow trench isolation trench on the upper surface of the substrate; forming a shallow trench isolation structure in the shallow trench isolation trench, wherein the top surface of the shallow trench isolation structure is higher than the upper surface of the substrate; forming a groove in the shallow groove isolation structure, wherein the depth, width and length of the groove are smaller than those of the shallow groove isolation structure; forming a programmable fuse on the upper surface of the shallow trench isolation structure and in the groove, wherein the programmable fuse comprises two first electrodes, two first vertical parts respectively connected with the two first electrodes and a first horizontal part connected with the two first vertical parts; depositing the isolation material in the recess forms a layer of isolation material covering at least the first horizontal portion.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a method for manufacturing a polysilicon fuse structure.
Background
The conventional method for forming the polysilicon fuse comprises the following steps: providing a substrate, wherein the substrate is provided with an isolation structure; thermally oxidizing a layer of silicon oxide on the surface of the substrate; depositing polysilicon on the surfaces of the silicon oxide and the isolation structure, and doping the polysilicon; and etching the polysilicon to form a fuse structure with two wide ends and a narrow middle part. The fuse structure formed by the method is firstly unfavorable for controlling the specific fusing position, and can cause fusing on a substrate, and the normal work of other devices on the substrate can be influenced due to overheating; and secondly, the fuse occupies larger surface area of the substrate, which is not beneficial to the integration of high-density devices, and the capacitance and inductance between a plurality of parallel fuses are larger, so that mutual crosstalk is easy.
Disclosure of Invention
Based on solving the above problems, the present invention provides a method for manufacturing a polysilicon fuse structure, comprising:
providing a substrate, and forming a shallow trench isolation trench on the upper surface of the substrate;
forming a shallow trench isolation structure in the shallow trench isolation trench, wherein the top surface of the shallow trench isolation structure is higher than the upper surface of the substrate;
forming a groove in the shallow groove isolation structure, wherein the depth, width and length of the groove are smaller than those of the shallow groove isolation structure;
forming a programmable fuse on the upper surface of the shallow trench isolation structure and in the groove, wherein the programmable fuse comprises two first electrodes, two first vertical parts respectively connected with the two first electrodes and a first horizontal part connected with the two first vertical parts; the two first electrodes are positioned at two ends of the upper surface of the shallow trench isolation structure, the two first vertical parts have a first length along the depth direction of the shallow trench isolation structure, and the first horizontal parts are covered by isolation materials of the shallow trench isolation structure and have a first depth in the shallow trench isolation structure;
depositing the isolation material in the recess forms a layer of isolation material covering at least the first horizontal portion.
According to an embodiment of the invention, forming the layer of isolation material comprises covering the first horizontal portion and a portion of the two first vertical portions.
According to an embodiment of the present invention, further comprising forming another programmable fuse on the isolation material layer, the another programmable fuse including two second electrodes, two second vertical portions respectively connected to the two second electrodes, and a second horizontal portion connected to the two second vertical portions; the two second electrodes are positioned at the other two ends of the upper surface of the shallow trench isolation structure, the two second vertical parts have a second length along the depth direction of the shallow trench isolation structure, and the second horizontal parts are covered by isolation materials of the shallow trench isolation structure and have a second depth in the shallow trench isolation structure.
According to an embodiment of the invention, the second horizontal portion and the first horizontal portion form a non-zero angle.
According to an embodiment of the invention, further comprising depositing the isolation structure in the recess to completely fill the recess.
According to an embodiment of the invention, the width of the two first electrodes is larger than the width of the first vertical portion and the first horizontal portion.
According to an embodiment of the invention, the width of the first vertical portion and the first horizontal portion are the same.
According to the embodiment of the invention, the isolation material of the shallow trench isolation structure is silicon oxide.
According to an embodiment of the present invention, the fuse structure is made of polysilicon.
According to the technical scheme, the fuse structure is arranged in the shallow trench isolation structure, so that the occupied area of the surface of the substrate is saved, and the isolation structure of the shallow trench isolation structure is used for isolating a plurality of fuse structures, so that the method is simple and easy to implement; in addition, a plurality of fuse structures have certain contained angle on the projection, can not be parallel, the interference is less to, utilize the thickness of the polycrystalline silicon of perpendicular part thinner, the great characteristic of resistance, control here carries out the electric fuse, realizes accurate control fusing position, avoids the high temperature influence to the substrate.
Drawings
FIG. 1 is a cross-sectional view of a programmable fuse structure of the present invention;
FIG. 2 is a top view of a programmable fuse structure of the present invention;
fig. 3-8 are flow diagrams illustrating a method of manufacturing a programmable fuse according to the present invention.
Detailed Description
Referring to fig. 1 and 2, the present invention provides a programmable fuse structure comprising: the substrate 1, in general, the substrate 1 is a silicon substrate, although other semiconductor substrates are possible; a shallow trench isolation structure 2 on the upper surface of the substrate 1, wherein the shallow trench isolation structure 2 is provided with an oxide isolation material, and the top surface of the shallow trench isolation structure 2 is higher than the upper surface of the substrate 1; a programmable fuse in the shallow trench isolation structure 2, wherein the fuse structure is a polysilicon fuse structure; the programmable fuse includes two first electrodes 3a and 4a, two first vertical portions 6a and 7a connected to the two first electrodes 3a and 4a, respectively, and a first horizontal portion 5a connected to the two first vertical portions 6a and 7 a; wherein two first electrodes 3a and 4a are located at two ends of the upper surface of the shallow trench isolation structure 2, two first vertical portions 6a and 7a have a first length along the depth direction of the shallow trench isolation structure 2, and the first horizontal portion 5a is covered with the isolation material of the shallow trench isolation structure and has a first depth in the shallow trench isolation structure 2.
Further comprising a further fuse structure comprising two second electrodes 3b and 4b, two second vertical portions 6b and 7b connecting the two second electrodes 3b and 4b, respectively, and a second horizontal portion 5b connecting the two second vertical portions 6b and 7 b; wherein two second electrodes 3b and 4b are located at the other two ends of the upper surface of the shallow trench isolation structure 2, two second vertical portions 6b and 7b have a second length along the depth direction of the shallow trench isolation structure 2, and the second horizontal portion 5b is covered with the isolation material of the shallow trench isolation structure 2 and has a second depth in the shallow trench isolation structure 2. The second depth is greater than the first depth, the second length is greater than the first length, and the second horizontal portion and the first horizontal portion form a non-zero included angle. The widths of the two first and second electrodes are greater than the widths of the first and second vertical portions and the first and second horizontal portions. The widths of the first and second vertical portions and the first and second horizontal portions are the same.
According to an embodiment of the present invention, there is further included a plurality of other fuse structures in the shallow trench isolation structure, the plurality of other fuse structures being identical to the fuse structure except that the horizontal portion has a different depth than the trench isolation structure.
The specific manufacturing method comprises the following steps:
(1) Referring to fig. 3, a substrate 1 is provided, and shallow trench isolation trenches are formed on the upper surface of the substrate 1;
(2) Referring to fig. 4, a shallow trench isolation structure 9 is formed in the shallow trench isolation trench, and a top surface of the shallow trench isolation structure 9 is higher than an upper surface of the substrate 1;
(3) Referring to fig. 5, a groove 10 is formed in the shallow trench isolation structure 9, and the depth, width and length of the groove 10 are smaller than those of the shallow trench isolation structure;
(4) Referring to fig. 6, a programmable fuse is formed on the upper surface of the shallow trench isolation structure 9 and in the recess 10, and the fuse structure is a polysilicon fuse structure; the programmable fuse includes two first electrodes 3a and 4a, two first vertical portions 6a and 7a connected to the two first electrodes 3a and 4a, respectively, and a first horizontal portion 5a connected to the two first vertical portions 6a and 7 a; wherein two first electrodes 3a and 4a are located at two ends of the upper surface of the shallow trench isolation structure 2, two first vertical portions 6a and 7a have a first length along the depth direction of the shallow trench isolation structure 2, and the first horizontal portion 5a is covered with isolation material of the shallow trench isolation structure and has a first depth in the shallow trench isolation structure 2;
(5) Referring to fig. 7, depositing the spacer material in the recess 10 forms a spacer material, 11, the spacer material layer 11 covering at least the first horizontal portion 5a. Specifically, forming the insulating material layer 11 includes covering the first horizontal portion 5a and a portion of the two first vertical portions 6a and 7a, that is, incompletely filling the recess 10.
(6) Referring to fig. 7, the other programmable fuse includes two second electrodes 3b and 4b, two second vertical portions 6b and 7b respectively connected to the two second electrodes 3b and 4b, and a second horizontal portion 5b connected to the two second vertical portions 6b and 7 b; wherein two second electrodes 3b and 4b are located at the other two ends of the upper surface of the shallow trench isolation structure 2, two second vertical portions 6b and 7b have a second length along the depth direction of the shallow trench isolation structure 2, and the second horizontal portion 5b is covered with the isolation material of the shallow trench isolation structure 2 and has a second depth in the shallow trench isolation structure 2.
(7) Referring to fig. 8, the isolation structure is further deposited in the recess 10 to form an isolation material layer 12 to completely fill the recess, ultimately forming a shallow trench isolation structure 2 and two fuse structures.
Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (1)
1. A method of fabricating a polysilicon fuse structure, comprising:
providing a substrate, and forming a shallow trench isolation trench on the upper surface of the substrate;
forming a shallow trench isolation structure in the shallow trench isolation trench, wherein the top surface of the shallow trench isolation structure is higher than the upper surface of the substrate;
forming a groove in the shallow groove isolation structure, wherein the depth, width and length of the groove are smaller than those of the shallow groove isolation structure;
forming a programmable fuse on the upper surface of the shallow trench isolation structure and in the groove, wherein the programmable fuse comprises two first electrodes, two first vertical parts respectively connected with the two first electrodes and a first horizontal part connected with the two first vertical parts; the two first electrodes are positioned at two ends of the upper surface of the shallow trench isolation structure, the two first vertical parts have a first length along the depth direction of the shallow trench isolation structure, and the first horizontal parts are covered by isolation materials of the shallow trench isolation structure and have a first depth in the shallow trench isolation structure;
depositing the isolation material in the groove to form an isolation material layer, wherein the isolation material layer at least covers the first horizontal part;
the isolation material of the shallow trench isolation structure is silicon oxide;
further comprising depositing an isolation structure in the recess to completely fill the recess; the widths of the two first electrodes are larger than those of the first vertical part and the first horizontal part;
the programmable fuse is made of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811011462.8A CN109390275B (en) | 2016-12-02 | 2016-12-02 | Manufacturing method of polycrystalline silicon fuse structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811011462.8A CN109390275B (en) | 2016-12-02 | 2016-12-02 | Manufacturing method of polycrystalline silicon fuse structure |
| CN201611096967.XA CN106449594B (en) | 2016-12-02 | 2016-12-02 | a kind of manufacturing method of programmable fuse structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611096967.XA Division CN106449594B (en) | 2016-12-02 | 2016-12-02 | a kind of manufacturing method of programmable fuse structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109390275A CN109390275A (en) | 2019-02-26 |
| CN109390275B true CN109390275B (en) | 2024-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611096967.XA Active CN106449594B (en) | 2016-12-02 | 2016-12-02 | a kind of manufacturing method of programmable fuse structure |
| CN201811028941.0A Active CN109411445B (en) | 2016-12-02 | 2016-12-02 | Method for manufacturing polysilicon fuse structure |
| CN201811013135.6A Active CN109346435B (en) | 2016-12-02 | 2016-12-02 | Method for manufacturing programmable polysilicon fuse structure |
| CN201811011462.8A Active CN109390275B (en) | 2016-12-02 | 2016-12-02 | Manufacturing method of polycrystalline silicon fuse structure |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611096967.XA Active CN106449594B (en) | 2016-12-02 | 2016-12-02 | a kind of manufacturing method of programmable fuse structure |
| CN201811028941.0A Active CN109411445B (en) | 2016-12-02 | 2016-12-02 | Method for manufacturing polysilicon fuse structure |
| CN201811013135.6A Active CN109346435B (en) | 2016-12-02 | 2016-12-02 | Method for manufacturing programmable polysilicon fuse structure |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256855B (en) * | 2017-07-11 | 2019-07-12 | 上海华力微电子有限公司 | A kind of fuse and its manufacturing method |
| CN111095546B (en) | 2018-08-24 | 2022-09-02 | 深圳市为通博科技有限责任公司 | Electric fuse, manufacturing method thereof and memory unit |
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- 2016-12-02 CN CN201811028941.0A patent/CN109411445B/en active Active
- 2016-12-02 CN CN201811013135.6A patent/CN109346435B/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109411445A (en) | 2019-03-01 |
| CN109411445B (en) | 2020-08-21 |
| CN106449594A (en) | 2017-02-22 |
| CN109346435A (en) | 2019-02-15 |
| CN106449594B (en) | 2018-10-02 |
| CN109390275A (en) | 2019-02-26 |
| CN109346435B (en) | 2023-09-05 |
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