CN104064548B - A kind of electrically programmable fuse device architecture and preparation method thereof - Google Patents
A kind of electrically programmable fuse device architecture and preparation method thereof Download PDFInfo
- Publication number
- CN104064548B CN104064548B CN201310089210.8A CN201310089210A CN104064548B CN 104064548 B CN104064548 B CN 104064548B CN 201310089210 A CN201310089210 A CN 201310089210A CN 104064548 B CN104064548 B CN 104064548B
- Authority
- CN
- China
- Prior art keywords
- polysilicon layer
- electrically programmable
- layer
- device architecture
- programmable fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 164
- 229920005591 polysilicon Polymers 0.000 claims abstract description 160
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 235
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 206010020741 Hyperpyrexia Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of electrically programmable fuse device architecture, including：Semiconductor substrate；The insulating oxide formed on the semiconductor substrate；Negative electrode, anode and the fuse for connecting the negative electrode and the anode of the electrically programmable fuse structure formed on the insulating oxide, and the virtual polysilicon layer positioned at the fuse both sides.According to the electrically programmable fuse device architecture of fuse of the manufacturing process of the present invention formation with uniform and small characteristic size, the electrically programmable fuse device architecture disclosure satisfy that the requirement of more advanced technology node.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of electrically programmable fuse (EFuse) device architecture and its
Preparation method.
Background technology
Microminiaturization and the raising of complexity with semiconductor technology, semiconductor element are also become easier to by various
The influence of defect or impurity, and the failure of plain conductor, diode or transistor etc. often constitutes the defect of whole chip, is
This problem is solved, prior art will form some fuses in integrated circuits, to ensure the utilizability of integrated circuit.
Electrically programmable fuse is the conventional device of semiconductor integrated circuit, and electrically programmable fuse is that the silicided polysilicon of electrically programmable melts
Silk.Electrically programmable fuse can with complementary metal oxide semiconductor (CMOS) technique of logic completely compatible, simple to operate, volume
It is small and higher flexibility can be provided.Therefore, electrically programmable fuse is widely used in many main integrated circuits, as
One Time Programmable (one-time-programmable, OTP) memory.In order to meet the semiconductor fabrication work continued to develop
Skill, electrically programmable fuse needs also be programmed under conditions of relatively low voltage and current intensity, and molten in electrically programmable
Its resistance value keeps constant after silk fusing.
A kind of common electrically programmable fuse device is as shown in Figure 1.The electrically programmable that Fig. 1 (a) is prepared according to prior art
The SEM schematic diagrames of fuse-wire device structure, from figure 1 it appears that electrically programmable fuse device is by anode, fuse and cathode sets
Into.Fig. 1 (b) is the schematic diagram of the single electrically programmable fuse and programmable transistor prepared according to prior art.
In the prior art for the technique of 90nm technology nodes, the Fuse in conventional electrically programmable fuse device
The length-width ratio (L/W) of link (fuse) size is smaller.Improved however as integrated circuit technique, device size constantly reduces.It is right
For the technique of more advanced technology node, the length-width ratio of fuse dimension is than existing in required electrically programmable fuse device
The length-width ratio of fuse dimension is much larger in technology.Therefore, electrically programmable fuse device of the prior art can not meet integrated
The requirement of circuit, and many defects can be produced, resistance value distribution scope increases after such as electrically programmable fuse fusing, fuse
The hyperpyrexia that the electric current being passed through is produced can cause the device overheat around on chip, then reduce device stability.
Therefore, it is badly in need of a kind of new electrically programmable fuse device architecture and preparation method thereof at present to meet more advanced skill
The requirement of art node.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of electrically programmable fuse device architecture, bag
Include：Semiconductor substrate；The insulating oxide formed on the semiconductor substrate；The electricity formed on the insulating oxide can
Negative electrode, anode and the fuse for connecting the negative electrode and the anode of programmable fuse structures, and positioned at the fuse both sides
Virtual polysilicon layer.
Preferably, the insulating oxide is shallow trench isolating oxide layer.
Preferably, the size of the negative electrode is more than the size of the anode.
Preferably, the virtual polysilicon layer is connected with the negative electrode and positioned at the both sides of the anode.
Preferably, the virtual polysilicon layer is not connected with the negative electrode and positioned at the both sides of the anode.
Preferably, the virtual polysilicon layer is the disrupted configuration being connected respectively with the negative electrode and the anode.
Preferably, the virtual polysilicon layer is the cut-off virtual polysilicon layer formed.
Preferably, the virtual polysilicon layer is cut off using P2- masks.
According to another aspect of the present invention, the invention also provides a kind of making for manufacturing electrically programmable fuse device architecture
Method, including：Semiconductor substrate is provided；Insulating oxide is formed on the semiconductor substrate；On the insulating oxide
Form polysilicon layer；It is described to form the negative electrode, anode and connection of electrically programmable fuse device architecture to etch the polysilicon layer
The fuse of negative electrode and the anode, and the virtual polysilicon layer positioned at the fuse both sides.
Preferably, in addition to cut off the virtual polysilicon layer the step of.
Preferably, virtual polysilicon layer is completely removed described in the cut-out step.
Preferably, autoregistration polycrystalline is sequentially formed on the polysilicon layer for being additionally included in the electrically programmable fuse device architecture
Silicide layer, contact hole etching stop-layer and interlayer dielectric layer, and the formation connection negative electrode in the interlayer dielectric layer
The step of with the contact hole of the anode.
It is to sum up shown, according to the electricity of fuse of the manufacturing process of the present invention formation with uniform, narrow and small characteristic size
Programmable fuse device architecture.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 (a) is the SEM schematic diagrames of the electrically programmable fuse device architecture made according to prior art；
Fig. 1 (b) is the single electrically programmable fuse device and a programmable transistor made according to prior art
Schematic diagram；
Fig. 2A is the top end view that electrically programmable fuse device architecture is made according to first embodiment of the present invention；
Fig. 2 B are the profilograph view that electrically programmable fuse device architecture is made according to first embodiment of the present invention；
Fig. 3 is the top end view that electrically programmable fuse device architecture is made according to second embodiment of the present invention；
Fig. 4 A- Fig. 4 C are the correlation step that electrically programmable fuse device architecture is made according to the 3rd embodiment of the present invention
The top end view of the device obtained；
Fig. 5 is the process chart that electrically programmable fuse device architecture is made according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it will be apparent to one skilled in the art that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What makes electrically programmable fuse device architecture using a kind of new method, to meet the requirement of more advanced technology nodes.Obviously
Presently preferred embodiments of the present invention being described as follows in detail, but remove these and be described in detail outer, the present invention can also have other
Embodiment.
The present invention proposes a kind of electrically programmable fuse device architecture and preparation method.Fig. 2A -2B are according to the present invention the
One embodiment makes the top end view and profilograph view of electrically programmable fuse device architecture.
As shown in Figure 2 B, semi-conductive substrate (not shown) is provided first, and the Semiconductor substrate can be silicon or exhausted
Silicon (SOI) on edge body, forms insulating oxide 200 on a semiconductor substrate, and insulating oxide 200 can be shallow trench isolation
(STI) oxide layer or buried oxide (BOX), its preparation method can be using techniques such as zone oxidation method and shallow isolating troughs.It is excellent
Shallow trench isolating oxide layer is selected, as an example, the step of forming the shallow trench isolating oxide layer includes, defined active
The first silicon oxide layer and nitration case are formed on the substrate in area, the substrate of the first silicon oxide layer, silicon nitride layer and partial depth is etched,
To form shallow trench between the active area, silicon dioxide layer is formed in the shallow trench, nitrogen is covered in silicon dioxide layer
Change layer, planarize the second silicon oxide layer, the nitration case of active area is covered with exposure, remove nitration case.Then, can be using chemistry
Vapour deposition (CVD) or other suitable methods form polysilicon layer (not shown) on shallow trench isolating oxide layer 200, many
The forming method of crystal silicon layer preferably uses low-pressure chemical vapor phase deposition (LPCVD) technique.As an example, the polysilicon is formed
The process conditions of layer include：Reacting gas is silane (SiH4), the range of flow of the silane can for 100~200 cubic centimetres/
Minute (sccm), such as 150 cc/mins (sccm)；Temperature range can be 700~750 degrees Celsius in reaction chamber；Reaction chamber
Interior pressure can be 250~350 milli millimetress of mercury (mTorr), such as 300mTorr；Buffering gas is may also include in the reacting gas
Body, the buffer gas can be helium (He) or nitrogen, and the range of flow of the helium and nitrogen can be 5~20 liters/min
(slm), such as 8slm, 10slm or 15slm.It is then possible to be selected using reactive ion etching (RIE) or other suitable methods
Partial polysilicon layer is removed to selecting property, thus etching forms the polysilicon layer 201 of electrically programmable fuse as shown in Figure 2 A, i.e. bottle
The polysilicon layer 201 of neck-shaped, the polysilicon layer 201 of electrically programmable fuse includes：Polysilicon layer 201b, the polycrystalline of fuse of fuse
The polysilicon layer 201a of the big fuse head at the silicon layer 201b two ends and polysilicon layer 201c of small fuse head, wherein, big fuse head
201a polysilicon layer can as electrically programmable fuse device architecture negative electrode, small fuse head 201c polysilicon layer can be used as electricity
The anode of programmable fuse device architecture, the size of negative electrode polysilicon layer is more than the size of anode polysilicon layer.Meanwhile, in fuse
Polysilicon layer 201b both sides be formed with virtual polysilicon (Dummy poly) layer 202, while virtual polysilicon layer 202 with it is cloudy
Pole polysilicon layer 201a connections and the both sides for also being located at anode polysilicon.Wherein, positioned at fuse polysilicon layer 201b both sides
Virtual polysilicon layer 202, its purpose is to prevent the polysilicon layer 201 in polysilicon layer etched composition formation fuse
Because polysilicon layer density is too low, fuse line width is smaller in process for making, the size of the polysilicon layer of fuse is influenceed
And uniformity, the structure (technological factor of influence includes photoetching, etching etc.) of the polysilicon layer of fuse is damaged, therefore, electricity can be compiled
The virtual polysilicon layer 202 of the both sides of polysilicon layer 201 of journey electric fuse structure is to realize with uniform and narrow fuse
Electrically programmable electric fuse device structure to meet more advanced technology node.Wherein, polysilicon layer 201 can mix N-type or P
Type undopes.Or as shown in Figure 2 A, be in 201a, 201b and 201c using three sections of different doping to polysilicon layer 201
Three sections of different DOPOS doped polycrystalline silicons, wherein, 201a is N-type (or p-type), and 201c opposite with 201a dopant species is p-type (or N-type),
201b can be undope area or n-type doping area or p-type doped region or p-type and N-type co-doped area.They are all same layers
The polysilicon of deposition, is formed using ion implantation doping, can be with the N in CMOS integrated circuits+Injection, and/or P+Injection and/
Or prolong before N-type drain injection, and/or p-type drain electrode before prolong injection mask plate share, do not increase any processing step and chip so
Area, can only be realized by layout design.
Then, self aligned polycide (salicide) layer is formed on the polysilicon layer 201 of electrically programmable fuse
203.As an example, forming the technique of self aligned polycide layer includes, first deposited metal layer, and it may include to contain
The material of tungsten, titanium, nickel, cobalt, tantalum and platinum or its combination.Then substrate is heated, causes metal level to occur with the polysilicon layer under it
Silicification, to form metal silicified layer region.Using erodable metal level, but will not attack metal disilicide layer region etching
Agent, unreacted metal level is removed.Then, in the polysilicon layer 201 and autoregistration polysilicon of the electrically programmable fuse
Clearance wall structure 204 is formed on the side wall of compound layer 203.Then, in insulating oxide 200, self aligned polycide layer 203
With formation contact hole etching stop-layer 205, the preferred nitride of material of contact hole etching stop-layer 205 on clearance wall structure 204.
Then, interlayer dielectric layer (not shown) is formed on contact hole etching stop-layer 205, it can be for one layer or more
Layer is constituted, and the material of interlayer dielectric layer can be a kind of or combination composition in oxide, nitride, nitrogen oxides.Prepare
Method can be using ion injection method, heat or plasma oxidation or nitriding method, chemical gaseous phase depositing process and physical vapor
Deposition process.
Then, the two ends in interlayer dielectric layer form through hole, and the through hole exposes metal silicide layer 203, then
Through hole is filled using conductive material, conductive material and metal silicide layer 203 is in contact, the connection negative electrode and anode is formed
Contact hole 206, the conductive material filled in the through hole can be DOPOS doped polycrystalline silicon, metal material etc., the conductive material
It is preferred that tungsten material.
After above-mentioned process implementing, forming the electrically programmable fuse structure of the present invention includes, and Semiconductor substrate (is not shown
Go out), the polysilicon layer 201 of insulating oxide 200 and electrically programmable fuse, the electrically programmable are formed with a semiconductor substrate
The polysilicon layer 201 of fuse includes：The polysilicon layer 201b of fuse, the negative electrode polysilicon layer at the polysilicon layer 201b two ends of fuse
201a and anode polysilicon layer 202c, while being the polysilicon layer 201b for being located at electrically programmable fuse on insulating oxide 200
Both sides be formed with virtual polysilicon layer 202, meanwhile, virtual polysilicon layer 202 be connected with negative electrode polysilicon layer 201a and
Positioned at anode polysilicon layer 201c both sides.Self aligned polycide layer 203 is formed with the polysilicon layer 201,
Clearance wall structure 204 is formed with the side wall of polysilicon layer 201 and self aligned polycide layer 203, then, in insulating oxide
Contact hole etching stop-layer 205, interlayer are formed with layer 200, self aligned polycide layer 203 and clearance wall structure 204 to be situated between
Matter layer (not shown) and the contact hole 206 for connecting the negative electrode and the anode at interlayer dielectric layer two ends.
Fig. 3 is the top end view that electrically programmable fuse device architecture is made according to second embodiment of the present invention, with the
The difference of one embodiment is that virtual polysilicon layer 302 does not connect with the negative electrode polysilicon layer 301a in polysilicon layer 301
Connect.Wherein, the virtual polysilicon layer 302 formed in the polysilicon layer 301b both sides of fuse, its purpose is to realize to have
Even and narrow electrically programmable electric fuse device structure is to meet the requirement of more advanced technology node.
Based on after one embodiment identical process implementing, forming the electrically programmable fuse device architecture bag of the present invention
Include, Semiconductor substrate (not shown), insulating oxide (not shown) and electrically programmable fuse are formed with a semiconductor substrate
Polysilicon layer 301, the polysilicon layer 301 of the electrically programmable fuse includes：Polysilicon layer 301b, the polysilicon of fuse of fuse
The negative electrode polysilicon layer 301a and anode polysilicon layer 302c at layer 301b two ends, at the same be fuse polysilicon layer 301b two
Side is formed with virtual polysilicon layer 302, meanwhile, virtual polysilicon layer 302 and negative electrode polysilicon layer 301a are not connected with and also position
In anode polysilicon layer 301c both sides.Autoregistration polysilicon is formed with the polysilicon layer 301 of the electrically programmable fuse
Compound layer (not shown), is formed with the side wall of polysilicon layer 301 and the self aligned polycide layer of electrically programmable fuse
Clearance wall structure (not shown), then, is formed on insulating oxide 300, self aligned polycide layer and clearance wall structure
There are contact hole etching stop-layer (not shown), interlayer dielectric layer (not shown) and described the moon of connection at interlayer dielectric layer two ends
The contact hole 303 of pole and the anode.
Fig. 4 A- Fig. 4 C are each step institute according to the 3rd embodiment making electrically programmable fuse device architecture of the present invention
The top end view of the device of acquisition.It is with the difference of first and second embodiment, the 3rd embodiment uses P2-
Mask cut (cutting of P2- masks) technique makes virtual polysilicon layer 402 and the moon in the polysilicon layer 401 of electrically programmable fuse
Pole polysilicon layer 401a and anode polysilicon layer 401b separation, that is, cut off virtual polysilicon layer 402, or can cut completely
Except virtual polysilicon layer 402.
As shown in Figure 4 A, semi-conductive substrate (not shown) is provided first, and the Semiconductor substrate can be silicon or exhausted
Silicon (SOI) on edge body, forms insulating oxide (not shown) on a semiconductor substrate, and insulating oxide can be shallow trench isolation
(STI) oxide layer or buried oxide (BOX), can be using techniques such as zone oxidation method and shallow isolating troughs.It is preferred that shallow trench every
From oxide layer.Then, can be using chemical vapor deposition (CVD) or other suitable methods in shallow trench isolating oxide layer
Polysilicon layer (not shown) is formed on (not shown), it is then possible to using reactive ion etching (RIE) or other suitable sides
Method optionally removes partial polysilicon layer, is consequently formed the polysilicon layer 401 of electrically programmable fuse as shown in Figure 4 A, i.e. bottle
The polysilicon layer 401 of neck-shaped, the polysilicon layer 401 of electrically programmable fuse includes：Polysilicon layer 401b, the polycrystalline of fuse of fuse
The polysilicon layer 401a of the big fuse head at the silicon layer 401b two ends and polysilicon layer 402c of small fuse head, wherein, big fuse head
Polysilicon layer 401a is as the negative electrode of electrically programmable fuse device architecture, and the polysilicon layer 401c of small fuse head is used as electrically programmable
The anode of fuse-wire device structure, the size of negative electrode polysilicon layer is more than the size of anode polysilicon layer.In the polysilicon layer of fuse
401b both sides are formed with virtual polysilicon layer 402, at the same virtual polysilicon layer 402 with negative electrode polysilicon layer 401a and anode
Polysilicon layer 402c is connected.Wherein, the virtual polysilicon layer 402 formed in the polysilicon layer 401b both sides of fuse, its purpose
It is to meet more advanced technology node in order to realize uniform and narrow small characteristic size electrically programmable electric fuse device structure.
As shown in Figure 4 B, virtual polysilicon layer 402 is cut using P2- masks.Wherein, due in more advanced technology nodes
Middle P2- masks have been used to processing polysilicon and silicon oxynitride.Therefore, cut virtual polysilicon layer 402 when, can and polycrystalline
Silicon and silicon oxynitride share P2- masks, do not increase the consumption of extra processing step and semi-conducting material.Through using P2- masks
To cut after virtual polysilicon layer 402, by virtual polysilicon layer 402 and negative electrode polysilicon layer 401a and anode polysilicon layer 401b
Separation, that is, cut off virtual polysilicon layer 402.Wherein, it is preferred to use P2- masks cut the virtual polysilicon layer 402 of removal completely.Most
Eventually, the polysilicon layer 403 of electrically programmable electric fuse is formed.
As shown in Figure 4 C, self aligned polycide (salicide) layer (not shown) is formed on polysilicon layer 403.Connect
, clearance wall structure (not shown) is formed on the side wall of polysilicon layer 403 and self-alignment silicide layer, in insulating oxide
Contact hole etching stop-layer (not shown), the preferred titanium nitride of material of wherein contact hole etching stop-layer are formed on 400.Then,
Interlayer dielectric layer (not shown) is formed on contact hole etching stop-layer.Then, two ends in the dielectric layer form through hole, described
Through hole exposes metal silicide layer, then fills through hole using conductive material, conductive material and metal silicide layer is connected
Touch, forming the conductive material filled in the contact hole 404 for connecting the negative electrode and the anode, the through hole can be more to adulterate
Crystal silicon, metal material etc., the preferred tungsten material of conductive material.
After above-mentioned process implementing, forming the electric fuse device structure of the present invention includes, Semiconductor substrate (not shown),
The polysilicon layer 403 of insulating oxide (not shown) and electrically programmable fuse is formed with a semiconductor substrate, and the electricity can be compiled
The polysilicon layer 403 of journey fuse includes：The polysilicon layer 403b of fuse, the negative electrode polysilicon at the polysilicon layer 403b two ends of fuse
Layer 403a and anode polysilicon layer 403c.Cut-off virtual polysilicon layer 402 is also formed with insulating oxide simultaneously, its
It is connected with negative electrode polysilicon layer and anode polysilicon layer.Formed on the polysilicon layer 403 of the electrically programmable fuse
There is self aligned polycide layer (not shown), in polysilicon layer 403 and the self aligned polycide layer of electrically programmable fuse
Side wall on formed clearance wall structure (not shown), insulating oxide, self aligned polycide layer and clearance wall structure on
Be formed with contact hole etching stop-layer, be formed with the contact hole etching stop-layer interlayer dielectric layer (not shown) and
The contact hole 404 for connecting the negative electrode and the anode at interlayer dielectric layer two ends.
Fig. 5 is the flow chart that electrically programmable fuse device architecture is made according to one embodiment of the present invention, for brief
The flow of whole manufacturing process is shown.
In step 501 there is provided Semiconductor substrate, insulating oxide is formed on a semiconductor substrate.In step 502,
The polysilicon layer and virtual polysilicon layer of electrically programmable fuse, the polysilicon layer of electrically programmable fuse are formed on insulating oxide
Including：The polysilicon layer of fuse, the negative electrode polysilicon layer and anode polysilicon layer at the polysilicon layer two ends of fuse, virtual polysilicon
Layer is located at the both sides of the polysilicon layer of fuse.Wherein virtual polysilicon layer can be connected with negative electrode polysilicon layer, virtual polysilicon
Layer can be not connected with negative electrode polysilicon layer or virtual polysilicon layer can be with negative electrode polysilicon layer and anode polysilicon layer
It is connected and virtual polysilicon layer is cut off.In step 503, autoregistration is formed on the polysilicon layer of electrically programmable fuse
Multi-crystal silicification nitride layer, clearance wall structure is formed with the side wall of polysilicon layer and autoregistration multicrystalline silicon compounds.In step 504
In, form etching stop layer dielectric layer on insulating oxide, self aligned polycide layer and clearance wall structure and interlayer is situated between
Matter layer.In step 505, the contact hole for connecting the negative electrode and the anode is formed in interlayer dielectric layer.
To sum up shown, the present invention proposes the structure and preparation method of new electrically programmable fuse device, according to the present invention
Technique can form the electrically programmable fuse device architecture of small characteristic size, i.e., form uniform and narrow between the fuse head of two ends
Fuse.The electrically programmable fuse device architecture disclosure satisfy that the requirement of more advanced technology nodes
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member it is understood that the invention is not limited in above-described embodiment, according to the present invention can also make more kinds of modifications and
Modification, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is by attached
Claims and its equivalent scope are defined.
Claims (12)
1. a kind of electrically programmable fuse device architecture, including：
Semiconductor substrate；
The insulating oxide formed on the semiconductor substrate；
The negative electrode of the electrically programmable fuse structure formed on the insulating oxide, anode and connect the negative electrode and the sun
The fuse of pole, and for realizing that being located at for the electrically programmable electric fuse device structure with uniform and narrow fuse is described molten
The virtual polysilicon layer of silk both sides.
2. electrically programmable fuse device architecture as claimed in claim 1, it is characterised in that the insulating oxide is shallow trench
Isolating oxide layer.
3. electrically programmable fuse device architecture as claimed in claim 1, it is characterised in that the size of the negative electrode is more than described
The size of anode.
4. electrically programmable fuse device architecture as claimed in claim 3, it is characterised in that the virtual polysilicon layer with it is described
Negative electrode is connected and positioned at the both sides of the anode.
5. electrically programmable fuse device architecture as claimed in claim 3, it is characterised in that the virtual polysilicon layer with it is described
Negative electrode is not connected with and positioned at the both sides of the anode.
6. electrically programmable fuse device architecture as claimed in claim 1, it is characterised in that the virtual polysilicon layer is difference
The disrupted configuration being connected with the negative electrode and the anode.
7. electrically programmable fuse device architecture as claimed in claim 6, it is characterised in that the virtual polysilicon layer is to be cut
The disconnected virtual polysilicon layer formed.
8. electrically programmable fuse device architecture as claimed in claim 7, it is characterised in that cut off described using P2- masks
Virtual polysilicon layer.
9. a kind of preparation method for manufacturing the electrically programmable fuse device architecture as any one of claim 1-8, bag
Include：
Semiconductor substrate is provided；
Insulating oxide is formed on the semiconductor substrate；
Polysilicon layer is formed on the insulating oxide；
The polysilicon layer is etched to form the negative electrode of electrically programmable fuse device architecture, anode and connect the negative electrode and described
The fuse of anode, and the virtual polysilicon layer positioned at the fuse both sides.
10. method as claimed in claim 9, it is characterised in that also including cutting off the virtual polysilicon layer the step of.
11. method as claimed in claim 10, it is characterised in that virtual polysilicon layer is complete described in the cut-out step
Full removal.
12. method as claimed in claim 9, it is characterised in that be additionally included in many of the electrically programmable fuse device architecture
Self aligned polycide layer, contact hole etching stop-layer and interlayer dielectric layer are sequentially formed on crystal silicon layer, and in the layer
Between the step of the contact hole for connecting the negative electrode and the anode is formed in dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310089210.8A CN104064548B (en) | 2013-03-19 | 2013-03-19 | A kind of electrically programmable fuse device architecture and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310089210.8A CN104064548B (en) | 2013-03-19 | 2013-03-19 | A kind of electrically programmable fuse device architecture and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104064548A CN104064548A (en) | 2014-09-24 |
| CN104064548B true CN104064548B (en) | 2017-08-01 |
Family
ID=51552192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310089210.8A Active CN104064548B (en) | 2013-03-19 | 2013-03-19 | A kind of electrically programmable fuse device architecture and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104064548B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106910525B (en) * | 2015-12-23 | 2019-09-20 | 中芯国际集成电路制造(北京)有限公司 | Electrically programmable fuse cell array and its operating method |
| CN109411445B (en) * | 2016-12-02 | 2020-08-21 | 乐清市风杰电子科技有限公司 | Method for manufacturing polysilicon fuse structure |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1645607A (en) * | 2004-01-23 | 2005-07-27 | 富士通株式会社 | Semiconductor device and method for fabricating the same |
| CN101261979A (en) * | 2007-03-09 | 2008-09-10 | 台湾积体电路制造股份有限公司 | integrated circuit structure |
| CN101546749A (en) * | 2008-03-27 | 2009-09-30 | 联发科技股份有限公司 | Electronic fuse structure |
| CN101562172A (en) * | 2008-04-14 | 2009-10-21 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN102074546A (en) * | 2009-11-25 | 2011-05-25 | 采钰科技股份有限公司 | Electronic component with fuse structure and repair method thereof |
-
2013
- 2013-03-19 CN CN201310089210.8A patent/CN104064548B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1645607A (en) * | 2004-01-23 | 2005-07-27 | 富士通株式会社 | Semiconductor device and method for fabricating the same |
| CN101261979A (en) * | 2007-03-09 | 2008-09-10 | 台湾积体电路制造股份有限公司 | integrated circuit structure |
| CN101546749A (en) * | 2008-03-27 | 2009-09-30 | 联发科技股份有限公司 | Electronic fuse structure |
| CN101562172A (en) * | 2008-04-14 | 2009-10-21 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN102074546A (en) * | 2009-11-25 | 2011-05-25 | 采钰科技股份有限公司 | Electronic component with fuse structure and repair method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104064548A (en) | 2014-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11011622B2 (en) | Closely packed vertical transistors with reduced contact resistance | |
| KR102465095B1 (en) | Etch stop layer for semiconductor devices | |
| TWI677016B (en) | Method of forming semiconductor device | |
| US10366940B2 (en) | Air gap and air spacer pinch off | |
| US7405112B2 (en) | Low contact resistance CMOS circuits and methods for their fabrication | |
| US6534781B2 (en) | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact | |
| US6649928B2 (en) | Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby | |
| US9437593B2 (en) | Silicided semiconductor structure and method of forming the same | |
| US8163640B2 (en) | Metal gate compatible electrical fuse | |
| US20080286957A1 (en) | Method forming epitaxial silicon structure | |
| US20020093042A1 (en) | Integrated circuit devices that utilize doped Poly-Si1-xGex conductive plugs as interconnects and methods of fabricating the same | |
| CN103050407B (en) | Embedded Transistor | |
| US10032679B1 (en) | Self-aligned doping in source/drain regions for low contact resistance | |
| EP3306670B1 (en) | Semiconductor device structure with non planar side wall and method of manufacturing using a doped dielectric | |
| US10832961B1 (en) | Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor | |
| CN104064548B (en) | A kind of electrically programmable fuse device architecture and preparation method thereof | |
| US20220069126A1 (en) | Method for fabricating semiconductor device with programmable element | |
| US10468491B1 (en) | Low resistance contact for transistors | |
| TW202303685A (en) | Method of forming the semiconductor structure | |
| KR100903470B1 (en) | Semiconductor element and manufacturing method thereof | |
| TWI855817B (en) | Semiconductor device structure including fuse structure embedded in substrate | |
| US20240079325A1 (en) | Hybrid backside dielectric for clock and power wires | |
| TWI334221B (en) | Electrostatic discharge protection device and method for fabricating thereof | |
| CN116013897A (en) | Fuse element, semiconductor element and method for manufacturing fuse element | |
| CN108461476A (en) | A kind of electric fuse device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |