CN109346572B - Manufacturing method of light emitting diode epitaxial wafer and light emitting diode epitaxial wafer - Google Patents

Abstract

The invention discloses a manufacturing method of a light-emitting diode epitaxial wafer and a light-emitting diode epitaxial wafer, belonging to the technical field of semiconductors. The manufacturing method includes: providing a substrate; growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence, and the N-type semiconductor layer is an N-type doped nitride; A groove extending to the N-type semiconductor is opened on the P-type semiconductor layer; electron irradiation is performed on the surface of the N-type semiconductor layer in the groove to increase nitrogen in the N-type semiconductor layer in the groove Vacancy, the surface of the N-type semiconductor layer in the groove is used for setting the N-type electrode. The invention increases the nitrogen vacancy in the N-type semiconductor layer by irradiating the surface of the N-type semiconductor layer with the N-type electrode, promotes the incorporation of the N-type dopant, improves the effectiveness of the incorporation of the doping element, and changes the Due to the high impurity state caused by heavy doping, the mobility of carriers is improved, and the light efficiency of the entire light-emitting diode is improved.

Description

A manufacturing method of a light-emitting diode epitaxial wafer and a light-emitting diode epitaxial wafer

technical field

The invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a light emitting diode epitaxial wafer and a light emitting diode epitaxial wafer.

Background technique

Light Emitting Diode (English: Light Emitting Diode, LED for short) is a semiconductor electronic component that can emit light. Gallium nitride (GaN) has good thermal conductivity, high temperature resistance, acid and alkali resistance, high hardness and other excellent characteristics, so that gallium nitride (GaN)-based LEDs have received more and more attention and research.

Epitaxial wafers are the primary finished products in the LED fabrication process. The existing LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, and the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate. The P-type semiconductor layer is used to provide holes for recombination emission, the N-type semiconductor layer is used to provide electrons for recombination emission, the active layer is used for radiative recombination emission of electrons and holes, and the substrate is used to provide epitaxial materials growth surface.

The chip is the core component of the LED, and the chip includes an epitaxial wafer and electrodes arranged on the epitaxial wafer. In the chip process, a groove extending to the N-type semiconductor layer is usually formed on the P-type semiconductor layer, and the N-type electrode is arranged on the N-type semiconductor layer in the groove. In addition, a P-type electrode is provided on the P-type semiconductor layer.

In order to form a good ohmic contact with the electrode, the N-type semiconductor layer is heavily doped, and an ultra-thin barrier is obtained by heavy doping. The ultra-thin barrier has no blocking ability for carriers, and the carriers can freely pass through the barrier to form a large tunnel current, thereby obtaining an ohmic contact (no obvious additional barrier is generated, and the voltage drop generated by the current on the contact layer) less than the voltage drop developed across the device itself).

In the process of realizing the present invention, the inventor found that the prior art has at least the following problems:

The material of the substrate is usually sapphire, and the material of the N-type semiconductor layer is usually gallium nitride. Sapphire and gallium nitride are heterogeneous materials, the lattice constants are quite different, and there is a large lattice mismatch between the two. . The stress and defects generated by the lattice mismatch will be introduced into the gallium nitride more and accumulate continuously during the epitaxial growth process, resulting in large crystal defects in the N-type semiconductor layer. In addition, the N-type semiconductor layer is heavily doped, and excessive impurity defects will be introduced in the process of heavy doping, so the defect concentration in the N-type semiconductor layer is very high. The high concentration of defects will constrain the migration of carriers and affect the light efficiency of the entire light-emitting diode.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a method for fabricating a light-emitting diode epitaxial wafer and a light-emitting diode epitaxial wafer, which can solve the problem that high-concentration defects in the N-type semiconductor layer in the prior art will constrain the migration of carriers and affect the light emission of the entire light-emitting diode. effectiveness issue. The technical solution is as follows:

In one aspect, an embodiment of the present invention provides a method for fabricating a light-emitting diode epitaxial wafer, the fabrication method comprising:

providing a substrate;

growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence, and the N-type semiconductor layer is an N-type doped nitride;

opening a groove extending to the N-type semiconductor on the P-type semiconductor layer;

The surface of the N-type semiconductor layer in the groove is irradiated with electrons to increase nitrogen vacancies in the N-type semiconductor layer in the groove, and the surface of the N-type semiconductor layer in the groove is used for setting N type electrode.

Optionally, the radiation dose of electron irradiation is 10 ¹⁶ /cm ² to 10 ²² /cm ² .

Optionally, performing electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove includes:

The surface of the N-type semiconductor layer in the groove is irradiated with an electron beam provided by a transmission electron microscope as a light source.

Preferably, the diameter of the electron beam is 8 μm˜30 μm.

Optionally, the manufacturing method further includes:

After the electron irradiation is performed on the surface of the N-type semiconductor layer in the groove, the N-type semiconductor layer in the groove is annealed.

In a possible implementation manner of the embodiment of the present invention, the manufacturing method further includes:

The surface of the P-type semiconductor layer is irradiated with electrons to increase nitrogen vacancies in the P-type semiconductor layer, the P-type semiconductor layer is a P-type doped nitride, and the surface of the P-type semiconductor layer is for setting P-type electrodes.

Optionally, the manufacturing method further includes:

After the electron irradiation to the surface of the P-type semiconductor layer, the P-type semiconductor layer is subjected to annealing treatment.

In another possible implementation manner of the embodiment of the present invention, the manufacturing method further includes:

growing a contact layer on the P-type semiconductor layer, the contact layer is a P-type doped nitride, and the surface of the contact layer is used for arranging a P-type electrode;

The surface of the contact layer is irradiated with electrons to increase nitrogen vacancies in the contact layer.

Optionally, the manufacturing method further includes:

After the electron irradiation of the surface of the contact layer, the contact layer is annealed.

On the other hand, an embodiment of the present invention provides a light-emitting diode epitaxial wafer, the light-emitting diode epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, the N-type semiconductor layer, the The active layer and the P-type semiconductor layer are sequentially stacked on the substrate, the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, and the N-type semiconductor layer in the groove The surface of the N-type semiconductor layer is used for setting the N-type electrode, and the surface of the N-type semiconductor layer in the groove is the surface treated by electron irradiation.

The beneficial effects brought by the technical solutions provided in the embodiments of the present invention are:

By irradiating the surface of the N-type semiconductor layer with the N-type electrode, the microstructure of the N-type semiconductor layer crystal is changed, and the shape and quantity of the defects in the N-type semiconductor layer are affected. Many nitrogen vacancies increase the nitrogen vacancies in the N-type semiconductor layer, promote the incorporation of N-type dopants, improve the effectiveness of the incorporation of doping elements, change the high impurity state caused by heavy doping, and improve the carrier The mobility of the N-type electrode is improved, the electrical contact between the N-type electrode and the N-type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the entire light-emitting diode is improved.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a flowchart of a method for fabricating a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 101 of the manufacturing method provided by an embodiment of the present invention;

3 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 102 is performed by the manufacturing method provided by the embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 103 of the manufacturing method provided by the embodiment of the present invention;

5 is a schematic structural diagram of a light-emitting diode epitaxial wafer during the execution of step 104 of the manufacturing method provided by the embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a light emitting diode epitaxial wafer provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

Embodiments of the present invention provide a method for fabricating a light-emitting diode epitaxial wafer. FIG. 1 is a flowchart of a method for fabricating a light-emitting diode epitaxial wafer according to an embodiment of the present invention. Referring to Figure 1, the manufacturing method includes:

Step 101: Provide a substrate.

FIG. 2 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 101 is performed by the manufacturing method provided by the embodiment of the present invention. Wherein, 10 represents the substrate.

Specifically, the material of the substrate can be sapphire (the main material is aluminum oxide), such as sapphire with a crystal orientation of [0001].

Specifically, this step 101 may include:

The temperature is controlled to be 1000°C to 1200°C (preferably 1100°C), and the substrate is annealed for 6 minutes to 10 minutes (preferably 8 minutes) in a hydrogen atmosphere;

The substrate is nitrided.

The above steps are used to clean the surface of the substrate to avoid doping impurities into the epitaxial wafer, affecting the overall crystal quality and reducing the luminous efficiency of the LED.

Step 102 : growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence, where the N-type semiconductor layer is an N-type doped nitride.

FIG. 3 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 102 is performed by the manufacturing method provided by the embodiment of the present invention. Among them, 20 represents an N-type semiconductor layer, 30 represents an active layer, and 40 represents a P-type semiconductor layer. Referring to FIG. 3 , the N-type semiconductor layer 20 , the active layer 30 , and the P-type semiconductor layer 40 are sequentially stacked on the substrate 10 .

Specifically, the material of the N-type semiconductor layer may be N-type doped (eg, silicon) gallium nitride (GaN). The active layer can include multiple quantum wells and multiple quantum barriers, and multiple quantum wells and multiple quantum barriers are alternately stacked; the material of the quantum wells can be indium gallium nitride (InGaN), such as In _x Ga _1-x N , 0<x<1; the material of the quantum barrier can be gallium nitride. The material of the P-type semiconductor layer can be P-type doped (eg, magnesium) gallium nitride.

Further, the thickness of the N-type semiconductor layer may be 1 μm˜5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer may be 10 ¹⁸ cm ^-3 -10 ¹⁹ cm ^-3 , preferably 5 *10 ¹⁸ cm ^-3 . The number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers can be 3 to 15 (preferably 9); the thickness of the quantum wells can be 2.5 nm to 3.5 nm (preferably 3 nm), and the thickness of the quantum barriers It may be 9 nm to 20 nm (preferably 15 nm). The thickness of the P-type semiconductor layer can be 100nm-800nm, preferably 450nm; the doping concentration of the P-type dopant in the P-type semiconductor layer can be 10 ¹⁸ cm ^-3 -10 ¹⁹ cm ^-3 , preferably 5*10 ¹⁸ cm ^-3 .

Specifically, this step 102 may include:

The first step is to control the temperature to be 1000°C to 1200°C (preferably 1100°C), and the pressure to be 100torr to 500torr (preferably 300torr), and grow an N-type semiconductor layer on the substrate;

In the second step, the active layer is grown on the N-type semiconductor layer; the growth temperature of the quantum well is 720°C to 829°C (preferably 770°C), and the growth pressure of the quantum well is 100torr to 500torr (preferably 300torr); the quantum barrier The growth temperature of the quantum barrier is 850°C to 959°C (preferably 900°C), and the growth pressure of the quantum barrier is 100torr to 500torr (preferably 300torr);

The third step is to control the temperature to be 850°C to 1080°C (preferably 960°C) and the pressure to be 100torr to 300torr (preferably 200torr) to grow a P-type semiconductor layer on the active layer.

Optionally, before the first step, the manufacturing method may further include:

A buffer layer is grown on the substrate.

The buffer layer is used to relieve the stress and defects caused by the lattice mismatch between the substrate material and the gallium nitride, and provide a nucleation center for the epitaxial growth of the gallium nitride material.

Accordingly, the N-type semiconductor layer is grown on the buffer layer.

Specifically, the material of the buffer layer can be gallium nitride (GaN).

Further, the thickness of the buffer layer may be 15 nm to 35 nm, preferably 25 nm.

Specifically, growing the buffer layer on the substrate may include:

Control the temperature to be 400°C to 600°C (preferably 500°C), and the pressure to be 400torr to 600torr (preferably 500torr), and grow a buffer layer on the substrate;

Control the temperature to be 1000°C to 1200°C (preferably 1100°C), the pressure to be 400 Torr to 600 Torr (preferably 500 torr), and the duration to be 5 minutes to 10 minutes (preferably 8 minutes), to perform in-situ annealing treatment on the buffer layer.

Preferably, after growing the buffer layer on the substrate, the manufacturing method may further include:

An undoped gallium nitride layer is grown on the buffer layer.

By further alleviating the stress and defects generated by the lattice mismatch between the substrate material and the gallium nitride, a growth surface with better crystal quality is provided for the main structure of the epitaxial wafer.

Accordingly, the N-type semiconductor layer is grown on the undoped gallium nitride layer.

In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown on the patterned substrate at a low temperature, so it is also called a low temperature buffer layer. Then, the longitudinal growth of gallium nitride in the low temperature buffer layer will form multiple independent three-dimensional island structures, which are called three-dimensional nucleation layers; then nitrogen is carried out on and between all three-dimensional island structures. The lateral growth of gallium nitride forms a two-dimensional planar structure, which is called a two-dimensional recovery layer; finally, a thicker layer of gallium nitride is grown on the two-dimensional growth layer at high temperature, which is called an intrinsic gallium nitride layer. In this embodiment, the three-dimensional nucleation layer, the two-dimensional recovery layer and the intrinsic gallium nitride layer are collectively referred to as the undoped gallium nitride layer.

Further, the thickness of the undoped gallium nitride layer may be 1 μm˜5 μm, preferably 3 μm.

Specifically, growing an undoped gallium nitride layer on the buffer layer may include:

The temperature is controlled to be 1000°C to 1100°C (preferably 1050°C), the pressure is controlled to be 100torr to 500torr (preferably 300torr), and an undoped gallium nitride layer is grown on the buffer layer.

Optionally, before the second step, the manufacturing method may further include:

A stress relief layer is grown on the N-type semiconductor layer.

The stress release layer is used to release the stress caused by the lattice mismatch between sapphire and gallium nitride to improve the crystal quality of the active layer, which is conducive to the radiative recombination of electrons and holes in the active layer, and improves the internal quantum of the LED. efficiency, thereby improving the luminous efficiency of the LED.

Accordingly, the active layer is grown on the stress release layer.

Specifically, the material of the stress release layer can be gallium indium aluminum nitride (AlInGaN), which can effectively release the stress caused by the lattice mismatch between sapphire and gallium nitride, improve the crystal quality of the epitaxial wafer, and improve the luminous efficiency of the LED.

Preferably, the molar content of the aluminum component in the stress release layer may be less than or equal to 0.2, and the molar content of the indium component in the stress release layer may be less than or equal to 0.05 to avoid adverse effects.

Further, the thickness of the stress release layer may be 50 nm to 500 nm, preferably 250 nm.

Specifically, growing the stress release layer on the N-type semiconductor layer may include:

The temperature is controlled to be 800°C to 1100°C (preferably 950°C), and the pressure is controlled to be 100torr to 500torr (preferably 300torr), and a stress release layer is grown on the N-type semiconductor layer.

Optionally, before the third step, the manufacturing method may further include:

An electron blocking layer is grown on the active layer.

The electron blocking layer is used to prevent electrons from transitioning to the P-type semiconductor layer for non-radiative recombination with holes, thereby reducing the luminous efficiency of the LED.

Specifically, the material of the electron blocking layer can be P-type doped aluminum gallium nitride (AlGaN), such as _{AlyGa1 -yN} , 0.1<y<0.5.

Further, the thickness of the electron blocking layer may be 50 nm to 150 nm, preferably 100 nm.

Specifically, growing an electron blocking layer on the active layer may include:

The temperature is controlled to be 850°C to 1080°C (preferably 960°C), and the pressure is controlled to be 200torr to 500torr (preferably 350torr), and an electron blocking layer is grown on the active layer.

Preferably, before growing the electron blocking layer on the active layer, the fabrication method may further include:

A low temperature P-type layer is grown on the active layer.

The low temperature P-type layer is used to avoid the precipitation of indium atoms in the active layer caused by the higher growth temperature of the electron blocking layer, which affects the luminous efficiency of the light emitting diode.

Accordingly, the electron blocking layer is grown on the low temperature P-type layer.

Specifically, the material of the low-temperature P-type layer may be the same as that of the P-type semiconductor layer. In this embodiment, the material of the low-temperature P-type layer may be P-type doped gallium nitride.

Further, the thickness of the low-temperature P-type layer may be 10 nm˜50 nm, preferably 30 nm; the doping concentration of the P-type dopant in the low-temperature P-type layer may be 10 ¹⁸ /cm ³ ˜10 ²⁰ /cm ³ , preferably 10 ¹⁹ /cm ³ .

Specifically, growing a low-temperature P-type layer on the active layer may include:

The temperature is controlled to be 600°C to 850°C (preferably 750°C), the pressure is controlled to be 100torr to 600torr (preferably 300torr), and a low temperature P-type layer is grown on the active layer.

Optionally, after step 102, the manufacturing method may further include:

A contact layer is grown on the P-type semiconductor layer.

Specifically, the material of the contact layer can be indium gallium nitride or gallium nitride doped with P-type (eg, magnesium).

Further, the thickness of the contact layer may be 5 nm to 300 nm, preferably 150 nm; the doping concentration of the P-type dopant in the contact layer may be 10 ²¹ /cm ³ to 10 ²² /cm ³ , preferably 5*10 ²¹ cm ^-3 .

Specifically, growing a contact layer on the P-type semiconductor layer may include:

The temperature is controlled to be 850°C to 1050°C (preferably 950°C), and the pressure is controlled to be 100torr to 300torr (preferably 200torr), and a contact layer is grown on the P-type semiconductor layer.

It should be noted that, after the above steps, the temperature is first lowered to 650°C to 850°C (preferably 750°C), and the epitaxial wafer is annealed for 5 minutes to 15 minutes (preferably 10 minutes) in a nitrogen atmosphere , and then the temperature of the epitaxial wafer is lowered to room temperature to end the growth of the epitaxial process.

Controlling temperature and pressure refers to controlling the temperature and pressure in the reaction chamber for growing epitaxial wafers. . High-purity hydrogen, or high-purity nitrogen, or a mixture of hydrogen and nitrogen is used as carrier gas, high-purity ammonia is used as nitrogen source, trimethylgallium or triethylgallium is used as gallium source, and trimethylindium is used as indium source, trimethylaluminum as the aluminum source, silane as the N-type dopant, and MgO as the P-type dopant.

Step 103: Opening a groove extending to the N-type semiconductor on the P-type semiconductor layer.

FIG. 4 is a schematic structural diagram of a light-emitting diode epitaxial wafer obtained after step 103 is performed by the manufacturing method provided by the embodiment of the present invention. Among them, 100 represents a groove. Referring to FIG. 4 , the groove 100 extends from the P-type semiconductor layer 40 to the N-type semiconductor layer 20 .

Specifically, this step 103 may include:

A photoresist with a set pattern is formed on the P-type semiconductor layer by using a photolithography technique, and the photoresist with a set pattern is arranged on an area other than the area where the groove is located;

Using dry etching technology to open a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;

Remove photoresist.

In the specific implementation, when photolithography technology is used to form a photoresist with a set pattern on the P-type semiconductor layer, a layer of photoresist is first laid on the P-type semiconductor layer, and then the photolithography is performed through a mask of a certain pattern. The photoresist is exposed, and finally the exposed photoresist is immersed in a developing solution to obtain a photoresist with a set pattern.

It is easy to know that if the contact layer is grown on the P-type semiconductor layer, the grooves extend from the contact layer to the N-type semiconductor layer.

Step 104: Electron irradiation is performed on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, and the surface of the N-type semiconductor layer in the groove is used for setting the N-type electrode.

In this embodiment, electron irradiation (English: Electron irradiation) uses high-energy electron beams to irradiate the material to cause displacement of crystal atoms and improve the properties of the material.

FIG. 5 is a schematic structural diagram of a light-emitting diode epitaxial wafer during the execution of step 104 of the manufacturing method provided by the embodiment of the present invention. Referring to FIG. 5 , electron irradiation (indicated by arrows in FIG. 5 ) acts on the N-type semiconductor layer within the groove 100 .

In the embodiment of the present invention, by irradiating the surface of the N-type semiconductor layer with the N-type electrode, the microstructure of the crystal of the N-type semiconductor layer is changed, and the shape and quantity of the defects in the N-type semiconductor layer are affected. In this case, more nitrogen vacancies are generated, which increases the nitrogen vacancies in the N-type semiconductor layer, promotes the incorporation of N-type dopants, improves the effectiveness of the incorporation of doping elements, and changes the high impurity state caused by heavy doping. The mobility of carriers is improved, the electrical contact between the N-type electrode and the N-type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the entire light-emitting diode is improved.

Alternatively, the radiation dose of electron irradiation may be 10 ¹⁶ /cm ² to 10 ²² /cm ² , preferably 10 ¹⁹ /cm ² .

If the radiation dose of electron irradiation is less than 10 ¹⁶ /cm ² , the nitrogen vacancies in the N-type semiconductor layer may not be effectively increased due to the fact that the radiation dose of electron irradiation is too small, and the light efficiency improvement effect of the light-emitting diode is not obvious; If the irradiated radiation dose is greater than 10 ²² /cm ² , the main structure of the N-type semiconductor layer crystal may be affected due to too much electrical radiation dose, and on the contrary, the light efficiency of the light-emitting diode will be reduced.

Among them, the radiation dose is the total number of electrons radiated per unit area of the electron-irradiated surface.

Optionally, the temperature of the environment where the N-type semiconductor layer is located during electron irradiation may be 20°C to 150°C, preferably 85°C.

Optionally, the pressure of the environment where the N-type semiconductor layer is located during the electron irradiation may be 5 Torr to 50 Torr, such as 28 Torr.

Optionally, this step 104 may include:

An electron beam provided by a transmission electron microscope (English: Transmission Electron Microscope, TEM for short) is used as a light source to illuminate the surface of the N-type semiconductor layer in the groove.

Directly using existing equipment for electron irradiation is simpler and more convenient to implement.

Specifically, a transmission electron microscope may include an electron gun, a condenser lens, a sample chamber, an objective lens, an intermediate mirror, a transmission mirror, and the like. Among them, the electron gun (English: electronic gun) is used to emit electrons, and is composed of a cathode (English: cathode), a grid (English: guid), and an anode (English: anode).

The cathode is the source of free electrons. In TEM, a heating filament (English: filament) is usually used as a cathode, and the material of the filament can be tungsten or lanthanum hexaboride. When a heating current of several amperes flows through the filament, the filament begins to emit free electrons based on the field electron emission or thermionic emission mechanism. Within a certain range, the amount of free electrons emitted by the filament is proportional to the heating current intensity.

The anode is a metal cylinder with an empty center. The anode is below the cathode. When an accelerating voltage of tens of kilovolts or hundreds of kilovolts is applied to the anode, it will have a strong gravitational effect on the free electrons emitted by the heating of the cathode, and make them change from a disordered state to an orderly directional movement, and at the same time Accelerate the free electrons to a certain speed to form a beam to the target surface of the anode. The electron beam current moving on the axis will pass through the circular hole in the center of the anode and shoot out of the electron gun, becoming the light source for illuminating the sample.

The grid is located between the cathode and anode, near the top of the filament. The grid is a cap-shaped metal object with a small hole in the center for the electron beam to pass through. A negative voltage of 0 to 1000V is applied to the grid (for the cathode), this negative voltage (called grid bias) can make the electron beam converge to the central axis, and at the same time, it also has a negative effect on the emission of free electrons on the filament. certain regulatory inhibition.

When the transmission electron microscope is working, under the action of the filament power supply, the current flows through the filament cathode, causing the filament to heat up. When the heating of the filament reaches above 2500°C, the filament generates free electrons, and the generated free electrons escape from the surface of the filament. At the same time, the accelerating voltage makes the surface of the anode gather dense positive charges, forming a strong positive electric field. Under the action of this positive electric field, free electrons fly out of the electron gun. In addition, adjusting the magnitude of the grid bias voltage can control the magnitude of the electron beam flux.

In practical applications, an electron beam provided by a TEM of 200 kiloelectron volts (English: kilo electron volt, keV for short) can be used as a light source. Further, the power source of the TEM can use a high voltage source of up to 100,000 volts to 300,000 volts. By controlling the heating current of the cathode in the TEM, the accelerating voltage of the anode in the TEM, the grid bias voltage of the grid in the TEM, and the duration of the electron irradiation, the radiation dose of the electron irradiation is 10 ¹⁶ /cm ² -10 ²² /cm ² .

Preferably, the diameter of the electron beam may be 8 μm˜30 μm, preferably 19 μm.

If the diameter of the electron beam is less than 8μm, the electron beam may be too concentrated because the diameter of the electron beam is too small, which will damage the main structure of the N-type semiconductor layer and affect the luminous efficiency of the LED; if the diameter of the electron beam is greater than 30μm, Then, the electron beam may be too scattered due to the large diameter of the electron beam, which cannot effectively increase the nitrogen vacancies in the N-type semiconductor layer, and the light efficiency improvement effect of the light emitting diode is not obvious.

Optionally, after step 104, the manufacturing method may further include:

The N-type semiconductor layer in the groove is annealed.

Partial defects and impurity states are eliminated by annealing treatment.

Optionally, the temperature of the annealing treatment may be 700° C.˜900° C., which achieves a better effect.

Optionally, the contact layer may be in a nitrogen atmosphere during the annealing treatment, which achieves a better effect.

Preferably, the vacuum degree of the nitrogen atmosphere can be 10 ^-8 Torr to 10 ^-6 Torr, which is better to achieve.

Optionally, the duration of the annealing treatment may be 15 min to 50 min, which achieves a better effect.

In an implementation manner of this embodiment, when the surface of the P-type semiconductor layer is used for arranging the P-type electrode, the manufacturing method may further include:

The surface of the P-type semiconductor layer is irradiated with electrons to increase nitrogen vacancies in the P-type semiconductor layer, and the P-type semiconductor layer is a P-type doped nitride.

By irradiating the surface of the P-type semiconductor layer with electrons, the microstructure of the crystal of the P-type semiconductor layer is changed, the shape and quantity of the defects in the P-type semiconductor layer are affected, and more nitrogen vacancies are generated without changing the proportion of nitrogen elements. , increase the nitrogen vacancies in the P-type semiconductor layer, promote the incorporation of P-type dopants, improve the effectiveness of the incorporation of doping elements, change the high impurity state caused by heavy doping, and improve the mobility of carriers, The electrical contact between the P-type electrode and the P-type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the entire light-emitting diode is improved.

In practical applications, electron irradiation can be performed on the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove at the same time, so as to save process steps, facilitate implementation, and reduce implementation costs. The surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove can also be irradiated with electrons respectively, for example, after the P-type semiconductor layer is grown, the surface of the P-type semiconductor layer is irradiated with electrons, and then the surface of the P-type semiconductor layer is irradiated with electrons. A groove extending to the N-type semiconductor layer is formed on the type semiconductor layer, and the surface of the N-type semiconductor layer in the groove is irradiated with electrons.

Specifically, the parameters for irradiating the surface of the P-type semiconductor layer with electrons may be the same as those for irradiating the surface of the N-type semiconductor layer in the groove, for example, the radiation dose of the electron irradiation is 10 ¹⁶ /cm ² ~ 10 ²² /cm ² .

Optionally, in the above implementation manner, the manufacturing method may further include:

After the surface of the P-type semiconductor layer is irradiated with electrons, the P-type semiconductor layer is subjected to annealing treatment.

Specifically, the parameters for annealing the P-type semiconductor layer may be the same as the parameters for annealing the N-type semiconductor layer in the groove, for example, the annealing temperature is 700°C to 900°C.

In another implementation manner of this embodiment, when the surface of the contact layer is used for arranging P-type electrodes, the manufacturing method may further include:

The surface of the contact layer is irradiated with electrons to increase nitrogen vacancies in the contact layer.

By irradiating the surface of the contact layer with electrons, the microstructure of the crystal of the contact layer is changed, the shape and quantity of defects in the contact layer are affected, and more nitrogen vacancies are generated without changing the proportion of nitrogen elements, increasing the amount of nitrogen in the contact layer. Nitrogen vacancies, promote the incorporation of P-type dopants, improve the effectiveness of the incorporation of doping elements, change the high impurity state due to heavy doping, improve the mobility of carriers, and improve the electrical contact between the electrode and the contact layer , reduce the series resistance and improve the light efficiency of the entire LED.

In practical applications, the surface of the contact layer and the surface of the N-type semiconductor layer in the groove can be irradiated with electrons at the same time, so as to save process steps, facilitate implementation, and reduce implementation costs. It is also possible to irradiate the surface of the contact layer and the surface of the N-type semiconductor layer in the groove respectively, for example, after the growth of the contact layer, the surface of the contact layer is irradiated with electrons, and then the opening on the contact layer extends to the N-type semiconductor layer. The groove of the N-type semiconductor layer is irradiated with electrons on the surface of the N-type semiconductor layer in the groove.

Specifically, the parameters of the electron irradiation on the surface of the contact layer can be the same as the electron irradiation parameters on the surface of the N-type semiconductor layer in the groove, for example, the radiation dose of the electron irradiation is 10 ¹⁶ /cm ² -10 ²² /cm ² .

Optionally, in the above implementation manner, the manufacturing method may further include:

After irradiating the surface of the contact layer with electrons, the contact layer is annealed.

Specifically, the parameters for annealing the contact layer may be the same as the parameters for annealing the N-type semiconductor layer in the groove, for example, the annealing temperature is 700°C to 900°C.

A specific implementation of the preparation method shown in Figure 1 may include:

Step 201 : control the temperature to be 1100° C. and the pressure to be 300 torr, and grow an N-type semiconductor layer with a thickness of 3 μm on the substrate. The doping concentration of the N-type dopant in the N-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 202 : growing an active layer on the N-type semiconductor layer; the active layer includes 9 quantum wells and 9 quantum barriers grown alternately; the thickness of the quantum wells is 3 nm, the growth temperature of the quantum wells is 770° C., and the The growth pressure is 300torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900°C, and the growth pressure of the quantum barrier is 300torr.

Step 203 : controlling the temperature to be 960° C. and the pressure of 200 torr, growing a P-type semiconductor layer with a thickness of 450 nm on the active layer, and the doping concentration of the P-type dopant in the P-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 204: Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Step 205: Perform electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, and the radiation dose of the electron irradiation is 10 ¹⁶ /cm ² .

The obtained epitaxial wafer is made into a chip, and the light efficiency of the chip is increased by 3% to 5% compared with that the N-type semiconductor layer in the groove is not irradiated with electrons.

Another specific implementation of the preparation method shown in Figure 1 may include:

Step 301 : control the temperature to 1100° C. and the pressure to 300 torr, grow an N-type semiconductor layer with a thickness of 3 μm on the substrate, and the doping concentration of the N-type dopant in the N-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 302 : growing an active layer on the N-type semiconductor layer; the active layer includes 9 quantum wells and 9 quantum barriers grown alternately; the thickness of the quantum wells is 3 nm, the growth temperature of the quantum wells is 770° C., and the The growth pressure is 300torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900°C, and the growth pressure of the quantum barrier is 300torr.

Step 303 : control the temperature to be 960° C. and the pressure to be 200 torr, and grow a P-type semiconductor layer with a thickness of 450 nm on the active layer. The doping concentration of the P-type dopant in the P-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 304: Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Step 305: Perform electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, and the radiation dose of the electron irradiation is 10 ¹⁹ /cm ² .

The obtained epitaxial wafer is made into a chip. Compared with the N-type semiconductor layer in the groove without electron irradiation, the light efficiency of the chip is improved by 5% to 7%.

Another specific implementation of the preparation method shown in Figure 1 may include:

Step 401 : control the temperature to be 1100° C. and the pressure to be 300 torr, and grow an N-type semiconductor layer with a thickness of 3 μm on the substrate. The doping concentration of the N-type dopant in the N-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 402 : growing an active layer on the N-type semiconductor layer; the active layer includes 9 quantum wells and 9 quantum barriers grown alternately; the thickness of the quantum wells is 3 nm, the growth temperature of the quantum wells is 770° C., and the The growth pressure is 300torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900°C, and the growth pressure of the quantum barrier is 300torr.

Step 403 : controlling the temperature to be 960° C. and the pressure of 200 torr, growing a P-type semiconductor layer with a thickness of 450 nm on the active layer, and the doping concentration of the P-type dopant in the P-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 404: Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Step 405: Perform electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, and the radiation dose of the electron irradiation is 10 ²² /cm ² .

The obtained epitaxial wafer is made into a chip. Compared with the N-type semiconductor layer in the groove without electron irradiation, the light efficiency of the chip is increased by 2% to 3%.

Another specific implementation of the preparation method shown in Figure 1 may include:

Step 501 : control the temperature to be 1100° C. and the pressure to be 300 torr, and grow an N-type semiconductor layer with a thickness of 3 μm on the substrate. The doping concentration of the N-type dopant in the N-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 502 : growing an active layer on the N-type semiconductor layer; the active layer includes 9 quantum wells and 9 quantum barriers grown alternately; the thickness of the quantum wells is 3 nm, the growth temperature of the quantum wells is 770° C., and the The growth pressure is 300torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900°C, and the growth pressure of the quantum barrier is 300torr.

Step 503 : control the temperature to be 960° C. and the pressure to be 200 torr, and grow a P-type semiconductor layer with a thickness of 450 nm on the active layer. The doping concentration of the P-type dopant in the P-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 504: Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Step 505 : irradiating the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove with electrons to increase nitrogen vacancies in the P-type semiconductor layer and the N-type semiconductor layer in the groove, and the radiation of electron irradiation The dose was 10 ¹⁹ /cm ² .

The obtained epitaxial wafer is made into a chip. Compared with the P-type semiconductor layer and the N-type semiconductor layer in the groove without electron irradiation, the light efficiency of the chip is improved by 5% to 7%.

A specific implementation of the preparation method shown in Figure 1 may include:

Step 601 : control the temperature to be 1100° C. and the pressure to be 300 torr, and grow an N-type semiconductor layer with a thickness of 3 μm on the substrate. The doping concentration of the N-type dopant in the N-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 602 : growing an active layer on the N-type semiconductor layer; the active layer includes 9 quantum wells and 9 quantum barriers grown alternately; the thickness of the quantum wells is 3 nm, the growth temperature of the quantum wells is 770° C., and the The growth pressure is 300torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900°C, and the growth pressure of the quantum barrier is 300torr.

Step 603 : control the temperature to be 960° C. and the pressure to be 200 torr, and grow a P-type semiconductor layer with a thickness of 450 nm on the active layer. The doping concentration of the P-type dopant in the P-type semiconductor layer is 5*10 ¹⁸ cm ⁻³ .

Step 604 : control the temperature to be 950° C. and the pressure to be 200 torr, and grow a contact layer with a thickness of 150 nm on the P-type semiconductor layer.

Step 605: Opening a groove extending to the N-type semiconductor layer on the contact layer.

Step 606: Perform electron irradiation on the surface of the contact layer and the N-type semiconductor layer in the groove to increase nitrogen vacancies in the contact layer and the N-type semiconductor layer in the groove, and the radiation dose of the electron irradiation is 10 ¹⁹ /cm ² .

The obtained epitaxial wafer is made into a chip. Compared with the contact layer and the N-type semiconductor layer in the groove without electron irradiation, the light efficiency of the chip is improved by 8% to 10%.

The embodiment of the present invention provides a light emitting diode epitaxial wafer, which is suitable for being fabricated by the fabrication method shown in FIG. 1 . FIG. 6 is a schematic structural diagram of a light emitting diode epitaxial wafer according to an embodiment of the present invention. 6 , the light-emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, an active layer 30 and a P-type semiconductor layer 40. The N-type semiconductor layer 20, the active layer 30 and the P-type semiconductor layer 40 are sequentially stacked on on the substrate 10 . The P-type semiconductor layer 40 is provided with a groove 100 extending to the N-type semiconductor layer 20 , and the surface of the N-type semiconductor layer 20 in the groove 100 is used for arranging an N-type electrode.

In this embodiment, the surface of the N-type semiconductor layer 20 in the groove 100 is the surface treated by electron irradiation.

Optionally, as shown in FIG. 6 , the light-emitting diode epitaxial wafer may further include a buffer layer 51 , and the buffer layer 51 is disposed between the substrate 10 and the N-type semiconductor layer 20 .

Preferably, as shown in FIG. 6 , the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 52 , and the undoped gallium nitride layer 52 is disposed between the buffer layer 51 and the N-type semiconductor layer 20 .

Optionally, as shown in FIG. 6 , the light emitting diode epitaxial wafer may further include a stress release layer 60 , and the stress release layer 60 is disposed between the N-type semiconductor layer 20 and the active layer 30 .

Optionally, as shown in FIG. 6 , the light-emitting diode epitaxial wafer may further include an electron blocking layer 71 , and the electron blocking layer 71 is disposed between the active layer 30 and the P-type semiconductor layer 40 .

Preferably, as shown in FIG. 6 , the light-emitting diode epitaxial wafer may further include a low-temperature P-type layer 72 , and the low-temperature P-type layer 72 is disposed between the active layer 30 and the electron blocking layer 71 .

Optionally, as shown in FIG. 6 , the light-emitting diode epitaxial wafer may further include a contact layer 80 , and the contact layer 80 is disposed on the P-type semiconductor layer 40 .

In an implementation manner of this embodiment, when the surface of the contact layer is used for arranging the P-type electrode, the surface of the contact layer may be a surface treated by electron irradiation.

In another implementation manner of this embodiment, when the surface of the P-type semiconductor layer is used for disposing the P-type electrode, the surface of the P-type semiconductor layer 40 may be a surface treated by electron irradiation.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (4)

1. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:

providing a substrate;

sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate, wherein the N-type semiconductor layer is N-type doped nitride, and the P-type semiconductor layer is P-type doped nitride;

forming a groove extending to the N-type semiconductor on the P-type semiconductor layer;

simultaneously carrying out electron irradiation on the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the P-type semiconductor layer and the N-type semiconductor layer in the groove, wherein the surface of the N-type semiconductor layer in the groove is used for arranging an N-type electrode, the P-type semiconductor layer is used for arranging a P-type electrode, and the radiation dose of the electron irradiation is 10¹⁶/cm²～10²²/cm²The doping concentration of the P type dopant in the P type semiconductor layer and the doping concentration of the N type dopant in the N type semiconductor layer are 10¹⁸cm^-3～10¹⁹cm^-3；

And annealing the P-type semiconductor layer and the N-type semiconductor layer in the groove.

2. The method for manufacturing according to claim 1, wherein the step of irradiating electrons to the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove comprises:

and irradiating the surface of the N-type semiconductor layer in the groove by using an electron beam provided by a transmission electron microscope as a light source.

3. The method of claim 2, wherein the diameter of the electron beam is 8 μm to 30 μm.

4. Hair-like hairThe light-emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, the N-type semiconductor layer is N-type doped nitride, the P-type semiconductor layer is P-type doped nitride, a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, an N-type electrode is arranged on the surface of the N-type semiconductor layer in the groove, the P-type semiconductor layer is used for arranging a P-type electrode, the light-emitting diode epitaxial wafer is characterized in that the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove are surfaces subjected to electron irradiation and annealing treatment, and the radiation dose of the electron irradiation is 10¹⁶/cm²～10²²/cm²The doping concentration of the P type dopant in the P type semiconductor layer and the doping concentration of the N type dopant in the N type semiconductor layer are 10¹⁸cm^-3～10¹⁹cm^-3。

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