CN109256422B - A semiconductor device and its manufacturing method and electronic device - Google Patents

Abstract

The present invention provides a semiconductor device, a method for manufacturing the same, and an electronic device, including: a device substrate, including a cell region and a terminal guard ring region surrounding the cell region; a first injection region, disposed on the device substrate The backside of the TP is opposite to the terminal guard ring area; the second injection area is arranged on the backside and opposite to the cell area, the first injection area surrounds the second injection area; the third injection area, It is arranged in the first implantation region and close to the second implantation region, wherein the doping concentration of the second implantation region and the third implantation region are both greater than the doping concentration of the first implantation region.

Description

A semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

How to improve the reverse turn-off safe working area of an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT for short) device has always been a difficulty and focus in the design of IGBT devices. The most common reverse turn-off failure of IGBT devices occurs in the edge cell (cell) of the device, and the mechanism is mainly triggered by the latch-up effect, resulting in device failure. From the perspective of the structure of the device, the front cell area is responsible for the on and off of the current, the terminal ring area is responsible for the lateral withstand voltage of the device, and the back electrode of the device has no pattern, which is responsible for the on and off of the current. break. Therefore, the current channel areas on the front side and the back side of the device are inconsistent, and the back side area is larger than the front side area (ie, the area of the cell). During the shutdown process of the device, the corresponding in-body hole carriers under the terminal guard ring will converge and flow out from the edge cell (the cell closest to the terminal guard ring), and the collected hole current is large enough , the latch-up effect of the edge cells is triggered, resulting in device failure, as shown in Figure 1, where the arrow curve in Figure 1 shows the reverse turn-off current path. Moreover, the higher the voltage level of the IGBT device, the larger the terminal protection ring area, and the failure rate of the edge cell will also be greatly improved.

Therefore, in order to solve the above-mentioned technical problems, the present invention proposes a new method for manufacturing a semiconductor device.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In view of the deficiencies of the prior art, one aspect of the present invention provides a semiconductor device, comprising:

a device substrate, including a cell region and a terminal guard ring region surrounding the cell region;

a first implantation region, disposed on the backside of the device substrate and opposite to the terminal guard ring region;

a second injection area, disposed on the backside and opposite to the cell area, the first injection area surrounds the second injection area;

A third implantation region is disposed in the first implantation region and close to the second implantation region, wherein the doping concentrations of the second implantation region and the third implantation region are both greater than those of the first implantation region doping concentration.

Exemplarily, the first implantation region has a polygonal shape, and the third implantation region is located in a region other than at least one corner of the first implantation region.

Exemplarily, the first implantation region includes four corners, and the third implantation region is located in a region other than the four corners of the first implantation region.

Exemplarily, the third injection region includes a plurality of strip-shaped injection regions spaced along the radial direction of the first injection region, wherein the extension direction of the strip-shaped injection regions is close to the strip-shaped injection region. The extending direction of the edge of the second implanted region is parallel; and/or,

The third implantation region includes a plurality of bulk implantation regions, and the bulk implantation regions are arranged at intervals along a part of the edge of the second implantation region.

Exemplarily, the second implantation region and the third implantation region have the same doping concentration.

Exemplarily, the second injection region is a polygon with one corner missing, and the third injection region is also located on the missing corner of the polygon;

The device substrate also includes a gate pad region outside the third implant region on the missing corner.

Exemplarily, the first implantation region, the second implantation region and the third implantation region have the same junction depth, and/or the first implantation region, the second implantation region and the The third implanted region has the same conductivity type.

Exemplarily, the second implantation region and the third implantation region are heavily doped implantation regions, and the first implantation region is a lightly doped implantation region.

Exemplarily, the device substrate further includes a transition region, the transition region surrounds the cell region and is located between the terminal guard ring region and the cell region, wherein the first injection region is further connected to the cell region. The transition area is opposite to the transition area, and the third injection area is opposite to the transition area.

Exemplarily, the semiconductor device is an IGBT device.

Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:

providing a device substrate, the device substrate including a cell region and a terminal guard ring region surrounding the cell region;

forming a first implantation region, wherein the first implantation region is formed on the backside of the device substrate and is opposite to the terminal guard ring region;

forming a second implantation region and a third implantation region, wherein the second implantation region is formed on the back surface and opposite to the cell region, and the third implantation region is formed in and adjacent to the first implantation region The doping concentrations of the second implantation region, the second implantation region and the third implantation region are all greater than the doping concentration of the first implantation region.

Exemplarily, the method of forming the first implantation region, the second implantation region and the third implantation region includes:

performing a first ion implantation on the backside of the device substrate to form a first implanted region in the device substrate;

forming a patterned mask layer on the backside of the device substrate, the mask layer exposing the region of the device substrate where the second implantation region and the third implantation region are to be formed;

Using the mask layer as a mask, a second ion implantation is performed to form the second implantation region and the third implantation region;

The mask layer is removed.

Exemplarily, after removing the mask layer, an annealing process is further included to activate the dopant ions in the first implantation region, the second implantation region and the third implantation region.

Exemplarily, the first injection region has a polygonal ring shape, and the third injection region is located in a region other than at least one corner of the first injection region.

Exemplarily, the first implantation region includes four corners, and the third implantation region is located in a region other than the four corners of the first implantation region.

Exemplarily, the third injection region includes a plurality of strip-shaped injection regions spaced along the radial direction of the first injection region, wherein the extension direction of the strip-shaped injection regions is close to the strip-shaped injection region. The extending direction of the edge of the second implanted region is parallel; and/or,

The third implantation region includes a plurality of bulk implantation regions, and the bulk implantation regions are arranged at intervals along a part of the edge of the second implantation region.

Exemplarily, the second injection region is a polygon with one corner missing, and the third injection region is also located on the missing corner of the polygon;

The device substrate also includes a gate pad region outside the third implant region on the missing corner.

Exemplarily, the first implantation region, the second implantation region and the third implantation region have the same junction depth, and/or the first implantation region, the second implantation region and the The third implanted region has the same conductivity type.

Exemplarily, the second implantation region and the third implantation region are heavily doped implantation regions, and the first implantation region is a lightly doped implantation region.

Exemplarily, the device substrate further includes a transition region, the transition region surrounds the cell region and is located between the terminal guard ring region and the cell region, wherein the first injection region is further connected to the cell region. The transition area is opposite to the transition area, and the third injection area is opposite to the transition area.

Exemplarily, the semiconductor device is an IGBT device.

Another aspect of the present invention provides an electronic device including the aforementioned semiconductor device.

The semiconductor device of the present invention includes a first implantation region disposed in the device substrate and close to the backside and opposite to the terminal guard ring region, disposed in the device substrate and close to the backside and the element a second implantation region opposite to the cell region, and a third implantation region disposed in the first implantation region and close to the second implantation region, wherein the doping concentration of the second implantation region is greater than that of the first implantation region The doping concentration of the implanted region, the doping concentration of the third implanted region is greater than the doping concentration of the first implanted region, and the doping concentration is set lower in the region opposite to the terminal guard ring region far from the cell region In the first injection region, the gain is further reduced, the large injection effect is weakened, and the reverse turn-off safe working region is increased, and a third injection with high doping concentration is set in the region opposite to the terminal guard ring region near the cell region. region, the deterioration of the on-voltage drop Vcesat can be avoided. Therefore, the semiconductor device of the present invention has high performance and reliability.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

FIG. 1 shows a schematic cross-sectional view of an IGBT device according to an existing embodiment;

FIG. 2A shows a top view of the backside of an IGBT device according to another existing embodiment;

Fig. 2B shows a schematic partial cross-sectional view of the IGBT device obtained along the section line AA' in Fig. 2A;

FIG. 3A shows a top view of the backside of an IGBT device according to an embodiment of the present invention;

FIG. 3B shows a back top view of an IGBT device according to another embodiment of the present invention;

Fig. 3C shows a schematic partial cross-sectional view of the IGBT device obtained along the section line AA' in Fig. 3A, wherein the arrow curve in Fig. 3C shows the reverse turn-off current path;

4A to 4C show schematic cross-sectional views of the device obtained by the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention;

5 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and corresponding dimensions of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

For a thorough understanding of the present invention, detailed steps will be presented in the following description in order to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

At present, for the improvement of the safe working area of reverse turn-off of IGBT devices, the mainstream solution is to introduce the backside patterning process, and keep the P+ injection area on the backside under the front cell area, that is, the injection of the collector area. Under the premise that the concentration remains unchanged, reduce the injection concentration of the corresponding backside P+ injection area under the overall terminal guard ring area, for example, reduce the injection concentration to the P- injection area, wherein the gate pad area on one corner of the cell area makes this area. The gain is reduced and the large injection effect is weakened. During the turn-off process of the device, the corresponding hole carrier concentration under the terminal guard ring decreases, reducing the hole current collected and flowing out through the edge cells from the source, increasing the reverse turn-off safe working area of the device, As shown in Figures 2A and 2B.

However, the disadvantage of this solution is that the P+ implantation concentration on the corresponding backside under the overall terminal guard ring region is reduced, which will lead to deterioration of the overall turn-on voltage drop Vcesat of the device.

In order to solve the aforementioned technical problems, the present invention provides a semiconductor device, which mainly includes:

a device substrate, including a cell region and a terminal guard ring region surrounding the cell region;

a first implantation region, disposed on the backside of the device substrate and opposite to the terminal guard ring region;

a second injection area, disposed on the backside and opposite to the cell area, the first injection area surrounds the second injection area;

A third implantation region is disposed in the first implantation region and close to the second implantation region, wherein the doping concentrations of the second implantation region and the third implantation region are both greater than those of the first implantation region doping concentration.

The semiconductor device of the present invention includes a first implantation region disposed in the device substrate and close to the backside and opposite to the terminal guard ring region, disposed in the device substrate and close to the backside and the element a second implantation region opposite to the cell region, and a third implantation region disposed in the first implantation region and close to the second implantation region, wherein the doping concentration of the second implantation region is greater than that of the first implantation region The doping concentration of the implanted region, the doping concentration of the third implanted region is greater than the doping concentration of the first implanted region, and the doping concentration is set lower in the region opposite to the terminal guard ring region far from the cell region In the first injection region, the gain is further reduced, the large injection effect is weakened, and the reverse turn-off safe working region is increased, and a third injection with high doping concentration is set in the region opposite to the terminal guard ring region near the cell region. region, the deterioration of the on-voltage drop Vcesat can be avoided. Therefore, the semiconductor device of the present invention has high performance and reliability.

Example 1

The semiconductor device of the present invention will be described in detail below with specific reference to FIGS. 3A to 3C . 3A shows a top view of the back side of the IGBT device according to an embodiment of the present invention; FIG. 3B shows a top view of the back side of the IGBT device according to another embodiment of the present invention; A schematic partial cross-sectional view of the obtained IGBT device, wherein the arrow curve in FIG. 3C shows the reverse turn-off current path.

Specifically, as shown in FIGS. 3A to 3C , in an example, the semiconductor device of the present invention may be an IGBT device or other semiconductor devices. In this embodiment, the IGBT device is mainly used as an example. methods are explained and illustrated.

As an example, as shown in FIG. 3C , the semiconductor device of the present invention includes a device substrate 300 including a front surface and a back surface opposite to the front surface. The front surface of the device substrate includes a cell region 31 and a terminal guard ring region 33 surrounding the cell region 31 .

The device substrate 300 is a bulk silicon substrate, which may be at least one of the following mentioned materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, It also includes multilayer structures composed of these semiconductors, or is silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and insulators On germanium (GeOI) and so on. Further, the substrate may also be an N-type substrate or a P-type substrate. In this embodiment, the device substrate 300 is preferably an N-type lightly doped substrate (N-substrate).

In one example, several isolation structures are formed on the front surface of the device substrate in the cell region, and the isolation structures are shallow trench isolation (STI) structures or localized silicon oxide (LOCOS) isolation structures. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate.

In one example, the cell region 31 includes a gate structure disposed on the front surface of the device substrate, an emitter region in contact with the gate structure, an N+ emitter region connected with the emitter region, and a P-type body connected with the emitter region The N+ emitter region is located in the P-type body region, and the P-type body region is located in the N- (N-type lightly doped) device substrate, or an N-drift region is provided in the device substrate , the P-type body region is located in the N-drift region, and the emitter is arranged on the emitter region. In each cell, a gate structure is formed on the surfaces of the two N+ emitter regions and the channel region, the gate structure includes a gate layer and a gate dielectric layer under the gate layer, through A gate dielectric layer opposes the N+ emitter and channel regions.

In one example, as shown in FIG. 3C , the device substrate 300 further includes a transition region 32 , the transition region 32 is disposed on the front surface of the device substrate 300 , and the transition region 32 surrounds the cell region 31 and It is located between the terminal guard ring region 33 and the cell region 31 .

Exemplarily, the transition region includes an equalization ring 321 formed in the device substrate 300, and the top surface of the equalization ring 321 is flush with the front surface of the device substrate 300, and the equalization ring 321 is flush with the front surface of the device substrate 300. The ring 321 is connected to the cell and surrounds the cell area. Since the allelic ring is connected to the cell during manufacture, it is equipotential with the emitter or cathode of the cell. The allelic ring has the following functions. First, because the outermost cell is extended and the junction depth is deeper, the curvature effect of the outermost cell is reduced, the electric field strength of the outermost cell is reduced, and the withstand voltage of the device is strengthened; The transition region also increases the hole extraction path of the bipolar gated device when it is turned off, thereby improving the reliability of the device when it is turned off. Third, because the transition region is wider, it can be used for gate control during layout design. The gate traces of the power devices provide layout space.

In one example, the equipotential ring 321 has a conductivity type opposite to that of the device substrate or the drift region. For example, the device substrate is an N-type substrate, then the equipotential ring 321 is a P-type equipotential ring. , especially the P+-type allelic ring.

In an example, on the front surface of the device substrate 300 opposite to the equipotential ring 321, a field oxygen and a field plate located on the field oxygen are further disposed in sequence, wherein the material of the field plate may include polysilicon or The metal may also be composed of polysilicon and metal stacked from bottom to top, and a dielectric layer may also be arranged between the metal and the polysilicon, wherein the metal may include aluminum, copper, gold, tin, etc. or their alloys.

In one example, a body lead-out region is further provided in the body region of the cell region. For example, if the body region is a P-type body region, the body lead-out region is heavily P-type doped. An allelic ring lead-out region is formed in the allelic ring, the allelic ring lead-out region has the same conductivity type as the allelic ring, and the allelic ring lead-out region has a higher doping concentration than the allelic ring.

Exemplarily, a metal interconnection structure electrically connected to the body lead-out region and the equipotential ring lead-out region is further formed above the gate structure on the front surface of the device substrate, for example, including contact holes and interconnections Metal interconnect structure of metal layers, the metal may include copper, aluminum or other metal materials.

In an example, as shown in FIG. 3C , at least one field limiting ring 331 is formed in the device substrate 300 of the terminal guard ring region 33 , and the field limiting ring 331 surrounds the element. The cell region 31 is further located outside the transition region. The field confinement ring 331 can be formed by, for example, ion implantation, and the field confinement ring has a conductivity type opposite to that of the device substrate. For example, the device substrate 300 is an N-type substrate, especially The N-type lightly doped substrate, the field confinement ring 331 is a P-type field confinement ring, such as a P-type heavily doped field confinement ring.

Exemplarily, the number of the field limiting loops 331 is reasonably selected according to the actual device requirements, for example, it may include 1, 2, 3 to n field limiting loops.

Exemplarily, the field limiting ring 331 and the equipotential ring 321 are disposed in the device substrate 300 at intervals.

Exemplarily, several field plate structures are also provided on the front side of the device substrate of the terminal guard ring region 33, wherein the number of field plate structures can be set according to the number of field confinement rings, for example, in each field plate structure. One of the field plate structures is disposed on both sides of the field limiting ring 331, wherein each of the field plate structures includes a field oxygen and a field plate located on the surface of the field oxygen, wherein the field oxygen generally includes silicon oxide, The material of the field plate can include polysilicon or metal, and can also include polysilicon and metal stacked from bottom to top. A dielectric layer can also be provided between the metal and the polysilicon, wherein the metal can include aluminum, copper, gold, Tin etc or their alloys.

In one example, several interconnect structures electrically connected to the field confinement ring 331 are further provided on the front surface of the device substrate 300 , and the interconnect structures include contacts between adjacent field plate structures A hole and a metal layer over a contact hole connecting the surface of the field limiting ring.

Exemplarily, a channel stop region is further provided in the device substrate where the edge of the terminal guard ring region is far from the cell region. For example, the channel stop region has a conductivity type opposite to that of the field limiting ring. In two implementations, the conductivity type of the channel stop region is N type, especially N+ type.

In one example, as shown in FIGS. 3A and 3B , the device substrate 300 further includes a gate pad region, the gate pad region is disposed on the front side of the device substrate, the The gate pad region includes a pad that is electrically connected to the gate through an interconnect structure.

In one example, the gate pad region is located on one corner of the cell region when viewed from a top view.

It is worth mentioning that the above description about the cell region, transition region and terminal guard ring region included in the device substrate is only an example, and the cell region, transition region and terminal region of any other structure type well known to those skilled in the art are used as examples. Guard ring regions may also be suitable for this application.

Further, as shown in FIGS. 3A to 3C , the semiconductor device of the present invention further includes a first implantation region 301 , and the first implantation region 301 is disposed on the backside of the device substrate 300 and is opposite to the terminal guard ring region 33 .

Exemplarily, the first injection region 301 is used as the collector region of the IGBT device, especially the collector region of the terminal guard ring region of the IGBT device.

In one example, the first implanted region 301 has a conductivity type opposite to that of the device substrate 300 or the drift region formed on the front side of the device substrate 300. For example, the device substrate 300 is N-type, so the The first implantation region 301 is P-type. In this embodiment, preferably, the first implantation region 301 is P-type lightly doped, that is, the first implantation region is a P-implantation region, and the The doping concentration can be any suitable doping concentration range known to those skilled in the art, and is not specifically limited.

In one example, the junction depth of the first implanted region 301 may be in the range of 0.2 μm˜0.4 μm, or other suitable ranges, and the junction depth refers to the bottom and back surfaces of the first implanted region 301 in the device substrate 300 . the distance between.

Further, if the device substrate 300 includes a transition region, the first implantation region 301 is disposed on the backside of the device substrate 300 opposite to the terminal guard ring region and the transition region, that is, on the device substrate The first injection region 301 is formed on the backside of 300 opposite to the terminal guard ring region and the transition region.

Exemplarily, the device substrate includes a gate pad region, the gate pad region is located on one corner of the cell region, and the first implantation region 301 is also provided on the backside of the device substrate and The part of the device substrate 300 opposite to the gate pad region is shown in FIG. 3A and FIG. 3B .

Exemplarily, the semiconductor device of the present invention further includes a second implantation region 302 , the second implantation region 302 is disposed on the backside of the device substrate 300 and is opposite to the cell region 31 , and the first implantation region 301 surrounds the second injection region 302 .

In one example, the second implantation region has the same conductivity type as the first implantation region, for example, the conductivity types of the second implantation region 302 and the first implantation region 301 are both P-type.

In one example, the doping concentration of the second implanted region 302 is greater than the doping concentration of the first implanted region 301 , for example, the first implanted region is a P-type lightly doped implanted region (P-implanted region ), and the second implantation region 302 is a P-type heavily doped implantation region (P+ implantation region).

Exemplarily, since the first implantation region 301 is arranged opposite to the terminal guard ring region 33 and the transition region 32, and the second implantation region 302 is arranged opposite to the cell region 31, therefore, the first implantation region formed on the backside of the device substrate 300 is formed. An implantation region 301 surrounds the second implantation region 302, as shown in 3A, 3B and 3C.

In an example, as shown in FIG. 3A , FIG. 3B and FIG. 3C , it further includes a third implantation region 303 disposed in the first implantation region 301 and close to the second implantation region 302 , wherein the first implantation region 303 is The doping concentration of the three implanted regions 303 is greater than the doping concentration of the first implanted region 301 .

It is worth mentioning that the fact that the third implantation region 303 is close to the second implantation region means that the distance from the third implantation region 303 to the adjacent inner edge of the first implantation region 301 is smaller than that of the third implantation region. 303 is the distance from the adjacent outer edge of the first implanted region 301 .

Optionally, the third implantation region 303 has the same conductivity type as the first implantation region 301 and the second implantation region 302 , for example, both are P-type.

Exemplarily, the second implantation region 302 and the third implantation region 303 may both be P-type heavily doped implantation regions, for example, the second implantation region 302 and the third implantation region 303 have substantially the same doping concentration .

In one example, the doping concentration of the third implantation region 303 may be higher than that of the first implantation region 301 , and the doping concentration of the second implantation region 302 may be higher than that of the third implantation region 303 .

Exemplarily, the first implanted region 301, the second implanted region 302 and the third implanted region 303 have the same junction depth, that is, the three implanted regions are located at the same depth in the device substrate, as shown in FIG. It can be seen from 3C that the third implantation region 303 penetrates the first implantation region 301 .

Exemplarily, the first injection region has a polygonal ring shape, and the third injection region 303 is located in a region other than at least one corner of the first injection region. For example, as shown in FIG. 3A and FIG. 3B , the The first implantation region 301 includes four corners, and each of the four corners has an arc-shaped inner edge and an outer edge. The third implantation region 303 is located in the regions other than the four corners of the first implantation region 301 , that is, in the region of the backside of the device substrate opposite to the terminal guard ring region 33 , especially in the four corners The position of the first implantation region 301 with low doping concentration is set to reduce the gain, weaken the large implantation effect, and increase the safe working area of reverse turn-off, while in the regions other than the four corners of the first implantation region 301 The third injection region is used to balance the deterioration of the conduction voltage drop Vcesat caused by the backside pattern design.

It is worth mentioning that, in this embodiment, preferably the positions of the four corners are only the first injection region 301, but it can also be selected and set according to the needs of the actual device, for example, only one corner, two The first implanted region 301 is set in the region of one or three corners, and the top-view shape of the second implanted region may be other polygons other than the shapes shown in FIGS. 3A and 3B , such as triangles, pentagons, Hexagonal or other irregular shapes can also be selected from other reasonable shapes, and the corresponding shape of the first injection region surrounding the second injection region can also be other triangular ring, pentagonal ring, hexagonal Ring etc.

In one example, as shown in FIG. 3A and FIG. 3B , the second implantation region 302 and the third implantation region 303 are separated by part of the first implantation region 301 .

Exemplarily, the second injection region 302 opposite to the cell region 31 can also be selectively extended to cover part of the transition region 32 opposite to the outside.

Exemplarily, the third implantation region 303 is disposed at a position close to the second implantation region 302, and the first implantation region 301 outside the third implantation region 303 is far from the cell region and has a low impurity doping concentration , so it can still play the role of reducing the gain, weakening the large injection effect, and increasing the reverse turn-off safety area.

In an example, the third implantation region 303 may also be disposed in the first implantation region 301 opposite to the transition region 32 , or may be further disposed in a portion adjacent to the transition region opposite to the terminal guard ring region The first injection region 301 can also be set from the inner edge of the terminal guard ring region to the outer edge.

In an example, as shown in FIG. 3A , the third implantation region 303 includes a plurality of strip-shaped implantation regions spaced apart along the radial direction of the first implantation region 301 , wherein the extending direction of the strip-shaped implantation regions parallel to the extending direction of the edge of the second implantation region 302 close to the strip-shaped implantation region, further, the strip-shaped implantation region is spaced from the inner edge of the first implantation region 301 to the outer edge direction .

The number of strip-shaped implantation regions can be reasonably set according to the actual device requirements. For example, at least one strip-shaped implantation region can be set on the outer sides of the four edges of the first implantation region, or two spaced strip-shaped implantation regions can be set respectively. area, and three spaced strip implantation areas can also be provided.

In one example, as shown in FIG. 3B , the third implantation region 303 includes a plurality of bulk implantation regions, and the bulk implantation regions are arranged at intervals along a part of the edge of the second implantation region, and further, a plurality of bulk implantation regions The implanted regions may also be spaced from the inner edge to the outer edge of the first implanted region, so that the bulk implanted regions outside each edge of the second implanted region are arranged in an array.

It is worth noting that the third implantation region includes several bulk implantation regions arranged at intervals, so it can also be referred to as a cellular implantation region.

Optionally, the top view shape of each of the bulk implantation regions is a rectangle, a circle, an ellipse, a triangle, a pentagon or a hexagon, or other shapes, which are not specifically limited herein.

In an example, as shown in FIG. 3A and FIG. 3B , the second implanted region 302 is a polygon with one corner missing, such as a triangle, a quadrilateral, a pentagon, a hexagon, etc., and the third implanted region 303 is also located on the missing corner of the polygon, and the device substrate further includes a gate pad area, the gate pad area is located outside the third injection region 303 on the missing corner, the The backside region of the device substrate of the gate pad region has the same implantation region as the first implantation region 301 .

For example, the second injection region 302 is a quadrilateral with one corner missing, and the three corners of the quadrilateral are arc-shaped, and the third injection region 303 is also located on the missing corner of the quadrilateral, so The front side of the device substrate further includes a gate pad region, the gate pad region is opposite to the missing corner of the polygon, and the gate pad region is located on the missing corner of the third injection region 303. On the outside, as shown in FIG. 3A , the second implanted region 302 includes two straight edges at the corners where the second implanted region 302 is missing, and at least one strip-shaped implanted region is provided on the outside of one straight edge, wherein preferably One strip-shaped implantation region is provided, and a plurality of strip-shaped implantation regions can also be provided, or, as shown in FIG. 3B , several block-shaped implantation regions are provided at intervals along the two straight edges.

It is worth mentioning that although FIG. 3A and FIG. 3B respectively show the case where the third implanted region is a strip-shaped implanted region and the third implanted region is a bulk-shaped implanted region, the third implanted region can also be set to be both. It includes strip-shaped implanted regions and block-shaped implanted regions.

In an example, a buffer area 304 is further provided on the backside of the device substrate 300 , and the top of the buffer area 304 is located in the device with the first implantation region 301 , the second implantation region 302 , and the third implantation region 303 . The bottom surfaces of the substrates are in contact with each other, and the bottom of the buffer area 304 is located in the device substrate 300. For example, when a drift region is provided on the front surface of the device substrate 300, the buffer area is located in the device substrate 300. Between an implantation region 301, a second implantation region 302, a third implantation region 303 and the drift region, wherein the buffer region 304 has the same conductivity type as the drift region or the device substrate, for example, the buffer region 304 has the same conductivity type as the drift region or the device substrate. The conductivity type is N-type, especially for N-type heavily doped buffers.

Exemplarily, the first injection region 301, the second injection region 302, and the third injection region 303 can be used as collector regions of the IGBT device.

Further, a collector layer is further provided on the surfaces of the first injection region 301 , the second injection region 302 and the third injection region 303 , and the collector layer is a metal layer, such as aluminum, gold and other metals.

So far, the introduction of the semiconductor device of the present invention is completed, and the complete device also includes other structures and components, which will not be repeated here.

To sum up, in the semiconductor device of the present invention, a second implantation region (eg P+ implantation region) with high doping concentration is arranged on the back side of the device substrate opposite to the cell region, and a second implantation region (for example, a P+ implantation region) with high doping concentration is arranged on the backside of the device substrate opposite to the cell region, and a second implantation region (for example, a P+ implantation region) with high doping concentration is arranged on the backside of the device substrate opposite to the cell region, and a second implantation region (for example, a P+ implantation region) with a high doping concentration is arranged on the backside of the device substrate opposite to the cell region. A first implantation region with low doping concentration (such as a P-implantation region) is arranged on the backside of the device substrate, especially the first implantation region is provided outside the corners of the cell region (for example, outside the four corners of the cell region). Reduce the gain, weaken the large injection effect, increase the reverse turn-off safe working area, and set a third implantation region with moderate doping concentration on the back side of the device substrate opposite to the terminal guard ring region near the cell region (such as P+ injection region), this setting can balance the deterioration of the conduction voltage drop Vcesat caused by the backside pattern design. In addition, the semiconductor device of the present invention can also reduce the corresponding internal hole load under the terminal ring during the device shutdown process. Convergence of currents, thereby weakening the hole currents gathered together, and avoiding the problem of device failure caused by triggering the latch-up effect of edge cells. Therefore, the semiconductor device of the present invention has high performance and reliability.

Embodiment 2

The present invention also provides a method for manufacturing the semiconductor device in the first embodiment. As shown in FIG. 5 , the method mainly includes the following steps:

Step S1, providing a device substrate, the device substrate including a cell region and a terminal guard ring region surrounding the cell region;

Step S2, forming a first implantation region, wherein the first implantation region is formed on the backside of the device substrate and is opposite to the terminal guard ring region;

Step S3, forming a second implantation region and a third implantation region, wherein the second implantation region is formed on the back surface and is opposite to the cell region, and the third implantation region is formed in the first implantation region In and close to the second implantation region, the doping concentrations of the second implantation region and the third implantation region are both greater than the doping concentration of the first implantation region.

Hereinafter, the manufacturing method of the semiconductor device of the present invention will be described in detail with reference to FIGS. 3A to 3C , FIGS. 4A to 4C and FIG. 5 . In an example, the semiconductor device of the present invention may be an IGBT device, or other semiconductor devices. In this embodiment, the method of the present invention is mainly explained and described by taking the IGBT device as an example.

First, step 1 is performed to provide a device substrate, where the device substrate includes a cell region and a terminal guard ring region surrounding the cell region.

Specifically, as shown in FIG. 4A , a device substrate 300 is provided, and the device substrate 300 includes a cell region and a terminal guard ring region surrounding the cell region.

For simplicity, in FIGS. 4A to 4C , only the device substrate 300 is shown in a blank frame, but it is conceivable that before the backside of the device substrate is processed A variety of element structures constituting the cell region and element structures constituting the terminal guard ring region have been formed, and these structures may be any IGBT structures well known to those skilled in the art, or may be as described in the first embodiment. The same or similar structures described are not repeated here in order to avoid repetition.

In order to make the size of the device substrate smaller, the backside of the device substrate 300 also needs to be thinned.

In this step, the thinning method can be a method commonly used in the art, such as mechanical grinding, chemical mechanical polishing (CMP), chemical etching, plasma etching and other methods. Optionally, the thickness of the thinned device substrate 300 ranges from 50 μm to 200 μm.

Exemplarily, in order to facilitate the operation on the backside of the device substrate, before the thinning, the following steps are further included:

First, a bonding layer (not shown) is formed on the front side of the device substrate.

The bonding layer is a bonding glue, the bonding glue can be, but not limited to, an organic polymer material or an organic material that can be modified by ultraviolet light, and the bonding glue has viscosity.

The bonding paste layer can be formed on the front side of the device substrate using methods such as coating.

Next, a support substrate is provided, and the bonding layer and the support substrate are bonded.

The support substrate may be a semiconductor substrate such as a silicon substrate, glass or ceramic material. It is used to support the device substrate, and it is convenient to operate the backside of the device substrate.

Exemplarily, in order to facilitate the operation on the back side of the device substrate, the front side of the device substrate may also be joined with a supporting substrate, and the supporting substrate is used for supporting the device substrate.

Then, step 2 is performed to form a first implantation region, wherein the first implantation region is formed on the backside of the device substrate and is opposite to the terminal guard ring region.

In one example, before forming the first implantation region, ion implantation may also be selectively performed on the backside of the device substrate to form a buffer layer (not shown) in the device substrate. Optionally, when the buffer layer is an N-type buffer layer, the implanted ions for ion implantation are N-type doping ions, including but not limited to at least one of phosphorus or arsenic.

The buffer layer can be implemented by ion implantation on the backside of the substrate, and the depth of the ion implantation can be controlled by controlling the energy of the implantation. Optionally, the implantation energy of the first ion implantation ranges from 2Mev to 3Mev, and the implantation dose ranges from 1E12 to 5E13 atoms/cm ² , and the numerical range is only used as an example.

Further, as shown in FIG. 4A , the method for forming the first implantation region includes: performing a first ion implantation on the back surface of the device substrate 300 to form a first implantation in the device substrate 300 District 301. In this step, ion implantation is performed on the backside of the entire device substrate without a mask, so the first implantation region formed first will also cover the backside of the entire device substrate 300 .

In one example, the first injection region 301 and the buffer region have opposite conductivity types. For example, if the buffer region is N-type, the first injection region 301 is P-type. In particular, the The first implant region 301 is P-type lightly doped.

Exemplarily, the first implantation region 301 is formed by ion implantation. When the first implantation region 301 is P-type, the type of implanted ions is a P-type impurity, such as boron.

Exemplarily, the depth of ion implantation is controlled by controlling the implantation energy. For example, the implantation energy range of the first ion implantation is 20Kev～40Kev, and the implantation dose range can be 1E11～5E12atom/cm ² , and these numerical ranges are only As an example, it is not intended to limit the present invention.

The first implantation region 301 formed by the above-mentioned ion implantation may be a P-type lightly doped implantation region.

Next, step 3 is performed to form a second implantation region and a third implantation region, wherein the second implantation region is formed on the backside of the device substrate and is opposite to the cell region, and the third implantation region is formed In the first implantation region and close to the second implantation region, the doping concentration of the second implantation region and the third implantation region are both greater than the doping concentration of the first implantation region.

Specifically, as shown in FIG. 4B and FIG. 4C , the method for forming the second implantation region and the third implantation region further includes the following steps:

First, as shown in FIG. 4B , a patterned mask layer 305 is formed on the backside of the device substrate 300 , and the mask layer 305 exposes the device substrate 300 to form the second implanted region and all the the region of the third injection region.

Specifically, the mask layer 305 may include any one of several mask materials, including but not limited to: hard mask materials and photoresist mask materials. In this embodiment, the mask layer 305 includes a photoresist mask material.

A suitable photomask can be designed according to the shapes of the second and third implanted regions in the first embodiment, and the photomask can be used to expose and develop the photoresist mask material coated on the backside of the device substrate 300, etc. , to form a mask layer defining a pattern of the second implantation region and the third implantation region.

The pattern shape and position of the predetermined second implantation region and the third implantation region are described in detail in Embodiment 1, and are not repeated here in order to avoid repetition.

Next, as shown in FIG. 4B , using the mask layer 305 as a mask, a second ion implantation is performed to form the second implantation region 302 and the third implantation region 303 .

Specifically, the second implantation region 302, the third implantation region 303, and the first implantation region 301 have the same conductivity type, for example, P-type. However, the doping concentrations of the second implantation region 302 and the third implantation region 303 are both greater than those of the first implantation region 301, so the doping concentration can be adjusted by controlling the implantation dose.

For example, the implanted ions of the second ion implantation may be P-type dopant ions, eg, may include boron.

Optionally, the implant dose range of the second ion implantation may be 1E13˜5E13 atoms/cm ² , and these numerical ranges are only examples and do not limit the present invention.

Exemplarily, the formed second implantation region 302 and the third implantation region 303 may be P-type heavily doped implantation regions.

Further, the second implantation region and the third implantation region have the same junction depth as the first implantation region, which can be achieved by making the first ion implantation and the second ion implantation have substantially the same implantation energy.

Subsequently, as shown in FIG. 4C, the mask layer is removed. A suitable method can be selected to remove the mask layer according to the material of the specific mask layer, for example, the mask layer of the photoresist material can be removed by using an ashing method.

Further, after the mask layer is removed, an annealing step is also included to activate the doping ions in the first implanted region 301, the second implanted region 302, and the third implanted region 303, and perform defect repair, for example, repairing because Lattice damage to the device substrate caused by ion implantation.

Illustratively, the annealing may use any annealing treatment method well known to those skilled in the art, including but not limited to rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, and the like. In this embodiment, preferably, laser annealing is used for the annealing. Laser annealing has the advantage of local heating, which can anneal only the area to be annealed without causing thermal damage to other areas.

Finally, the first implantation region 301 , the second implantation region 302 , and the third implantation region 303 in the foregoing Embodiment 1 are formed on the backside of the device substrate.

In order to avoid repetition, the first implantation region 301 , the second implantation region 302 , and the third implantation region 303 are not described herein again, and the specific details thereof may refer to the content in the foregoing first embodiment.

Subsequently, in one example, a metal layer may also be formed on the surfaces of the first implantation region 301, the second implantation region 302, and the third implantation region 303, and annealing is performed to form a metal silicide, and the metal layer may include Ti, for example Metal.

Exemplarily, collector electrodes (not shown) may also be formed on the surfaces of the first injection region 301 , the second injection region 302 , and the third injection region 303 . The material of the collector electrode includes metal, and the metal includes but is not limited to aluminum, copper, titanium, or chromium.

Subsequently, in one example, a debonding process is performed to separate the device substrate and the support substrate.

Specifically, any debonding method well-known to those skilled in the art can be used to separate the device substrate and the supporting substrate. The supporting substrate is removed, and the bonding layer that has lost its adhesion is peeled off.

So far, the introduction of the key steps of the semiconductor device manufacturing method of the present invention has been completed, and other steps are required for the complete device fabrication, which will not be repeated here.

Since the manufacturing method of the present invention produces the semiconductor device in the first embodiment, the manufacturing method of the present invention has the same advantages as the first embodiment.

Embodiment 3

The present invention also provides an electronic device, including the semiconductor device described in the first embodiment, and the semiconductor device is prepared according to the method described in the second embodiment.

The electronic device in this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, MP3, MP4, PSP, etc. A product or device can also be any intermediate product that includes a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

Among them, FIG. 6 shows an example of a mobile phone handset. The mobile phone handset 400 is provided with a display portion 402 included in a casing 401, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like.

The mobile phone includes the semiconductor device described in Embodiment 1, and the semiconductor device includes:

a device substrate, including a cell region and a terminal guard ring region surrounding the cell region;

a first implantation region, disposed on the backside of the device substrate and opposite to the terminal guard ring region;

a second injection area, disposed on the backside and opposite to the cell area, the first injection area surrounds the second injection area;

A third implantation region is disposed in the first implantation region and close to the second implantation region, wherein the doping concentrations of the second implantation region and the third implantation region are both greater than those of the first implantation region doping concentration.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (22)

1. A semiconductor device, comprising:

the device comprises a device substrate, a first electrode and a second electrode, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area;

the first injection region is arranged on the back surface of the device substrate and is opposite to the terminal protection ring region;

a second implanted region disposed on the back surface and opposite to the cell region, the first implanted region surrounding the second implanted region;

and the third injection region is arranged in the first injection region and is close to the second injection region, wherein the first injection region, the second injection region and the third injection region have the same conductivity type, and the doping concentration of the second injection region and the doping concentration of the third injection region are all greater than that of the first injection region.

2. The semiconductor device of claim 1, wherein the first implant region is in the shape of a polygonal ring and the third implant region is located in a region outside at least one corner of the first implant region.

3. The semiconductor device of claim 2, wherein the first implanted region includes four corners, and the third implanted region is located in a region outside the four corners of the first implanted region.

4. The semiconductor device according to claim 1, wherein the third implantation region comprises a plurality of strip-shaped implantation regions arranged at intervals in a radial direction of the first implantation region, wherein an extending direction of the strip-shaped implantation regions is parallel to an extending direction of edges of the second implantation regions to which the strip-shaped implantation regions are close; and/or the presence of a gas in the gas,

the third injection region comprises a plurality of block injection regions which are arranged at intervals along part of the edge of the second injection region.

5. The semiconductor device of claim 1, wherein the doping concentration of the second and third implanted regions is the same.

6. The semiconductor device of claim 1, wherein the second implant region is in the shape of a polygon with one missing corner, and the third implant region is also located on the missing corner of the polygon;

the device substrate further includes a gate pad region located outside the third implant region on the missing corner.

7. The semiconductor device according to claim 1,

the first, second and third implanted regions have the same junction depth.

8. The semiconductor device of claim 1, wherein the second and third implanted regions are heavily doped implanted regions and the first implanted region is a lightly doped implanted region.

9. The semiconductor device of claim 1, wherein the device substrate further comprises a transition region surrounding the cell region and located between the terminal guard ring region and the cell region, wherein the first implant region is further opposite the transition region and the third implant region is opposite the transition region.

10. The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT device.

11. A method of manufacturing a semiconductor device, comprising:

providing a device substrate, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area;

forming a first implantation region, wherein the first implantation region is formed on the back surface of the device substrate and is opposite to the terminal protection ring region;

and forming a second injection region and a third injection region, wherein the second injection region is formed on the back surface and is opposite to the cellular region, the third injection region is formed in the first injection region and is close to the second injection region, the first injection region, the second injection region and the third injection region have the same conductivity type, and the doping concentration of the second injection region and the doping concentration of the third injection region are all greater than that of the first injection region.

12. The method of manufacturing of claim 11, wherein forming the first, second, and third implant regions comprises:

performing a first ion implantation on the back side of the device substrate to form a first implanted region in the device substrate;

forming a patterned mask layer on the back surface of the device substrate, wherein the mask layer exposes regions of the device substrate, where the second injection region and the third injection region are scheduled to be formed;

performing second ion implantation by taking the mask layer as a mask to form a second implantation area and a third implantation area;

and removing the mask layer.

13. The method of claim 12, further comprising a step of performing an annealing process to activate dopant ions in the first, second, and third implanted regions after removing the mask layer.

14. The method of manufacturing of claim 12 wherein the first implant region is in the shape of a polygonal ring and the third implant region is located in a region outside at least one corner of the first implant region.

15. The method of manufacturing of claim 14, wherein the first implanted region comprises four corners and the third implanted region is located in a region other than the four corners of the first implanted region.

16. The method of claim 12, wherein the third implant region comprises a plurality of stripe-shaped implant regions spaced apart along a radial direction of the first implant region, wherein an extending direction of the stripe-shaped implant regions is parallel to an extending direction of edges of the second implant regions adjacent to the stripe-shaped implant regions; and/or the presence of a gas in the gas,

the third injection region comprises a plurality of block injection regions which are arranged at intervals along part of the edge of the second injection region.

17. The method of manufacturing of claim 11 wherein the second implant region is in the shape of a polygon with one missing corner, and the third implant region is further located on the missing corner of the polygon;

the semiconductor substrate further includes a gate pad region located outside the third implant region on the missing corner.

18. The manufacturing method according to claim 11,

the first, second and third implanted regions have the same junction depth.

19. The method of manufacturing of claim 11, wherein the second and third implanted regions are heavily doped implanted regions and the first implanted region is a lightly doped implanted region.

20. The method of manufacturing of claim 11, wherein the device substrate further comprises a transition region surrounding the cell region and located between the terminal guard ring region and the cell region, wherein the first implant region is further opposite the transition region and the third implant region is opposite the transition region.

21. The manufacturing method according to claim 11, wherein the semiconductor device is an IGBT device.

22. An electronic device, characterized in that the electronic device comprises the semiconductor device according to one of claims 1 to 10.

Images