CN110729190A - A kind of semiconductor device and its manufacturing method, electronic device - Google Patents

Abstract

The present invention provides a semiconductor device, a manufacturing method thereof, and an electronic device, the method comprising: providing a semiconductor substrate, in which a shallow trench isolation is formed, and a gate structure is formed on the shallow trench isolation ; form a patterned photoresist layer on the gate structure; use the patterned photoresist layer as a mask to etch the gate structure and the shallow trench to isolate the A groove is formed in the trench isolation; a shielding field plate is formed in the groove. According to the manufacturing method of the semiconductor device provided by the present invention, a patterned photoresist layer is formed on the gate, and then the gate and the shallow trench are etched by using the patterned photoresist layer as a mask to isolate the gate and shallow trenches. The shielding field plate is formed in the groove formed by the trench isolation, which simplifies the process steps, saves the process cost, and improves the device performance.

Description

A kind of semiconductor device and its manufacturing method, electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

With the continuous development of semiconductor technology, Lateral Double Diffused MOSFET (LDMOS) devices are widely used in mobile phones due to their good short-channel characteristics, especially in cellular phones. middle. With the continuous increase of the mobile communication market (especially the cellular communication market), the fabrication process of LDMOS devices is becoming more and more mature. As a power switching device, LDMOS has the characteristics of relatively high operating voltage, simple process, and easy process compatibility with low-voltage CMOS circuits. Because it is usually used in power circuits, it needs to obtain a large output power, so it must be able to withstand a high breakdown voltage. At the same time, with the higher and higher requirements for the device performance of LDMOS, it is necessary to further strengthen the control of the electric field distribution.

Therefore, it is necessary to propose a new fabrication method of semiconductor devices to solve the above problems.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

a semiconductor substrate is provided, a shallow trench isolation is formed in the semiconductor substrate, and a gate structure is formed on the shallow trench isolation;

forming a patterned photoresist layer on the gate structure;

etching the gate structure and the shallow trench isolation using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;

A shielded field plate is formed in the groove.

Further, the material of the shielding field plate includes metal.

Further, the gate structure is etched using the patterned photoresist layer as a mask to form a separate first gate structure and a second gate structure.

Further, forming the shielding field plate also includes the step of forming a metal contact over the semiconductor substrate.

Further, the upper surface of the shielding field plate is not lower than the upper surface of the gate structure.

Further, the semiconductor device includes an LDMOS device.

The present invention also provides a semiconductor device, comprising:

a semiconductor substrate, wherein a shallow trench isolation is formed in the semiconductor substrate, and a gate structure is formed on the shallow trench isolation;

A groove is formed in the shallow trench isolation, and a shielding field plate is formed in the groove.

Further, the material of the shielding field plate includes metal.

Further, the gate structure includes a separate first gate structure and a second gate structure.

Further, the upper surface of the shielding field plate is not lower than the upper surface of the gate structure.

The present invention also provides an electronic device, which includes the above-mentioned semiconductor device and an electronic component connected with the semiconductor device.

According to the manufacturing method of the semiconductor device provided by the present invention, a patterned photoresist layer is formed on the gate, and then the gate and the shallow trench are etched by using the patterned photoresist layer as a mask to isolate the gate and shallow trenches. The shielding field plate is formed in the groove formed by the trench isolation, which simplifies the process steps, saves the process cost, and improves the device performance.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and together with the embodiments of the present invention, they are used to explain the present invention, and do not limit the present invention. In the drawings, the same reference numbers generally refer to the same components or steps.

In the attached picture:

FIG. 1 is a schematic flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present invention.

2A-2D are schematic cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an exemplary embodiment of the present invention.

FIG. 3 shows a schematic diagram of an electronic device according to an exemplary embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present invention, detailed steps and detailed structures will be proposed in the following description to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Since LDMOS devices are usually used in power circuits and need to obtain larger output power, they must be able to withstand higher breakdown voltages. At the same time, with the higher and higher requirements for the device performance of LDMOS, it is necessary to further strengthen the control of the electric field distribution.

In view of the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

a semiconductor substrate is provided, a shallow trench isolation is formed in the semiconductor substrate, and a gate structure is formed on the shallow trench isolation;

forming a patterned photoresist layer on the gate structure;

etching the gate structure and the shallow trench isolation using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;

A shielded field plate is formed in the groove.

Wherein, the material of the shielding field plate includes metal; the gate structure is etched by using the patterned photoresist layer as a mask to form a separate first gate structure and a second gate structure; The shielding field plate also includes the step of forming a metal contact above the semiconductor substrate; the upper surface of the shielding field plate is not lower than the upper surface of the gate structure; the semiconductor device includes an LDMOS device.

According to the manufacturing method of the semiconductor device provided by the present invention, a patterned photoresist layer is formed on the gate, and then the gate and the shallow trench are etched by using the patterned photoresist layer as a mask to isolate the gate and shallow trenches. The shielding field plate is formed in the groove formed by the trench isolation, which simplifies the process steps, saves the process cost, and improves the device performance.

Referring to FIG. 1 and FIGS. 2A-2D, FIG. 1 shows a schematic flow chart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2A-2D shows an exemplary embodiment of the present invention. Schematic cross-sectional views of the devices respectively obtained by the steps performed in sequence in the method.

The present invention provides a preparation method of a semiconductor device, as shown in FIG. 1 , the main steps of the preparation method include:

Step S101 : providing a semiconductor substrate, in which a shallow trench isolation is formed, and a gate structure is formed on the shallow trench isolation;

Step S102: forming a patterned photoresist layer on the gate structure;

Step S103 : etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;

Step S104: forming a shielding field plate in the groove.

First, step S101 is performed. As shown in FIG. 2A , a semiconductor substrate 200 is provided, in which a shallow trench isolation 201 is formed, and a gate structure 202 is formed on the shallow trench isolation 201 .

Exemplarily, the semiconductor device of the present invention includes a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, and the semiconductor device of the present invention includes a first conductivity type and a second conductivity type. Exemplarily, the first conductivity type is P-type, and the second conductivity type is N-type, wherein the P-type doping ions include but not limited to boron ions, and the N-type doping ions include but are not limited to phosphorus ions or arsenic ions.

Exemplarily, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator ( S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, the semiconductor substrate 200 is a silicon substrate having a first conductivity type or a second conductivity type.

Exemplarily, a P well is formed in the semiconductor substrate 200 as a body region (Body) 2001 . As an example, a standard well implantation process is used to form a P well in a semiconductor substrate. The P well can be formed by a high energy implantation process, or a P well can be formed by a low energy implantation combined with a high temperature thermal annealing process.

Exemplarily, a drift region (Drift) 2002 is further formed in the semiconductor substrate 200. The drift region 2002 is located in the semiconductor substrate 200 and is generally a lightly doped region. For an N-channel LDMOS, the drift region is N-type doped. As an example, the drift region 2002 and the P-well are formed in a similar manner, and can be formed by a high-energy implantation process, or can be formed by a low-energy implantation combined with a high-temperature thermal annealing process.

As an example, semiconductor substrate 200 has a first conductivity type, body region 2001 has a first conductivity type, and drift region 2002 has a second conductivity type to form an NLDMOS device.

Illustratively, a source region (source) 2004 and a body lead-out region 2006 are formed in the body region 2001, a doped region 2003 is formed in the drift region 2002, a drain region (drain) 2005 is formed in the doped region 2003, and the source region 2004 is formed , and the drain region 2005 can respectively lead out a source electrode and a drain electrode.

Further, the source region 2004, the drain region 2005 and the doped region 2003 have the second conductivity type, and the body extraction region 2006 has the first conductivity type. The doping concentration of the drain region 2005 is higher than that of the doping region 2003 , and the doping concentration of the doping region 2003 is higher than that of the drift region 2002 . As an example, N-type impurities are implanted into the body region 2001 to form the source region 2004, and N-type impurities are implanted into the doped region 2003 to form the drain region 2005. The doping concentrations of the source region 2004 and the drain region 2005 can be the same, therefore, the two Can be formed by doping synchronously. As an example, a P-type impurity is implanted in the body region 2001 to form a body lead-out region 2006 .

Exemplarily, Shallow Trench Isolation (STI) 201 is formed in the semiconductor substrate 200 . Specifically, a portion of the semiconductor substrate 200 is etched to form a shallow trench, and an isolation material is filled in the shallow trench to form a shallow trench isolation structure 201 that isolates the active region.

Exemplarily, a gate structure 202 is formed on the shallow trench isolation 201 . The gate structure 202 includes a gate dielectric layer and a gate material layer sequentially stacked from bottom to top. The gate dielectric layer includes an oxide layer, such as a silicon dioxide (SiO ₂ ) layer. The gate material layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer.

In addition, an interlayer dielectric layer (not shown) is also formed on the semiconductor substrate 200 , and the interlayer interface layer covers the source region 2004 , the drain region 2005 and the body lead-out region 2006 .

Next, step S102 is performed, as shown in FIG. 2B , a patterned photoresist layer 203 is formed on the gate structure 202 .

Exemplarily, a layer of photoresist is coated on the upper surface of the gate structure 202, and then an exposure and development process is performed by means of a photomask having an exposure pattern, thereby forming an opening pattern in the photoresist.

Next, step S103 is performed, as shown in FIG. 2C , the gate structure 202 and the shallow trench isolation 201 are etched by using the patterned photoresist layer 203 as a mask, so that the Recesses are formed in the isolation 201 . Further, the gate structure 202 is etched using the patterned photoresist layer 203 as a mask to form a separate first gate structure 2021 and a second gate structure 2022 .

Exemplarily, the gate structure 202 and the shallow trench isolation 201 are etched using the patterned photoresist layer 203 as a mask to form a first groove 204 and a second groove 205, wherein part of the gate structure 202 is etched and part of the shallow trench isolation 201 to form a first groove 204, and the gate structure 202 is etched until the upper surface of the shallow trench isolation 201 is exposed to form a second groove 205, the second groove 205 connects the gate The structure 202 is separated into a first gate structure 2021 and a second gate structure 2022 . Specifically, the gate structure 202 and the shallow trench isolation 201 are etched by a dry etching process, including but not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, laser etching Ablation or any combination of these methods.

The gate structure 202 is separated into the separated first gate structure 2021 and the second gate structure 2022 by the second groove 205 to serve as gate field plates, which increases the capacitance of the LDMOS device, improves the electric field distribution, and further improves the pressure resistance.

Further, while using the patterned photoresist layer 203 as a mask to etch the gate structure 202 and the shallow trench isolation 201, it also includes etching the interlayer dielectric by using the patterned photoresist layer 203 as a mask layer to form a contact hole in the interlayer dielectric layer above the source region 2004 , the drain region 2005 and the body lead-out region 2006 .

Next, step S104 is performed, as shown in FIG. 2D , a shielding field plate 206 is formed in the first groove 204 .

Exemplarily, a metal material (eg, tungsten) is filled in the first groove 204 to form a shielding field plate 206 , and the upper surface of the shielding field plate 206 is not lower than the upper surface of the gate electrode 202 . In this embodiment, when the shielding field plate 206 is formed, the step of filling metal in the contact holes above the source region 2004 , the drain region 2005 and the body lead-out region 2006 to form a metal contact (CT) is also included.

By forming the shielding field plate 206 in the first groove 204, the capacitance of the LDMOS device is increased, the electric field distribution is improved, and the withstand voltage performance is further improved.

According to the manufacturing method of the semiconductor device provided by the present invention, in the above steps, the photoresist layer is only formed once and the etching process is performed once. Compared with the prior art, the process steps are simplified, the process cost is saved, and the device performance.

The structure of the semiconductor device provided by the embodiment of the present invention will be described below with reference to FIG. 2D . The semiconductor device includes: a semiconductor substrate 200, in which a shallow trench isolation 201 is formed, and a gate electrode is formed on the shallow trench isolation 201; and a groove is formed in the shallow trench isolation 201 , a shielding field plate 206 is formed in the groove.

Exemplarily, the semiconductor device of the present invention includes a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, and the semiconductor device of the present invention includes a first conductivity type and a second conductivity type. Exemplarily, the first conductivity type is P-type, and the second conductivity type is N-type, wherein the P-type doping ions include but not limited to boron ions, and the N-type doping ions include but are not limited to phosphorus ions or arsenic ions.

Exemplarily, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator ( S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, the semiconductor substrate 200 is a silicon substrate having a first conductivity type or a second conductivity type.

Exemplarily, a P-well is formed in the semiconductor substrate 200 as a body region (Body) 2001, and a drift region (Drift) 2002 is also formed in the semiconductor substrate 200. The drift region 2002 is located in the semiconductor substrate 200 and is generally lightly doped. Impurity region, for N-channel LDMOS, the drift region is N-type doped. As an example, semiconductor substrate 200 has a first conductivity type, body region 2001 has a first conductivity type, and drift region 2002 has a second conductivity type to form an NLDMOS device.

Further, an active region (source) 2004 and a body lead-out region 2006 are formed in the body region 2001, a doping region 2003 is formed in the drift region 2002, a drain region 2005 is formed in the doping region 2003, and the source region is 2004 and the drain region 2005 can respectively lead out a source electrode and a drain electrode. The source region 2004, the drain region 2005 and the doped region 2003 have the second conductivity type, and the body lead-out region 2006 has the first conductivity type. The doping concentration of the drain region 2005 is greater than that of the doping region 2003 , and the doping concentration of the doping region 2003 is greater than that of the drift region 2002 .

Exemplarily, Shallow Trench Isolation (STI) 201 is formed in the semiconductor substrate 200 . A first groove is formed in the shallow trench isolation 201, and a shielding field plate 206 is formed in the first groove. Further, the material of the shielding field plate 206 includes metal, such as tungsten. By forming the shielding field plate 206 in the shallow trench isolation 201, the capacitance of the LDMOS device is increased, the electric field distribution is improved, and the withstand voltage performance is further improved.

Exemplarily, a second groove 205 is formed in the gate 202 , and the second groove 205 separates the gate 202 into a first gate 2021 and a second gate 2022 . The gate 202 is separated into the separated first gate 2021 and the second gate 2022 by the second groove 205 to serve as the gate field plate, which increases the capacitance of the LDMOS device, improves the electric field distribution, and further increases the withstand voltage performance.

The present invention also provides an electronic device comprising a semiconductor device and an electronic component connected with the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate 200, a shallow trench isolation 201 is formed in the semiconductor substrate 200, a gate is formed on the shallow trench isolation 201; A groove in which the shielding field plate 206 is formed.

The electronic components may be any electronic components such as discrete devices and integrated circuits.

The electronic device in this embodiment may be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video camera, voice recorder, MP3, MP4, PSP, etc. , or any intermediate product including the semiconductor device.

Among them, FIG. 3 shows an example of a mobile phone. The exterior of the cellular phone 300 is provided with a display portion 302 included in a casing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (11)

1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:

providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;

forming a patterned photoresist layer on the gate structure;

etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;

a shielded field plate is formed in the recess.

2. The method of claim 1, wherein the material of the shielded field plate comprises a metal.

3. The method of claim 1, wherein the gate structure is etched using the patterned photoresist layer as a mask to form separate first and second gate structures.

4. The method of claim 1, wherein forming the shielded field plate further comprises forming a metal contact over the semiconductor substrate.

5. The method of claim 1, wherein an upper surface of the shielded field plate is not lower than an upper surface of the gate structure.

6. The method of manufacturing of claim 1, wherein the semiconductor device comprises an LDMOS device.

7. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a gate structure is formed on the shallow trench isolation;

a groove is formed in the shallow trench isolation, and a shielding field plate is formed in the groove.

8. The semiconductor device of claim 7, in which a material of the shielded field plate comprises a metal.

9. The semiconductor device of claim 7, in which the gate structure comprises a first gate structure and a second gate structure that are separated.

10. The semiconductor device of claim 7, wherein an upper surface of the shielded field plate is not lower than an upper surface of the gate structure.

11. An electronic device comprising the semiconductor device according to claim 7 and an electronic component connected to the semiconductor device.

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