CN109216345B - Electrostatic discharge protection architecture, integrated circuit and protection method of core circuit thereof - Google Patents
Electrostatic discharge protection architecture, integrated circuit and protection method of core circuit thereof Download PDFInfo
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Abstract
用来保护集成电路的核心电路免受导电垫片所接收的静电放电事件的伤害的静电放电防护架构,其包含第一导电层、箝制元件、第一电性连接部以第二电性连接部。该第一导电层形成于该导电垫片的下方,并包含第一导电部分、隔绝部分及第二导电部分。该隔绝部分由该第一导电部分与该第二导电部分所包围。该第一导电部分电连接于该导电垫片与该第二导电部分之间。该箝制元件用以箝制该静电放电事件。该第一电性连接部耦接于该第一导电层的该第一导电部分与该箝制元件之间。该第二电性连接部耦接于该第一导电层的该第二导电部分与该核心电路之间。
An electrostatic discharge protection structure for protecting the core circuit of an integrated circuit from electrostatic discharge events received by a conductive pad comprises a first conductive layer, a clamping element, a first electrical connection portion and a second electrical connection portion. The first conductive layer is formed below the conductive pad and comprises a first conductive portion, an isolation portion and a second conductive portion. The isolation portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamping element is used to clamp the electrostatic discharge event. The first electrical connection portion is coupled between the first conductive portion of the first conductive layer and the clamping element. The second electrical connection portion is coupled between the second conductive portion of the first conductive layer and the core circuit.
Description
技术领域technical field
本发明涉及静电放电防护(electrostatic discharge protection,ESDprotection),特别涉及一种利用导电层的布图规划设计(floor plan design)来保护集成电路的核心电路免受静电放电事件的伤害的静电放电防护架构,及其相关的集成电路与静电放电防护方法。The present invention relates to electrostatic discharge protection (ESD protection), and more particularly to an ESD protection structure that utilizes a floor plan design of a conductive layer to protect a core circuit of an integrated circuit from damage caused by electrostatic discharge events , and related integrated circuits and electrostatic discharge protection methods.
背景技术Background technique
为了避免集成电路的核心电路(core circuit)因为静电放电电流(ESD current)的缘故而损坏,集成电路会采用设置于其中的箝制电路(clamp circuit)来箝制静电放电电流。然而,一旦静电放电电流在流入该箝制电路以前先流入核心电路,集成电路并无法避免核心电路遭受静电放电的伤害。因此,需要一种创新的静电放电防护机制来提升静电放电防护的能力。In order to prevent the core circuit of the integrated circuit from being damaged due to ESD current, the integrated circuit uses a clamp circuit disposed therein to clamp the ESD current. However, once the ESD current flows into the core circuit before flowing into the clamp circuit, the integrated circuit cannot prevent the core circuit from being damaged by ESD. Therefore, an innovative ESD protection mechanism is required to improve the capability of ESD protection.
发明内容SUMMARY OF THE INVENTION
有鉴于此,本发明的目的之一在于提供一种利用导电层的布图规划设计(floorplan design)来保护集成电路的核心电路免受静电放电事件的伤害的静电放电防护架构,及其相关的集成电路与静电放电防护方法,来解决上述问题。In view of this, one of the objectives of the present invention is to provide an ESD protection structure that utilizes a floorplan design of a conductive layer to protect the core circuit of an integrated circuit from ESD events, and related ESD protection structures. Integrated circuits and electrostatic discharge protection methods to solve the above problems.
依据本发明的一实施例,其公开一种静电放电防护架构。该静电放电防护架构用来保护一集成电路的一核心电路免受一导电垫片所接收的一静电放电事件的伤害。该静电放电防护架构包含有一第一导电层、一箝制元件、一第一电性连接部以及一第二电性连接部。该第一导电层形成于该导电垫片的下方,其中该第一导电层包含一第一导电部分、一隔绝部分以及一第二导电部分,该隔绝部分是由该第一导电部分与该第二导电部分所包围,以及该第一导电部分是电连接于该导电垫片与该第二导电部分之间。该箝制元件用以箝制该静电放电事件。该第一电性连接部耦接于该第一导电层的该第一导电部分与该箝制元件之间。该第二电性连接部耦接于该第一导电层的该第二导电部分与该核心电路之间。According to an embodiment of the present invention, an electrostatic discharge protection structure is disclosed. The ESD protection architecture is used to protect a core circuit of an integrated circuit from an ESD event received by a conductive pad. The electrostatic discharge protection structure includes a first conductive layer, a clamping element, a first electrical connection portion and a second electrical connection portion. The first conductive layer is formed under the conductive pad, wherein the first conductive layer includes a first conductive portion, an insulating portion and a second conductive portion, and the insulating portion is formed by the first conductive portion and the second conductive portion. Surrounded by two conductive parts, and the first conductive part is electrically connected between the conductive pad and the second conductive part. The clamping element is used to clamp the electrostatic discharge event. The first electrical connection portion is coupled between the first conductive portion of the first conductive layer and the clamping element. The second electrical connection portion is coupled between the second conductive portion of the first conductive layer and the core circuit.
依据本发明的一实施例,其公开一种集成电路。该集成电路包含一导电垫片、一核心电路以及一静电放电防护架构。该静电放电防护架构耦接于该导电垫片与该核心电路,用以保护该核心电路免受该导电垫片所接收的一静电放电事件的伤害。该静电放电防护架构包含有一第一导电层、一箝制元件、一第一电性连接部以及一第二电性连接部。该第一导电层形成于该导电垫片的下方,其中该第一导电层包含一第一导电部分、一隔绝部分以及一第二导电部分,该隔绝部分是由该第一导电部分与该第二导电部分所包围,以及该第一导电部分是电连接于该导电垫片与该第二导电部分之间。该箝制元件用以箝制该静电放电事件。该第一电性连接部耦接于该第一导电层的该第一导电部分与该箝制元件之间。该第二电性连接部耦接于该第一导电层的该第二导电部分与该核心电路之间。According to an embodiment of the present invention, an integrated circuit is disclosed. The integrated circuit includes a conductive pad, a core circuit and an electrostatic discharge protection structure. The electrostatic discharge protection structure is coupled to the conductive pad and the core circuit for protecting the core circuit from an electrostatic discharge event received by the conductive pad. The electrostatic discharge protection structure includes a first conductive layer, a clamping element, a first electrical connection portion and a second electrical connection portion. The first conductive layer is formed under the conductive pad, wherein the first conductive layer includes a first conductive portion, an insulating portion and a second conductive portion, and the insulating portion is formed by the first conductive portion and the second conductive portion. Surrounded by two conductive parts, and the first conductive part is electrically connected between the conductive pad and the second conductive part. The clamping element is used to clamp the electrostatic discharge event. The first electrical connection portion is coupled between the first conductive portion of the first conductive layer and the clamping element. The second electrical connection portion is coupled between the second conductive portion of the first conductive layer and the core circuit.
依据本发明的一实施例,其公开一种用来保护一集成电路的一核心电路免受一导电垫片所接收的一静电放电事件的伤害的方法。该方法包含下列步骤:于该导电垫片的下方提供一第一导电层,其中该第一导电层包含一第一导电部分、一隔绝部分以及一第二导电部分,该隔绝部分是由该第一导电部分与该第二导电部分所包围,以及该第一导电部分是电连接于该导电垫片与该第二导电部分之间;将一第一电性连接部耦接于该第一导电层的该第一导电部分与一箝制元件之间,其中该箝制元件用于箝制该静电放电事件;以及将一第二电性连接部耦接于该第一导电层的该第二导电部分与该核心电路之间。According to one embodiment of the present invention, a method for protecting a core circuit of an integrated circuit from an electrostatic discharge event received by a conductive pad is disclosed. The method includes the following steps: providing a first conductive layer under the conductive pad, wherein the first conductive layer includes a first conductive part, an isolation part and a second conductive part, the isolation part is formed by the first conductive part A conductive portion is surrounded by the second conductive portion, and the first conductive portion is electrically connected between the conductive pad and the second conductive portion; a first electrical connection portion is coupled to the first conductive portion between the first conductive portion of the layer and a clamping element, wherein the clamping element is used to clamp the electrostatic discharge event; and a second electrical connection is coupled between the second conductive portion of the first conductive layer and the between the core circuits.
本发明所提供的静电放电防护机制可通过导电路径的设计(例如:导电层/金属层的布图规划/布局设计),优先将静电放电电流导引至箝制元件,进而防止静电放电电流直接流入核心电路。此外,本发明所提供的静电放电防护机制可具有较高的电流承受能力(其可避免/减少电迁移效应)以及较小的寄生电容。The electrostatic discharge protection mechanism provided by the present invention can preferentially guide the electrostatic discharge current to the clamping element through the design of the conductive path (for example, the layout planning/layout design of the conductive layer/metal layer), thereby preventing the electrostatic discharge current from directly flowing into core circuit. In addition, the ESD protection mechanism provided by the present invention may have higher current carrying capability (which may avoid/reduce electromigration effects) and smaller parasitic capacitance.
附图说明Description of drawings
图1为本发明集成电路的一实施例的功能方块示意图。FIG. 1 is a functional block diagram of an embodiment of an integrated circuit of the present invention.
图2为图1所示的静电放电防护架构的一局部结构的一实施例的示意图。FIG. 2 is a schematic diagram of an embodiment of a partial structure of the ESD protection structure shown in FIG. 1 .
图3为图2所示的导电层的一布图规划布局的一实施例的示意图。FIG. 3 is a schematic diagram of an embodiment of a floorplan layout of the conductive layer shown in FIG. 2 .
图4为图2所示的导电层的一布图规划布局的一实施例的示意图。FIG. 4 is a schematic diagram of an embodiment of a floorplan layout of the conductive layer shown in FIG. 2 .
图5为图2所示的导电层的一布图规划布局的一实施例的示意图。FIG. 5 is a schematic diagram of an embodiment of a floorplan layout of the conductive layer shown in FIG. 2 .
图6为图2所示的导电层的一布图规划布局的一实施例的示意图。FIG. 6 is a schematic diagram of an embodiment of a floorplan layout of the conductive layer shown in FIG. 2 .
图7为本发明用来保护一集成电路的一核心电路免受一导电垫片所接收的一静电放电事件的伤害的方法的一实施例的流程图。7 is a flow diagram of one embodiment of a method of the present invention for protecting a core circuit of an integrated circuit from an electrostatic discharge event received by a conductive pad.
附图标记说明:Description of reference numbers:
100 集成电路100 integrated circuits
102 导电垫片102 Conductive gasket
104 核心电路104 Core circuit
110 静电放电防护架构110 ESD Protection Architecture
122、124 箝制元件122, 124 Clamping element
231~237、431、531、631 导电层231~237, 431, 531, 631 Conductive layer
241、242、243 电性连接部241, 242, 243 Electrical connection part
352、452、552、652 第一导电部分352, 452, 552, 652 The first conductive part
353、453、553、653 隔绝部分353, 453, 553, 653 Isolation part
354、454、554、654 第二导电部分354, 454, 554, 654 Second conductive part
710、720、730 步骤710, 720, 730 steps
A11、A12、A21、A22、A31、A32、A41、A42 传导方向A11, A12, A21, A22, A31, A32, A41, A42 Conduction direction
VDD 电源电压VDD supply voltage
GND 接地电压GND ground voltage
EESD 静电放电事件E ESD electrostatic discharge event
IESD 静电放电电流I ESD electrostatic discharge current
D1、D2 二极管D1, D2 diode
具体实施方式Detailed ways
在說明书及后续的申请专利范围当中使用了某些词汇來指称特定的元件。所属領域中具有通常知識者应可理解,制造商可能会用不同的名词來称呼同样的元件。本說明书及后续的申请专利范围并不以名称的差異來作为区别元件的方式,而是以元件在功能上的差異來作为区别的基准。在通篇說明书及权利要求当中所提及的「包含」为一开放式的用语,故应解释成「包含但不限定于」。此外,「耦接」一词在此是包含任何直接及间接的电气連接手段。因此,若文中描述一第一装置电性連接于一第二装置,则代表该第一装置可直接連接于该第二装置,或通过其他装置或連接手段间接地連接至该第二装置。Certain terms are used in the specification and subsequent claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same element by different nouns. The scope of this specification and subsequent patent applications does not take the difference in name as a way to distinguish elements, but takes the difference in function of the elements as a basis for distinction. The "comprising" mentioned in the entire specification and claims is an open-ended term, so it should be interpreted as "including but not limited to". Furthermore, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described herein that a first device is electrically connected to a second device, it means that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or connecting means.
图1为本发明集成电路的一实施例的功能方块示意图。集成电路100可包含(但不限于)一导电垫片(conductive pad)102、一核心电路104以及一静电放电防护架构(ESDprotection structure)110。核心电路104耦接于一电源电压VDD与一接地电压GND之间,并可依据导电垫片102所接收的不同的控制信号(未绘示于图1中)来执行相对应的功能/操作(诸如时序控制(timing control)或源极驱动(source driving))。静电放电防护架构110耦接于导电垫片102与核心电路104,并可用来保护核心电路104免受导电垫片102所接收的一静电放电事件EESD的伤害。于此实施例中,静电放电防护架构110可包含(但不限于)一箝制元件122以及一箝制元件124,其中箝制元件122耦接于导电垫片102与电源电压VDD之间以箝制静电放电事件EESD,而箝制元件124则是耦接于导电垫片102与接地电压GND之间以箝制静电放电事件EESD。举例来说(但本发明不限于此),箝制元件122可由一二极管D1来实施,及/或箝制元件124可由一二极管D2来实施。FIG. 1 is a functional block diagram of an embodiment of an integrated circuit of the present invention. The
为了避免因应静电放电事件EESD所产生的一静电放电电流IESD未经一箝制电路(诸如箝制元件122/124)就直接流入核心电路104,静电放电防护架构110可利用传导路径/导通路径(conductive path)的设计(诸如导电层/金属层的布图规划/布局(floorplan/layout)设计)来控制静电放电电流IESD的流向,确保静电放电电流IESD不会在流入该箝制电路之前先流入核心电路104。值得注意的是,由于图1所示的二极管D1(箝制元件122)所涉及的静电放电防护路径及其相关操作与图1所示的二极管D2(箝制元件124)所涉及的静电放电防护路径及其相关操作相似/相同,为了简洁起见,以下是以图1所示的二极管D1所涉及的静电放电防护路径来说明本发明所提供的静电放电防护机制。进一步的说明如下。In order to prevent an electrostatic discharge current I ESD generated in response to an electrostatic discharge event E ESD from directly flowing into the
请连同图1来参阅图2。图2为图1所示的静电放电防护架构110的一局部结构的一实施例的示意图。于此实施例中,导电垫片102是经由一电性连接部241来耦接于静电放电防护架构110,其中电性连接部241可将静电放电电流IESD由导电垫片102传导/导引至静电放电防护架构110。除了二极管D1,静电放电防护架构110另可包含(但不限于)多个导电层231~237(诸如多个金属层)、一电性连接部242以及一电性连接部243,其中多个导电层231~237均形成于导电垫片102的下方,且多个导电层231~237之中的每一导电层均电连接于导电垫片102与二极管D1之间。导电层231是经由电性连接部242来耦接至二极管D1以提供导电垫片102与二极管D1之间的传导路径,以及经由电性连接部243来耦接至核心电路104以提供导电垫片102与核心电路104之间的传导路径。Please refer to Figure 2 in conjunction with Figure 1 . FIG. 2 is a schematic diagram of an embodiment of a partial structure of the
通过传导路径的设计,静电放电防护架构110可确保静电放电电流IESD不会在流入二极管D1之前就先流入核心电路104。请一并参阅图2与图3。图3为图2所示的导电层231的一布图规划布局(floorplan layout)的一实施例的示意图。于图3所示的实施例中,导电层231可包含(但不限于)一第一导电部分(first conductive portion)352、一隔绝部分(insulating portion)353以及一第二导电部分354,其中隔绝部分353是由第一导电部分352与第二导电部分354所包围,以及第一导电部分352是电连接于导电垫片102与第二导电部分354之间。此外,电性连接部242是耦接于导电层231的第一导电部分352与二极管D1之间,而电性连接部243则是耦接于导电层231的第二导电部分354与核心电路104之间。Through the design of the conduction path, the
在一电流经由导电垫片102流入导电层231的情形下,由于导电层231是经由第一导电部分352来与导电垫片102电连接,因此该电流可能会从第一导电部分352流入二极管D1或核心电路104。举例来说(但本发明不限于此),该电流可依序经由第一导电部分352及电性连接部242而流入二极管D1(对应于一第一传导路径),或可依序经由第一导电部分352、第二导电部分354及电性连接部243而流入核心电路104(对应于一第二传导路径)。值得注意的是,隔绝部分353可致使流入导电层231的该电流朝着电性连接部242的方向(传导方向A11)来传导,而不是直接朝着电性连接部243的方向(传导方向A12)来传导。由于电性连接部242是电连接于二极管D1,因此,一旦该电流流经导电层231的第一导电部分352,该电流的全部(或几乎全部)会经由电性连接部242而流入二极管D1。换言之,上述第一传导路径为该电流的主要传导路径。In the case where a current flows into the
因此,当静电放电事件EESD发生时,导电层231可利用第一导电部分352接收来自导电垫片102的静电放电电流IESD,而电性连接部242便可将静电放电电流IESD(全部或几乎全部的静电放电电流IESD)导引/传导至二极管D1以抑制静电放电电流IESD。通过传导路径的设计,导电层231可优先将静电放电电流IESD经由第一导电部分352与电性连接部242导引/传导至二极管D1,进而避免静电放电电流IESD直接流入核心电路104而不是先流入二极管D1。换言之,在静电放电电流IESD经由第一导电部分352、第二导电部分354与电性连接部243流入核心电路104之前,电性连接部242可将全部或几乎全部的静电放电电流IESD导引/传导至二极管D1。如此一来,静电放电防护架构110可确保全部或几乎全部的静电放电电流IESD先流入二极管D1而不是先流入核心电路104。Therefore, when the electrostatic discharge event E ESD occurs, the
于此实施例中,隔绝部分353可由导电层231的一开口(opening)(诸如一空气隙开口)来实施。然而,这并非用来作为本发明的限制。例如:采用一电性绝缘材料(electrically insulating material)(诸如一介电材质(dielectric material))来实作出隔绝部分353也是可行的。又例如:隔绝部分353也可是由电性绝缘材料所填满的开口。只要导电层231可包含一隔绝部分以防止所接收的电流的全部(或几乎全部)直接流入电性连接部243(亦即,沿着传导方向A12)而不是流入电性连接部242,设计上相关的变化均遵循本发明的精神而落入本发明的范畴。In this embodiment, the
此外,于图2所示的实施例中,耦接于核心电路104的导电层231可以是形成于其他导电层(亦即,多个导电层232~237)的上方的一顶导电层(top conductive layer),因而可具有较厚的厚度、较高的电流承受能力(current capability)(可避免/减少电迁移效应(electromigration effect,EM effect))以及较小的寄生电容。请注意,这并非用来作为本发明的限制。于一设计变化中,耦接于核心电路104的一导电层也可以是多个导电层232~237的其一而不是顶导电层。于另一设计变化中,耦接于核心电路104的一导电层可以是多个导电层231~237之中具有最大的厚度的一导电层。In addition, in the embodiment shown in FIG. 2 , the
以上所述是仅供说明之需,并非用来作为本发明的限制。举例来说,图2所示的形成于导电垫片102与二极管D1之间的导电层的层数并非用来作为本发明的限制。于某些实施例中,可于一导电垫片(诸如图2所示的导电垫片102)与一箝制元件(诸如图2所示的二极管D1)之间形成一层或多层的导电层。此外,于某些实施例中,图1所示的箝制元件122/124也可由其他类型的箝制电路来实施。The above description is for illustrative purposes only, and is not intended to be used as a limitation of the present invention. For example, the number of layers of the conductive layer formed between the
图3所示的布图规划布局是仅供说明之需,并非用来作为本发明的限制。图4~图6绘示了图2所示的导电层231的布图规划布局的多个实施例的示意图。于图4所示的实施例中,导电层431的隔绝部分453可致使流入第一导电部分452的一电流(诸如静电放电电流)流向/流经电性连接部242(传导方向A21),防止该电流直接经由第二导电部分454流向电性连接部243(传导方向A22)。于图5所示的实施例中,导电层531的隔绝部分553可致使流入第一导电部分552的一电流(诸如静电放电电流)流向/流经电性连接部242(传导方向A31),防止该电流直接经由第二导电部分554流向电性连接部243(传导方向A32)。于图6所示的实施例中,导电层631的隔绝部分653可致使流入第一导电部分652的一电流(诸如静电放电电流)流向/流经电性连接部242(传导方向A41),防止该电流直接经由第二导电部分654流向电性连接部243(传导方向A42)。由于熟习技艺者经由阅读图1~图3的相关说明之后,应可了解图4~图6所示的静电放电防护机制可优先将静电放电电流导引/传导至箝制元件,进而避免静电放电电流直接流入核心电路,是故进一步的说明在此便不再赘述。The floorplan layout shown in FIG. 3 is for illustrative purposes only and is not intended to be a limitation of the present invention. 4 to 6 are schematic diagrams illustrating various embodiments of the floorplanning layout of the
本发明所提供的静电放电防护机制可简单归纳于图7。图7为本发明用来保护一集成电路的一核心电路免受一导电垫片所接收的一静电放电事件的伤害的方法的一实施例的流程图。为了方便说明,以下搭配图2与图3所示的静电放电防护结构110来说明图7所示的方法。此外,假若所得到的结果实质上大致相同,则步骤不一定要依照图7所示的次序来执行之。举例来说,可安插某些步骤于其中。图7所示的方法可简单归纳如下。The ESD protection mechanism provided by the present invention can be simply summarized in FIG. 7 . 7 is a flow diagram of one embodiment of a method of the present invention for protecting a core circuit of an integrated circuit from an electrostatic discharge event received by a conductive pad. For the convenience of description, the method shown in FIG. 7 is described below with reference to the electrostatic
步骤710:于导电垫片102的下方提供导电层231,其中导电层231可包含第一导电部分352、隔绝部分353以及第二导电部分354。隔绝部分353是由第一导电部分352与第二导电部分354所包围,以及第一导电部分352是电连接于导电垫片102与第二导电部分354之间。Step 710 : Provide a
步骤720:将电性连接部242耦接于导电层231的第一导电部分352与一箝制元件(二极管D1)之间,其中该箝制元件用以箝制该静电放电事件。Step 720 : Coupling the
步骤730:将电性连接部243耦接于导电层231的第二导电部分354与核心电路104之间。Step 730 : Coupling the
于一实作范例中,当该静电放电事件发生时,该方法可利用导电层231的第一导电部分352接收因应该静电放电事件所产生的一静电放电电流。此外,在该静电放电电流经由导电层231的第二导电部分354与电性连接部243流入核心电路104之前,该方法可利用电性连接部242将该静电放电电流导引/传导至该箝制元件。由于熟习技艺者经由阅读图1~图6的相关说明之后,应可了解图7所示的流程中每一步骤的操作细节,故进一步的说明在此便不再赘述。In an implementation example, when the ESD event occurs, the method may utilize the first
综上所述,本发明所提供的静电放电防护机制可通过导电路径的设计(例如:导电层/金属层的布图规划/布局设计),优先将静电放电电流导引至箝制元件,进而防止静电放电电流直接流入核心电路。此外,本发明所提供的静电放电防护机制可具有较高的电流承受能力(其可避免/减少电迁移效应)以及较小的寄生电容。To sum up, the ESD protection mechanism provided by the present invention can preferentially guide the ESD current to the clamping element through the design of the conductive path (for example, the layout planning/layout design of the conductive layer/metal layer), thereby preventing the Electrostatic discharge current flows directly into the core circuitry. In addition, the ESD protection mechanism provided by the present invention may have higher current carrying capability (which may avoid/reduce electromigration effects) and smaller parasitic capacitance.
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